test/tools/llvm-mca/X86/Haswell/cmpxchg16b.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=haswell -timeline -timeline-max-iterations=3 -dispatch-stats < %s | FileCheck %s
   3
   4 cmpxchg16b (%rsi)
   5
   6 # CHECK:      Iterations:        100
   7 # CHECK-NEXT: Instructions:      100
   8 # CHECK-NEXT: Total Cycles:      2203
   9 # CHECK-NEXT: Total uOps:        1900
  10
  11 # CHECK:      Dispatch Width:    4
  12 # CHECK-NEXT: uOps Per Cycle:    0.86
  13 # CHECK-NEXT: IPC:               0.05
  14 # CHECK-NEXT: Block RThroughput: 4.8
  15
  16 # CHECK:      Instruction Info:
  17 # CHECK-NEXT: [1]: #uOps
  18 # CHECK-NEXT: [2]: Latency
  19 # CHECK-NEXT: [3]: RThroughput
  20 # CHECK-NEXT: [4]: MayLoad
  21 # CHECK-NEXT: [5]: MayStore
  22 # CHECK-NEXT: [6]: HasSideEffects (U)
  23
  24 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  25 # CHECK-NEXT:  19     22    4.00    *      *            cmpxchg16b      (%rsi)
  26
  27 # CHECK:      Dynamic Dispatch Stall Cycles:
  28 # CHECK-NEXT: RAT     - Register unavailable:                      0
  29 # CHECK-NEXT: RCU     - Retire tokens unavailable:                 1487  (67.5%)
  30 # CHECK-NEXT: SCHEDQ  - Scheduler full:                            0
  31 # CHECK-NEXT: LQ      - Load queue full:                           0
  32 # CHECK-NEXT: SQ      - Store queue full:                          0
  33 # CHECK-NEXT: GROUP   - Static restrictions on the dispatch group: 0
  34
  35 # CHECK:      Dispatch Logic - number of cycles where we saw N micro opcodes dispatched:
  36 # CHECK-NEXT: [# dispatched], [# cycles]
  37 # CHECK-NEXT:  0,              1703  (77.3%)
  38 # CHECK-NEXT:  3,              100  (4.5%)
  39 # CHECK-NEXT:  4,              400  (18.2%)
  40
  41 # CHECK:      Resources:
  42 # CHECK-NEXT: [0]   - HWDivider
  43 # CHECK-NEXT: [1]   - HWFPDivider
  44 # CHECK-NEXT: [2]   - HWPort0
  45 # CHECK-NEXT: [3]   - HWPort1
  46 # CHECK-NEXT: [4]   - HWPort2
  47 # CHECK-NEXT: [5]   - HWPort3
  48 # CHECK-NEXT: [6]   - HWPort4
  49 # CHECK-NEXT: [7]   - HWPort5
  50 # CHECK-NEXT: [8]   - HWPort6
  51 # CHECK-NEXT: [9]   - HWPort7
  52
  53 # CHECK:      Resource pressure per iteration:
  54 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]
  55 # CHECK-NEXT:  -      -     2.00   6.00   0.66   0.67   1.00   4.00   4.00   0.67
  56
  57 # CHECK:      Resource pressure by instruction:
  58 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
  59 # CHECK-NEXT:  -      -     2.00   6.00   0.66   0.67   1.00   4.00   4.00   0.67   cmpxchg16b  (%rsi)
  60
  61 # CHECK:      Timeline view:
  62 # CHECK-NEXT:                     0123456789          0123456789          0123456789
  63 # CHECK-NEXT: Index     0123456789          0123456789          0123456789          012345678
  64
  65 # CHECK:      [0,0]     DeeeeeeeeeeeeeeeeeeeeeeER.    .    .    .    .    .    .    .    .  .   cmpxchg16b      (%rsi)
  66 # CHECK-NEXT: [1,0]     .    D=================eeeeeeeeeeeeeeeeeeeeeeER   .    .    .    .  .   cmpxchg16b      (%rsi)
  67 # CHECK-NEXT: [2,0]     .    .    D==================================eeeeeeeeeeeeeeeeeeeeeeER   cmpxchg16b      (%rsi)
  68
  69 # CHECK:      Average Wait times (based on the timeline view):
  70 # CHECK-NEXT: [0]: Executions
  71 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
  72 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
  73 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
  74
  75 # CHECK:            [0]    [1]    [2]    [3]
  76 # CHECK-NEXT: 0.     3     18.0   0.3    0.0       cmpxchg16b   (%rsi)