test/tools/llvm-mca/X86/intel-syntax.s

   1 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
   2 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false                       < %s | FileCheck %s -check-prefixes=ALL,INTEL
   3 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=0 < %s | FileCheck %s -check-prefixes=ALL,ATT
   4 # RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -resource-pressure=false -output-asm-variant=1 < %s | FileCheck %s -check-prefixes=ALL,INTEL
   5
   6   .intel_syntax noprefix
   7   mov   eax, 1
   8   mov   ebx, 0xff
   9   imul  esi, edi
  10   lea   eax, [rsi + rdi]
  11
  12 # ALL:        Iterations:        100
  13 # ALL-NEXT:   Instructions:      400
  14 # ALL-NEXT:   Total Cycles:      305
  15 # ALL-NEXT:   Total uOps:        500
  16
  17 # ALL:        Dispatch Width:    2
  18 # ALL-NEXT:   uOps Per Cycle:    1.64
  19 # ALL-NEXT:   IPC:               1.31
  20 # ALL-NEXT:   Block RThroughput: 2.5
  21
  22 # ALL:        Instruction Info:
  23 # ALL-NEXT:   [1]: #uOps
  24 # ALL-NEXT:   [2]: Latency
  25 # ALL-NEXT:   [3]: RThroughput
  26 # ALL-NEXT:   [4]: MayLoad
  27 # ALL-NEXT:   [5]: MayStore
  28 # ALL-NEXT:   [6]: HasSideEffects (U)
  29
  30 # ALL:        [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
  31
  32 # ATT-NEXT:    1      1     0.50                        movl    $1, %eax
  33 # ATT-NEXT:    1      1     0.50                        movl    $255, %ebx
  34 # ATT-NEXT:    2      3     1.00                        imull   %edi, %esi
  35 # ATT-NEXT:    1      1     0.50                        leal    (%rsi,%rdi), %eax
  36
  37 # INTEL-NEXT:  1      1     0.50                        mov     eax, 1
  38 # INTEL-NEXT:  1      1     0.50                        mov     ebx, 255
  39 # INTEL-NEXT:  2      3     1.00                        imul    esi, edi
  40 # INTEL-NEXT:  1      1     0.50                        lea     eax, [rsi + rdi]