[PowerPC] Generate Power9 extswsli extend sign and shift immediate instruction
[llvm-core.git] / lib / Target / PowerPC / PPCSubtarget.cpp
blobc0cbfd779cb908137374fa8682acbd5bdca92677
1 //===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the PPC specific subclass of TargetSubtargetInfo.
12 //===----------------------------------------------------------------------===//
14 #include "PPCSubtarget.h"
15 #include "PPC.h"
16 #include "PPCRegisterInfo.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineScheduler.h"
20 #include "llvm/IR/Attributes.h"
21 #include "llvm/IR/Function.h"
22 #include "llvm/IR/GlobalValue.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include <cstdlib>
28 using namespace llvm;
30 #define DEBUG_TYPE "ppc-subtarget"
32 #define GET_SUBTARGETINFO_TARGET_DESC
33 #define GET_SUBTARGETINFO_CTOR
34 #include "PPCGenSubtargetInfo.inc"
36 static cl::opt<bool> UseSubRegLiveness("ppc-track-subreg-liveness",
37 cl::desc("Enable subregister liveness tracking for PPC"), cl::Hidden);
39 static cl::opt<bool> QPXStackUnaligned("qpx-stack-unaligned",
40 cl::desc("Even when QPX is enabled the stack is not 32-byte aligned"),
41 cl::Hidden);
43 PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU,
44 StringRef FS) {
45 initializeEnvironment();
46 initSubtargetFeatures(CPU, FS);
47 return *this;
50 PPCSubtarget::PPCSubtarget(const Triple &TT, const std::string &CPU,
51 const std::string &FS, const PPCTargetMachine &TM)
52 : PPCGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT),
53 IsPPC64(TargetTriple.getArch() == Triple::ppc64 ||
54 TargetTriple.getArch() == Triple::ppc64le),
55 TM(TM), FrameLowering(initializeSubtargetDependencies(CPU, FS)),
56 InstrInfo(*this), TLInfo(TM, *this) {}
58 void PPCSubtarget::initializeEnvironment() {
59 StackAlignment = 16;
60 DarwinDirective = PPC::DIR_NONE;
61 HasMFOCRF = false;
62 Has64BitSupport = false;
63 Use64BitRegs = false;
64 UseCRBits = false;
65 HasHardFloat = false;
66 HasAltivec = false;
67 HasSPE = false;
68 HasFPU = false;
69 HasQPX = false;
70 HasVSX = false;
71 HasP8Vector = false;
72 HasP8Altivec = false;
73 HasP8Crypto = false;
74 HasP9Vector = false;
75 HasP9Altivec = false;
76 HasFCPSGN = false;
77 HasFSQRT = false;
78 HasFRE = false;
79 HasFRES = false;
80 HasFRSQRTE = false;
81 HasFRSQRTES = false;
82 HasRecipPrec = false;
83 HasSTFIWX = false;
84 HasLFIWAX = false;
85 HasFPRND = false;
86 HasFPCVT = false;
87 HasISEL = false;
88 HasBPERMD = false;
89 HasExtDiv = false;
90 HasCMPB = false;
91 HasLDBRX = false;
92 IsBookE = false;
93 HasOnlyMSYNC = false;
94 IsPPC4xx = false;
95 IsPPC6xx = false;
96 IsE500 = false;
97 FeatureMFTB = false;
98 DeprecatedDST = false;
99 HasLazyResolverStubs = false;
100 HasICBT = false;
101 HasInvariantFunctionDescriptors = false;
102 HasPartwordAtomics = false;
103 HasDirectMove = false;
104 IsQPXStackUnaligned = false;
105 HasHTM = false;
106 HasFusion = false;
107 HasFloat128 = false;
108 IsISA3_0 = false;
109 UseLongCalls = false;
110 SecurePlt = false;
112 HasPOPCNTD = POPCNTD_Unavailable;
115 void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
116 // Determine default and user specified characteristics
117 std::string CPUName = CPU;
118 if (CPUName.empty() || CPU == "generic") {
119 // If cross-compiling with -march=ppc64le without -mcpu
120 if (TargetTriple.getArch() == Triple::ppc64le)
121 CPUName = "ppc64le";
122 else
123 CPUName = "generic";
126 // Initialize scheduling itinerary for the specified CPU.
127 InstrItins = getInstrItineraryForCPU(CPUName);
129 // Parse features string.
130 ParseSubtargetFeatures(CPUName, FS);
132 // If the user requested use of 64-bit regs, but the cpu selected doesn't
133 // support it, ignore.
134 if (IsPPC64 && has64BitSupport())
135 Use64BitRegs = true;
137 // Set up darwin-specific properties.
138 if (isDarwin())
139 HasLazyResolverStubs = true;
141 if (HasSPE && IsPPC64)
142 report_fatal_error( "SPE is only supported for 32-bit targets.\n", false);
143 if (HasSPE && (HasAltivec || HasQPX || HasVSX || HasFPU))
144 report_fatal_error(
145 "SPE and traditional floating point cannot both be enabled.\n", false);
147 // If not SPE, set standard FPU
148 if (!HasSPE)
149 HasFPU = true;
151 // QPX requires a 32-byte aligned stack. Note that we need to do this if
152 // we're compiling for a BG/Q system regardless of whether or not QPX
153 // is enabled because external functions will assume this alignment.
154 IsQPXStackUnaligned = QPXStackUnaligned;
155 StackAlignment = getPlatformStackAlignment();
157 // Determine endianness.
158 // FIXME: Part of the TargetMachine.
159 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
162 /// Return true if accesses to the specified global have to go through a dyld
163 /// lazy resolution stub. This means that an extra load is required to get the
164 /// address of the global.
165 bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV) const {
166 if (!HasLazyResolverStubs)
167 return false;
168 if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
169 return true;
170 // 32 bit macho has no relocation for a-b if a is undefined, even if b is in
171 // the section that is being relocated. This means we have to use o load even
172 // for GVs that are known to be local to the dso.
173 if (GV->isDeclarationForLinker() || GV->hasCommonLinkage())
174 return true;
175 return false;
178 bool PPCSubtarget::enableMachineScheduler() const {
179 return true;
182 // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
183 bool PPCSubtarget::enablePostRAScheduler() const { return true; }
185 PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const {
186 return TargetSubtargetInfo::ANTIDEP_ALL;
189 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
190 CriticalPathRCs.clear();
191 CriticalPathRCs.push_back(isPPC64() ?
192 &PPC::G8RCRegClass : &PPC::GPRCRegClass);
195 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
196 unsigned NumRegionInstrs) const {
197 // The GenericScheduler that we use defaults to scheduling bottom up only.
198 // We want to schedule from both the top and the bottom and so we set
199 // OnlyBottomUp to false.
200 // We want to do bi-directional scheduling since it provides a more balanced
201 // schedule leading to better performance.
202 Policy.OnlyBottomUp = false;
203 // Spilling is generally expensive on all PPC cores, so always enable
204 // register-pressure tracking.
205 Policy.ShouldTrackPressure = true;
208 bool PPCSubtarget::useAA() const {
209 return true;
212 bool PPCSubtarget::enableSubRegLiveness() const {
213 return UseSubRegLiveness;
216 unsigned char
217 PPCSubtarget::classifyGlobalReference(const GlobalValue *GV) const {
218 // Note that currently we don't generate non-pic references.
219 // If a caller wants that, this will have to be updated.
221 // Large code model always uses the TOC even for local symbols.
222 if (TM.getCodeModel() == CodeModel::Large)
223 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
225 if (TM.shouldAssumeDSOLocal(*GV->getParent(), GV))
226 return PPCII::MO_PIC_FLAG;
227 return PPCII::MO_PIC_FLAG | PPCII::MO_NLP_FLAG;
230 bool PPCSubtarget::isELFv2ABI() const { return TM.isELFv2ABI(); }
231 bool PPCSubtarget::isPPC64() const { return TM.isPPC64(); }