1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3 declare i1 @llvm.amdgcn.class.f32(float, i32)
5 ; Produces error after adding an implicit def to v_cndmask_b32
7 ; GCN-LABEL: {{^}}vcc_shrink_vcc_def:
8 ; GCN: v_cmp_eq_u32_e64 vcc, s{{[0-9]+}}, 0{{$}}
9 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
10 ; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
11 define amdgpu_kernel void @vcc_shrink_vcc_def(float %arg, i32 %arg1, float %arg2, i32 %arg3) {
13 %tmp = icmp sgt i32 %arg1, 4
14 %c = icmp eq i32 %arg3, 0
15 %tmp4 = select i1 %c, float %arg, float 1.000000e+00
16 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
17 %tmp6 = fcmp olt float %arg2, 1.000000e+00
18 %tmp7 = fcmp olt float %arg, %tmp4
19 %tmp8 = and i1 %tmp5, %tmp6
20 %tmp9 = and i1 %tmp8, %tmp7
21 br i1 %tmp9, label %bb1, label %bb2
24 store volatile i32 0, i32 addrspace(1)* undef
31 ; The undef flag on the condition src must be preserved on the
32 ; implicit vcc use to avoid verifier errors.
34 ; GCN-LABEL: {{^}}preserve_condition_undef_flag:
36 ; GCN: v_cndmask_b32_e32 v{{[0-9]+}}, 1.0, v{{[0-9]+}}, vcc
37 ; GCN: v_cndmask_b32_e64 v0, 0, 1, s{{\[[0-9]+:[0-9]+\]}}
38 define amdgpu_kernel void @preserve_condition_undef_flag(float %arg, i32 %arg1, float %arg2) {
40 %tmp = icmp sgt i32 %arg1, 4
41 %undef = call i1 @llvm.amdgcn.class.f32(float undef, i32 undef)
42 %tmp4 = select i1 %undef, float %arg, float 1.000000e+00
43 %tmp5 = fcmp ogt float %arg2, 0.000000e+00
44 %tmp6 = fcmp olt float %arg2, 1.000000e+00
45 %tmp7 = fcmp olt float %arg, %tmp4
46 %tmp8 = and i1 %tmp5, %tmp6
47 %tmp9 = and i1 %tmp8, %tmp7
48 br i1 %tmp9, label %bb1, label %bb2
51 store volatile i32 0, i32 addrspace(1)* undef