| blob | fb16faa30a946447d2d75bc0b59458331ba1d8a3 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX
5 ; fold (sra 0, x) -> 0
6 define <4 x i32> @combine_vec_ashr_zero(<4 x i32> %x) {
7 ; SSE-LABEL: combine_vec_ashr_zero:
8 ; SSE: # BB#0:
9 ; SSE-NEXT: xorps %xmm0, %xmm0
10 ; SSE-NEXT: retq
11 ;
12 ; AVX-LABEL: combine_vec_ashr_zero:
13 ; AVX: # BB#0:
14 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
15 ; AVX-NEXT: retq
16 %1 = ashr <4 x i32> zeroinitializer, %x
17 ret <4 x i32> %1
18 }
20 ; fold (sra -1, x) -> -1
21 define <4 x i32> @combine_vec_ashr_allones(<4 x i32> %x) {
22 ; SSE-LABEL: combine_vec_ashr_allones:
23 ; SSE: # BB#0:
24 ; SSE-NEXT: pcmpeqd %xmm0, %xmm0
25 ; SSE-NEXT: retq
26 ;
27 ; AVX-LABEL: combine_vec_ashr_allones:
28 ; AVX: # BB#0:
29 ; AVX-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
30 ; AVX-NEXT: retq
31 %1 = ashr <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, %x
32 ret <4 x i32> %1
33 }
35 ; fold (sra x, c >= size(x)) -> undef
36 define <4 x i32> @combine_vec_ashr_outofrange0(<4 x i32> %x) {
37 ; SSE-LABEL: combine_vec_ashr_outofrange0:
38 ; SSE: # BB#0:
39 ; SSE-NEXT: retq
40 ;
41 ; AVX-LABEL: combine_vec_ashr_outofrange0:
42 ; AVX: # BB#0:
43 ; AVX-NEXT: retq
44 %1 = ashr <4 x i32> %x, <i32 33, i32 33, i32 33, i32 33>
45 ret <4 x i32> %1
46 }
48 define <4 x i32> @combine_vec_ashr_outofrange1(<4 x i32> %x) {
49 ; SSE-LABEL: combine_vec_ashr_outofrange1:
50 ; SSE: # BB#0:
51 ; SSE-NEXT: retq
52 ;
53 ; AVX-LABEL: combine_vec_ashr_outofrange1:
54 ; AVX: # BB#0:
55 ; AVX-NEXT: retq
56 %1 = ashr <4 x i32> %x, <i32 33, i32 34, i32 35, i32 36>
57 ret <4 x i32> %1
58 }
60 ; fold (sra x, 0) -> x
61 define <4 x i32> @combine_vec_ashr_by_zero(<4 x i32> %x) {
62 ; SSE-LABEL: combine_vec_ashr_by_zero:
63 ; SSE: # BB#0:
64 ; SSE-NEXT: retq
65 ;
66 ; AVX-LABEL: combine_vec_ashr_by_zero:
67 ; AVX: # BB#0:
68 ; AVX-NEXT: retq
69 %1 = ashr <4 x i32> %x, zeroinitializer
70 ret <4 x i32> %1
71 }
73 ; fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
74 define <4 x i32> @combine_vec_ashr_ashr0(<4 x i32> %x) {
75 ; SSE-LABEL: combine_vec_ashr_ashr0:
76 ; SSE: # BB#0:
77 ; SSE-NEXT: psrad $6, %xmm0
78 ; SSE-NEXT: retq
79 ;
80 ; AVX-LABEL: combine_vec_ashr_ashr0:
81 ; AVX: # BB#0:
82 ; AVX-NEXT: vpsrad $6, %xmm0, %xmm0
83 ; AVX-NEXT: retq
84 %1 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2>
85 %2 = ashr <4 x i32> %1, <i32 4, i32 4, i32 4, i32 4>
86 ret <4 x i32> %2
87 }
89 define <4 x i32> @combine_vec_ashr_ashr1(<4 x i32> %x) {
90 ; SSE-LABEL: combine_vec_ashr_ashr1:
91 ; SSE: # BB#0:
92 ; SSE-NEXT: movdqa %xmm0, %xmm1
93 ; SSE-NEXT: psrad $10, %xmm1
94 ; SSE-NEXT: movdqa %xmm0, %xmm2
95 ; SSE-NEXT: psrad $6, %xmm2
96 ; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
97 ; SSE-NEXT: movdqa %xmm0, %xmm1
98 ; SSE-NEXT: psrad $8, %xmm1
99 ; SSE-NEXT: psrad $4, %xmm0
100 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
101 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
102 ; SSE-NEXT: retq
103 ;
104 ; AVX-LABEL: combine_vec_ashr_ashr1:
105 ; AVX: # BB#0:
106 ; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
107 ; AVX-NEXT: retq
108 %1 = ashr <4 x i32> %x, <i32 0, i32 1, i32 2, i32 3>
109 %2 = ashr <4 x i32> %1, <i32 4, i32 5, i32 6, i32 7>
110 ret <4 x i32> %2
111 }
113 define <4 x i32> @combine_vec_ashr_ashr2(<4 x i32> %x) {
114 ; SSE-LABEL: combine_vec_ashr_ashr2:
115 ; SSE: # BB#0:
116 ; SSE-NEXT: psrad $31, %xmm0
117 ; SSE-NEXT: retq
118 ;
119 ; AVX-LABEL: combine_vec_ashr_ashr2:
120 ; AVX: # BB#0:
121 ; AVX-NEXT: vpsrad $31, %xmm0, %xmm0
122 ; AVX-NEXT: retq
123 %1 = ashr <4 x i32> %x, <i32 17, i32 18, i32 19, i32 20>
124 %2 = ashr <4 x i32> %1, <i32 25, i32 26, i32 27, i32 28>
125 ret <4 x i32> %2
126 }
128 define <4 x i32> @combine_vec_ashr_ashr3(<4 x i32> %x) {
129 ; SSE-LABEL: combine_vec_ashr_ashr3:
130 ; SSE: # BB#0:
131 ; SSE-NEXT: movdqa %xmm0, %xmm1
132 ; SSE-NEXT: psrad $27, %xmm1
133 ; SSE-NEXT: movdqa %xmm0, %xmm2
134 ; SSE-NEXT: psrad $5, %xmm2
135 ; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
136 ; SSE-NEXT: movdqa %xmm0, %xmm1
137 ; SSE-NEXT: psrad $31, %xmm1
138 ; SSE-NEXT: psrad $1, %xmm0
139 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
140 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
141 ; SSE-NEXT: movdqa %xmm0, %xmm1
142 ; SSE-NEXT: psrad $10, %xmm1
143 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm0[4,5,6,7]
144 ; SSE-NEXT: psrad $31, %xmm0
145 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
146 ; SSE-NEXT: retq
147 ;
148 ; AVX-LABEL: combine_vec_ashr_ashr3:
149 ; AVX: # BB#0:
150 ; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
151 ; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
152 ; AVX-NEXT: retq
153 %1 = ashr <4 x i32> %x, <i32 1, i32 5, i32 50, i32 27>
154 %2 = ashr <4 x i32> %1, <i32 33, i32 10, i32 33, i32 0>
155 ret <4 x i32> %2
156 }
158 ; fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))).
159 define <4 x i32> @combine_vec_ashr_trunc_and(<4 x i32> %x, <4 x i64> %y) {
160 ; SSE-LABEL: combine_vec_ashr_trunc_and:
161 ; SSE: # BB#0:
162 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
163 ; SSE-NEXT: andps {{.*}}(%rip), %xmm1
164 ; SSE-NEXT: movaps %xmm1, %xmm2
165 ; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
166 ; SSE-NEXT: movdqa %xmm0, %xmm3
167 ; SSE-NEXT: psrad %xmm2, %xmm3
168 ; SSE-NEXT: movaps %xmm1, %xmm2
169 ; SSE-NEXT: psrlq $32, %xmm2
170 ; SSE-NEXT: movdqa %xmm0, %xmm4
171 ; SSE-NEXT: psrad %xmm2, %xmm4
172 ; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
173 ; SSE-NEXT: pxor %xmm2, %xmm2
174 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
175 ; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
176 ; SSE-NEXT: movdqa %xmm0, %xmm2
177 ; SSE-NEXT: psrad %xmm1, %xmm2
178 ; SSE-NEXT: psrad %xmm3, %xmm0
179 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
180 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
181 ; SSE-NEXT: retq
182 ;
183 ; AVX-LABEL: combine_vec_ashr_trunc_and:
184 ; AVX: # BB#0:
185 ; AVX-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
186 ; AVX-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
187 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm1, %xmm1
188 ; AVX-NEXT: vpsravd %xmm1, %xmm0, %xmm0
189 ; AVX-NEXT: vzeroupper
190 ; AVX-NEXT: retq
191 %1 = and <4 x i64> %y, <i64 15, i64 255, i64 4095, i64 65535>
192 %2 = trunc <4 x i64> %1 to <4 x i32>
193 %3 = ashr <4 x i32> %x, %2
194 ret <4 x i32> %3
195 }
197 ; fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
198 ; if c1 is equal to the number of bits the trunc removes
199 define <4 x i32> @combine_vec_ashr_trunc_lshr(<4 x i64> %x) {
200 ; SSE-LABEL: combine_vec_ashr_trunc_lshr:
201 ; SSE: # BB#0:
202 ; SSE-NEXT: psrlq $32, %xmm1
203 ; SSE-NEXT: psrlq $32, %xmm0
204 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
205 ; SSE-NEXT: movaps %xmm0, %xmm2
206 ; SSE-NEXT: movaps %xmm0, %xmm1
207 ; SSE-NEXT: psrad $2, %xmm1
208 ; SSE-NEXT: blendpd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
209 ; SSE-NEXT: psrad $3, %xmm0
210 ; SSE-NEXT: psrad $1, %xmm2
211 ; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
212 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
213 ; SSE-NEXT: movdqa %xmm1, %xmm0
214 ; SSE-NEXT: retq
215 ;
216 ; AVX-LABEL: combine_vec_ashr_trunc_lshr:
217 ; AVX: # BB#0:
218 ; AVX-NEXT: vpsrlq $32, %ymm0, %ymm0
219 ; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
220 ; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
221 ; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
222 ; AVX-NEXT: vzeroupper
223 ; AVX-NEXT: retq
224 %1 = lshr <4 x i64> %x, <i64 32, i64 32, i64 32, i64 32>
225 %2 = trunc <4 x i64> %1 to <4 x i32>
226 %3 = ashr <4 x i32> %2, <i32 0, i32 1, i32 2, i32 3>
227 ret <4 x i32> %3
228 }
230 ; fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2))
231 ; if c1 is equal to the number of bits the trunc removes
232 define <4 x i32> @combine_vec_ashr_trunc_ashr(<4 x i64> %x) {
233 ; SSE-LABEL: combine_vec_ashr_trunc_ashr:
234 ; SSE: # BB#0:
235 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
236 ; SSE-NEXT: psrad $31, %xmm1
237 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm2[0,1],xmm1[2,3],xmm2[4,5],xmm1[6,7]
238 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,3],xmm1[0,2]
239 ; SSE-NEXT: movaps %xmm0, %xmm2
240 ; SSE-NEXT: movaps %xmm0, %xmm1
241 ; SSE-NEXT: psrad $2, %xmm1
242 ; SSE-NEXT: blendpd {{.*#+}} xmm1 = xmm0[0],xmm1[1]
243 ; SSE-NEXT: psrad $3, %xmm0
244 ; SSE-NEXT: psrad $1, %xmm2
245 ; SSE-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm0[4,5,6,7]
246 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
247 ; SSE-NEXT: movdqa %xmm1, %xmm0
248 ; SSE-NEXT: retq
249 ;
250 ; AVX-LABEL: combine_vec_ashr_trunc_ashr:
251 ; AVX: # BB#0:
252 ; AVX-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[1,3,2,3,5,7,6,7]
253 ; AVX-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
254 ; AVX-NEXT: vpsravd {{.*}}(%rip), %xmm0, %xmm0
255 ; AVX-NEXT: vzeroupper
256 ; AVX-NEXT: retq
257 %1 = ashr <4 x i64> %x, <i64 32, i64 32, i64 32, i64 32>
258 %2 = trunc <4 x i64> %1 to <4 x i32>
259 %3 = ashr <4 x i32> %2, <i32 0, i32 1, i32 2, i32 3>
260 ret <4 x i32> %3
261 }
263 ; If the sign bit is known to be zero, switch this to a SRL.
264 define <4 x i32> @combine_vec_ashr_positive(<4 x i32> %x, <4 x i32> %y) {
265 ; SSE-LABEL: combine_vec_ashr_positive:
266 ; SSE: # BB#0:
267 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
268 ; SSE-NEXT: movdqa %xmm1, %xmm2
269 ; SSE-NEXT: psrldq {{.*#+}} xmm2 = xmm2[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
270 ; SSE-NEXT: movdqa %xmm0, %xmm3
271 ; SSE-NEXT: psrld %xmm2, %xmm3
272 ; SSE-NEXT: movdqa %xmm1, %xmm2
273 ; SSE-NEXT: psrlq $32, %xmm2
274 ; SSE-NEXT: movdqa %xmm0, %xmm4
275 ; SSE-NEXT: psrld %xmm2, %xmm4
276 ; SSE-NEXT: pblendw {{.*#+}} xmm4 = xmm4[0,1,2,3],xmm3[4,5,6,7]
277 ; SSE-NEXT: pxor %xmm2, %xmm2
278 ; SSE-NEXT: pmovzxdq {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero
279 ; SSE-NEXT: punpckhdq {{.*#+}} xmm1 = xmm1[2],xmm2[2],xmm1[3],xmm2[3]
280 ; SSE-NEXT: movdqa %xmm0, %xmm2
281 ; SSE-NEXT: psrld %xmm1, %xmm2
282 ; SSE-NEXT: psrld %xmm3, %xmm0
283 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
284 ; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3],xmm0[4,5],xmm4[6,7]
285 ; SSE-NEXT: retq
286 ;
287 ; AVX-LABEL: combine_vec_ashr_positive:
288 ; AVX: # BB#0:
289 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
290 ; AVX-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
291 ; AVX-NEXT: retq
292 %1 = and <4 x i32> %x, <i32 15, i32 255, i32 4095, i32 65535>
293 %2 = ashr <4 x i32> %1, %y
294 ret <4 x i32> %2
295 }
297 define <4 x i32> @combine_vec_ashr_positive_splat(<4 x i32> %x, <4 x i32> %y) {
298 ; SSE-LABEL: combine_vec_ashr_positive_splat:
299 ; SSE: # BB#0:
300 ; SSE-NEXT: xorps %xmm0, %xmm0
301 ; SSE-NEXT: retq
302 ;
303 ; AVX-LABEL: combine_vec_ashr_positive_splat:
304 ; AVX: # BB#0:
305 ; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm0
306 ; AVX-NEXT: retq
307 %1 = and <4 x i32> %x, <i32 1023, i32 1023, i32 1023, i32 1023>
308 %2 = ashr <4 x i32> %1, <i32 10, i32 10, i32 10, i32 10>
309 ret <4 x i32> %2
310 }