| blob | c399ea077ccc45e3e77b4a60e9d42ad4c02066ed |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512F
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512BW
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX512 --check-prefix=AVX512DQ
9 ;
10 ; add
11 ;
13 define <4 x i32> @trunc_add_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
14 ; SSE-LABEL: trunc_add_v4i64_v4i32:
15 ; SSE: # BB#0:
16 ; SSE-NEXT: paddq %xmm3, %xmm1
17 ; SSE-NEXT: paddq %xmm2, %xmm0
18 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
19 ; SSE-NEXT: retq
20 ;
21 ; AVX1-LABEL: trunc_add_v4i64_v4i32:
22 ; AVX1: # BB#0:
23 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
24 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
25 ; AVX1-NEXT: vpaddq %xmm2, %xmm3, %xmm2
26 ; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0
27 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
28 ; AVX1-NEXT: vzeroupper
29 ; AVX1-NEXT: retq
30 ;
31 ; AVX2-LABEL: trunc_add_v4i64_v4i32:
32 ; AVX2: # BB#0:
33 ; AVX2-NEXT: vpaddq %ymm1, %ymm0, %ymm0
34 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
35 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
36 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
37 ; AVX2-NEXT: vzeroupper
38 ; AVX2-NEXT: retq
39 ;
40 ; AVX512-LABEL: trunc_add_v4i64_v4i32:
41 ; AVX512: # BB#0:
42 ; AVX512-NEXT: vpaddq %ymm1, %ymm0, %ymm0
43 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
44 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
45 ; AVX512-NEXT: vzeroupper
46 ; AVX512-NEXT: retq
47 %1 = add <4 x i64> %a0, %a1
48 %2 = trunc <4 x i64> %1 to <4 x i32>
49 ret <4 x i32> %2
50 }
52 define <8 x i16> @trunc_add_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
53 ; SSE-LABEL: trunc_add_v8i64_v8i16:
54 ; SSE: # BB#0:
55 ; SSE-NEXT: paddq %xmm6, %xmm2
56 ; SSE-NEXT: paddq %xmm7, %xmm3
57 ; SSE-NEXT: paddq %xmm4, %xmm0
58 ; SSE-NEXT: paddq %xmm5, %xmm1
59 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
60 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
61 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
62 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
63 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
64 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
65 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
66 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
67 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
68 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
69 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
70 ; SSE-NEXT: retq
71 ;
72 ; AVX1-LABEL: trunc_add_v8i64_v8i16:
73 ; AVX1: # BB#0:
74 ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm4
75 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
76 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
77 ; AVX1-NEXT: vpaddq %xmm2, %xmm0, %xmm0
78 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm2
79 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
80 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
81 ; AVX1-NEXT: vpaddq %xmm3, %xmm1, %xmm1
82 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
83 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
84 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
85 ; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
86 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
87 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0],xmm3[1,2,3],xmm4[4],xmm3[5,6,7]
88 ; AVX1-NEXT: vpackusdw %xmm0, %xmm2, %xmm0
89 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
90 ; AVX1-NEXT: vzeroupper
91 ; AVX1-NEXT: retq
92 ;
93 ; AVX2-LABEL: trunc_add_v8i64_v8i16:
94 ; AVX2: # BB#0:
95 ; AVX2-NEXT: vpaddq %ymm3, %ymm1, %ymm1
96 ; AVX2-NEXT: vpaddq %ymm2, %ymm0, %ymm0
97 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
98 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
99 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
100 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
101 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
102 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
103 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
104 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
105 ; AVX2-NEXT: vzeroupper
106 ; AVX2-NEXT: retq
107 ;
108 ; AVX512-LABEL: trunc_add_v8i64_v8i16:
109 ; AVX512: # BB#0:
110 ; AVX512-NEXT: vpaddq %zmm1, %zmm0, %zmm0
111 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
112 ; AVX512-NEXT: vzeroupper
113 ; AVX512-NEXT: retq
114 %1 = add <8 x i64> %a0, %a1
115 %2 = trunc <8 x i64> %1 to <8 x i16>
116 ret <8 x i16> %2
117 }
119 define <8 x i16> @trunc_add_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
120 ; SSE-LABEL: trunc_add_v8i32_v8i16:
121 ; SSE: # BB#0:
122 ; SSE-NEXT: paddd %xmm2, %xmm0
123 ; SSE-NEXT: paddd %xmm3, %xmm1
124 ; SSE-NEXT: pslld $16, %xmm1
125 ; SSE-NEXT: psrad $16, %xmm1
126 ; SSE-NEXT: pslld $16, %xmm0
127 ; SSE-NEXT: psrad $16, %xmm0
128 ; SSE-NEXT: packssdw %xmm1, %xmm0
129 ; SSE-NEXT: retq
130 ;
131 ; AVX1-LABEL: trunc_add_v8i32_v8i16:
132 ; AVX1: # BB#0:
133 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm2
134 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
135 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
136 ; AVX1-NEXT: vpaddd %xmm1, %xmm0, %xmm0
137 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
138 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
139 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
140 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
141 ; AVX1-NEXT: vzeroupper
142 ; AVX1-NEXT: retq
143 ;
144 ; AVX2-LABEL: trunc_add_v8i32_v8i16:
145 ; AVX2: # BB#0:
146 ; AVX2-NEXT: vpaddd %ymm1, %ymm0, %ymm0
147 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
148 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
149 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
150 ; AVX2-NEXT: vzeroupper
151 ; AVX2-NEXT: retq
152 ;
153 ; AVX512-LABEL: trunc_add_v8i32_v8i16:
154 ; AVX512: # BB#0:
155 ; AVX512-NEXT: vpaddd %ymm1, %ymm0, %ymm0
156 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
157 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
158 ; AVX512-NEXT: vzeroupper
159 ; AVX512-NEXT: retq
160 %1 = add <8 x i32> %a0, %a1
161 %2 = trunc <8 x i32> %1 to <8 x i16>
162 ret <8 x i16> %2
163 }
165 define <16 x i8> @trunc_add_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
166 ; SSE-LABEL: trunc_add_v16i64_v16i8:
167 ; SSE: # BB#0:
168 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm0
169 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm1
170 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm2
171 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm3
172 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm4
173 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm5
174 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm6
175 ; SSE-NEXT: paddq {{[0-9]+}}(%rsp), %xmm7
176 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
177 ; SSE-NEXT: pand %xmm8, %xmm7
178 ; SSE-NEXT: pand %xmm8, %xmm6
179 ; SSE-NEXT: packuswb %xmm7, %xmm6
180 ; SSE-NEXT: pand %xmm8, %xmm5
181 ; SSE-NEXT: pand %xmm8, %xmm4
182 ; SSE-NEXT: packuswb %xmm5, %xmm4
183 ; SSE-NEXT: packuswb %xmm6, %xmm4
184 ; SSE-NEXT: pand %xmm8, %xmm3
185 ; SSE-NEXT: pand %xmm8, %xmm2
186 ; SSE-NEXT: packuswb %xmm3, %xmm2
187 ; SSE-NEXT: pand %xmm8, %xmm1
188 ; SSE-NEXT: pand %xmm8, %xmm0
189 ; SSE-NEXT: packuswb %xmm1, %xmm0
190 ; SSE-NEXT: packuswb %xmm2, %xmm0
191 ; SSE-NEXT: packuswb %xmm4, %xmm0
192 ; SSE-NEXT: retq
193 ;
194 ; AVX1-LABEL: trunc_add_v16i64_v16i8:
195 ; AVX1: # BB#0:
196 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm8
197 ; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4
198 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
199 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm0
200 ; AVX1-NEXT: vpaddq %xmm5, %xmm1, %xmm4
201 ; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm5
202 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
203 ; AVX1-NEXT: vpaddq %xmm5, %xmm1, %xmm1
204 ; AVX1-NEXT: vpaddq %xmm6, %xmm2, %xmm5
205 ; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm6
206 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
207 ; AVX1-NEXT: vpaddq %xmm6, %xmm2, %xmm2
208 ; AVX1-NEXT: vpaddq %xmm7, %xmm3, %xmm6
209 ; AVX1-NEXT: vextractf128 $1, %ymm7, %xmm7
210 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
211 ; AVX1-NEXT: vpaddq %xmm7, %xmm3, %xmm3
212 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
213 ; AVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
214 ; AVX1-NEXT: vpand %xmm7, %xmm6, %xmm6
215 ; AVX1-NEXT: vpackuswb %xmm3, %xmm6, %xmm3
216 ; AVX1-NEXT: vpand %xmm7, %xmm2, %xmm2
217 ; AVX1-NEXT: vpand %xmm7, %xmm5, %xmm5
218 ; AVX1-NEXT: vpackuswb %xmm2, %xmm5, %xmm2
219 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
220 ; AVX1-NEXT: vpand %xmm7, %xmm1, %xmm1
221 ; AVX1-NEXT: vpand %xmm7, %xmm4, %xmm3
222 ; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
223 ; AVX1-NEXT: vpand %xmm7, %xmm0, %xmm0
224 ; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm3
225 ; AVX1-NEXT: vpackuswb %xmm0, %xmm3, %xmm0
226 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
227 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
228 ; AVX1-NEXT: vzeroupper
229 ; AVX1-NEXT: retq
230 ;
231 ; AVX2-LABEL: trunc_add_v16i64_v16i8:
232 ; AVX2: # BB#0:
233 ; AVX2-NEXT: vpaddq %ymm5, %ymm1, %ymm1
234 ; AVX2-NEXT: vpaddq %ymm4, %ymm0, %ymm0
235 ; AVX2-NEXT: vpaddq %ymm7, %ymm3, %ymm3
236 ; AVX2-NEXT: vpaddq %ymm6, %ymm2, %ymm2
237 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
238 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
239 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
240 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
241 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
242 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
243 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
244 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
245 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
246 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
247 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
248 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
249 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
250 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
251 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
252 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
253 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
254 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
255 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
256 ; AVX2-NEXT: vzeroupper
257 ; AVX2-NEXT: retq
258 ;
259 ; AVX512-LABEL: trunc_add_v16i64_v16i8:
260 ; AVX512: # BB#0:
261 ; AVX512-NEXT: vpaddq %zmm3, %zmm1, %zmm1
262 ; AVX512-NEXT: vpaddq %zmm2, %zmm0, %zmm0
263 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
264 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
265 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
266 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
267 ; AVX512-NEXT: vzeroupper
268 ; AVX512-NEXT: retq
269 %1 = add <16 x i64> %a0, %a1
270 %2 = trunc <16 x i64> %1 to <16 x i8>
271 ret <16 x i8> %2
272 }
274 define <16 x i8> @trunc_add_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
275 ; SSE-LABEL: trunc_add_v16i32_v16i8:
276 ; SSE: # BB#0:
277 ; SSE-NEXT: paddd %xmm4, %xmm0
278 ; SSE-NEXT: paddd %xmm5, %xmm1
279 ; SSE-NEXT: paddd %xmm6, %xmm2
280 ; SSE-NEXT: paddd %xmm7, %xmm3
281 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
282 ; SSE-NEXT: pand %xmm4, %xmm3
283 ; SSE-NEXT: pand %xmm4, %xmm2
284 ; SSE-NEXT: packuswb %xmm3, %xmm2
285 ; SSE-NEXT: pand %xmm4, %xmm1
286 ; SSE-NEXT: pand %xmm4, %xmm0
287 ; SSE-NEXT: packuswb %xmm1, %xmm0
288 ; SSE-NEXT: packuswb %xmm2, %xmm0
289 ; SSE-NEXT: retq
290 ;
291 ; AVX1-LABEL: trunc_add_v16i32_v16i8:
292 ; AVX1: # BB#0:
293 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm4
294 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
295 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
296 ; AVX1-NEXT: vpaddd %xmm2, %xmm0, %xmm0
297 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm2
298 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
299 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
300 ; AVX1-NEXT: vpaddd %xmm3, %xmm1, %xmm1
301 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
302 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
303 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
304 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
305 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
306 ; AVX1-NEXT: vpand %xmm3, %xmm4, %xmm2
307 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
308 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
309 ; AVX1-NEXT: vzeroupper
310 ; AVX1-NEXT: retq
311 ;
312 ; AVX2-LABEL: trunc_add_v16i32_v16i8:
313 ; AVX2: # BB#0:
314 ; AVX2-NEXT: vpaddd %ymm2, %ymm0, %ymm0
315 ; AVX2-NEXT: vpaddd %ymm3, %ymm1, %ymm1
316 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
317 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
318 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
319 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
320 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
321 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
322 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
323 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
324 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
325 ; AVX2-NEXT: vzeroupper
326 ; AVX2-NEXT: retq
327 ;
328 ; AVX512-LABEL: trunc_add_v16i32_v16i8:
329 ; AVX512: # BB#0:
330 ; AVX512-NEXT: vpaddd %zmm1, %zmm0, %zmm0
331 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
332 ; AVX512-NEXT: vzeroupper
333 ; AVX512-NEXT: retq
334 %1 = add <16 x i32> %a0, %a1
335 %2 = trunc <16 x i32> %1 to <16 x i8>
336 ret <16 x i8> %2
337 }
339 define <16 x i8> @trunc_add_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
340 ; SSE-LABEL: trunc_add_v16i16_v16i8:
341 ; SSE: # BB#0:
342 ; SSE-NEXT: paddw %xmm2, %xmm0
343 ; SSE-NEXT: paddw %xmm3, %xmm1
344 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
345 ; SSE-NEXT: pand %xmm2, %xmm1
346 ; SSE-NEXT: pand %xmm2, %xmm0
347 ; SSE-NEXT: packuswb %xmm1, %xmm0
348 ; SSE-NEXT: retq
349 ;
350 ; AVX1-LABEL: trunc_add_v16i16_v16i8:
351 ; AVX1: # BB#0:
352 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm2
353 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
354 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
355 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
356 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
357 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
358 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
359 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
360 ; AVX1-NEXT: vzeroupper
361 ; AVX1-NEXT: retq
362 ;
363 ; AVX2-LABEL: trunc_add_v16i16_v16i8:
364 ; AVX2: # BB#0:
365 ; AVX2-NEXT: vpaddw %ymm1, %ymm0, %ymm0
366 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
367 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
368 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
369 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
370 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
371 ; AVX2-NEXT: vzeroupper
372 ; AVX2-NEXT: retq
373 ;
374 ; AVX512F-LABEL: trunc_add_v16i16_v16i8:
375 ; AVX512F: # BB#0:
376 ; AVX512F-NEXT: vpaddw %ymm1, %ymm0, %ymm0
377 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
378 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
379 ; AVX512F-NEXT: vzeroupper
380 ; AVX512F-NEXT: retq
381 ;
382 ; AVX512BW-LABEL: trunc_add_v16i16_v16i8:
383 ; AVX512BW: # BB#0:
384 ; AVX512BW-NEXT: vpaddw %ymm1, %ymm0, %ymm0
385 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
386 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
387 ; AVX512BW-NEXT: vzeroupper
388 ; AVX512BW-NEXT: retq
389 ;
390 ; AVX512DQ-LABEL: trunc_add_v16i16_v16i8:
391 ; AVX512DQ: # BB#0:
392 ; AVX512DQ-NEXT: vpaddw %ymm1, %ymm0, %ymm0
393 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
394 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
395 ; AVX512DQ-NEXT: vzeroupper
396 ; AVX512DQ-NEXT: retq
397 %1 = add <16 x i16> %a0, %a1
398 %2 = trunc <16 x i16> %1 to <16 x i8>
399 ret <16 x i8> %2
400 }
402 define <8 x i16> @trunc_add_v8i32_v8i16_sext_8i8(<16 x i8> %a0, <8 x i32> %a1) {
403 ; SSE-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
404 ; SSE: # BB#0:
405 ; SSE-NEXT: pslld $16, %xmm2
406 ; SSE-NEXT: psrad $16, %xmm2
407 ; SSE-NEXT: pslld $16, %xmm1
408 ; SSE-NEXT: psrad $16, %xmm1
409 ; SSE-NEXT: packssdw %xmm2, %xmm1
410 ; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
411 ; SSE-NEXT: psraw $8, %xmm0
412 ; SSE-NEXT: paddw %xmm1, %xmm0
413 ; SSE-NEXT: retq
414 ;
415 ; AVX1-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
416 ; AVX1: # BB#0:
417 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
418 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
419 ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
420 ; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
421 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
422 ; AVX1-NEXT: vpmovsxbw %xmm0, %xmm0
423 ; AVX1-NEXT: vpaddw %xmm1, %xmm0, %xmm0
424 ; AVX1-NEXT: vzeroupper
425 ; AVX1-NEXT: retq
426 ;
427 ; AVX2-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
428 ; AVX2: # BB#0:
429 ; AVX2-NEXT: vpmovsxbw %xmm0, %xmm0
430 ; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
431 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
432 ; AVX2-NEXT: vpaddw %xmm1, %xmm0, %xmm0
433 ; AVX2-NEXT: vzeroupper
434 ; AVX2-NEXT: retq
435 ;
436 ; AVX512-LABEL: trunc_add_v8i32_v8i16_sext_8i8:
437 ; AVX512: # BB#0:
438 ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
439 ; AVX512-NEXT: vpmovdw %zmm1, %ymm1
440 ; AVX512-NEXT: vpmovsxbw %xmm0, %xmm0
441 ; AVX512-NEXT: vpaddw %xmm1, %xmm0, %xmm0
442 ; AVX512-NEXT: vzeroupper
443 ; AVX512-NEXT: retq
444 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
445 %2 = sext <8 x i8> %1 to <8 x i32>
446 %3 = add <8 x i32> %2, %a1
447 %4 = trunc <8 x i32> %3 to <8 x i16>
448 ret <8 x i16> %4
449 }
451 ;
452 ; add to constant
453 ;
455 define <4 x i32> @trunc_add_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
456 ; SSE-LABEL: trunc_add_const_v4i64_v4i32:
457 ; SSE: # BB#0:
458 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
459 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
460 ; SSE-NEXT: retq
461 ;
462 ; AVX1-LABEL: trunc_add_const_v4i64_v4i32:
463 ; AVX1: # BB#0:
464 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
465 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
466 ; AVX1-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
467 ; AVX1-NEXT: vzeroupper
468 ; AVX1-NEXT: retq
469 ;
470 ; AVX2-LABEL: trunc_add_const_v4i64_v4i32:
471 ; AVX2: # BB#0:
472 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
473 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
474 ; AVX2-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
475 ; AVX2-NEXT: vzeroupper
476 ; AVX2-NEXT: retq
477 ;
478 ; AVX512-LABEL: trunc_add_const_v4i64_v4i32:
479 ; AVX512: # BB#0:
480 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
481 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
482 ; AVX512-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
483 ; AVX512-NEXT: vzeroupper
484 ; AVX512-NEXT: retq
485 %1 = add <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
486 %2 = trunc <4 x i64> %1 to <4 x i32>
487 ret <4 x i32> %2
488 }
490 define <8 x i16> @trunc_add_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
491 ; SSE-LABEL: trunc_add_const_v8i64_v8i16:
492 ; SSE: # BB#0:
493 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
494 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
495 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
496 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
497 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
498 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
499 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
500 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
501 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
502 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
503 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
504 ; SSE-NEXT: paddw {{.*}}(%rip), %xmm0
505 ; SSE-NEXT: retq
506 ;
507 ; AVX1-LABEL: trunc_add_const_v8i64_v8i16:
508 ; AVX1: # BB#0:
509 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
510 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
511 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
512 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
513 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
514 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
515 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
516 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
517 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
518 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
519 ; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
520 ; AVX1-NEXT: vzeroupper
521 ; AVX1-NEXT: retq
522 ;
523 ; AVX2-LABEL: trunc_add_const_v8i64_v8i16:
524 ; AVX2: # BB#0:
525 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
526 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
527 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
528 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
529 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
530 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
531 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
532 ; AVX2-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
533 ; AVX2-NEXT: vzeroupper
534 ; AVX2-NEXT: retq
535 ;
536 ; AVX512-LABEL: trunc_add_const_v8i64_v8i16:
537 ; AVX512: # BB#0:
538 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
539 ; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
540 ; AVX512-NEXT: vzeroupper
541 ; AVX512-NEXT: retq
542 %1 = add <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
543 %2 = trunc <8 x i64> %1 to <8 x i16>
544 ret <8 x i16> %2
545 }
547 define <8 x i16> @trunc_add_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
548 ; SSE-LABEL: trunc_add_const_v8i32_v8i16:
549 ; SSE: # BB#0:
550 ; SSE-NEXT: pslld $16, %xmm1
551 ; SSE-NEXT: psrad $16, %xmm1
552 ; SSE-NEXT: pslld $16, %xmm0
553 ; SSE-NEXT: psrad $16, %xmm0
554 ; SSE-NEXT: packssdw %xmm1, %xmm0
555 ; SSE-NEXT: paddw {{.*}}(%rip), %xmm0
556 ; SSE-NEXT: retq
557 ;
558 ; AVX1-LABEL: trunc_add_const_v8i32_v8i16:
559 ; AVX1: # BB#0:
560 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
561 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
562 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
563 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
564 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
565 ; AVX1-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
566 ; AVX1-NEXT: vzeroupper
567 ; AVX1-NEXT: retq
568 ;
569 ; AVX2-LABEL: trunc_add_const_v8i32_v8i16:
570 ; AVX2: # BB#0:
571 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
572 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
573 ; AVX2-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
574 ; AVX2-NEXT: vzeroupper
575 ; AVX2-NEXT: retq
576 ;
577 ; AVX512-LABEL: trunc_add_const_v8i32_v8i16:
578 ; AVX512: # BB#0:
579 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
580 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
581 ; AVX512-NEXT: vpaddw {{.*}}(%rip), %xmm0, %xmm0
582 ; AVX512-NEXT: vzeroupper
583 ; AVX512-NEXT: retq
584 %1 = add <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
585 %2 = trunc <8 x i32> %1 to <8 x i16>
586 ret <8 x i16> %2
587 }
589 define <16 x i8> @trunc_add_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
590 ; SSE-LABEL: trunc_add_const_v16i64_v16i8:
591 ; SSE: # BB#0:
592 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
593 ; SSE-NEXT: pand %xmm8, %xmm7
594 ; SSE-NEXT: pand %xmm8, %xmm6
595 ; SSE-NEXT: packuswb %xmm7, %xmm6
596 ; SSE-NEXT: pand %xmm8, %xmm5
597 ; SSE-NEXT: pand %xmm8, %xmm4
598 ; SSE-NEXT: packuswb %xmm5, %xmm4
599 ; SSE-NEXT: packuswb %xmm6, %xmm4
600 ; SSE-NEXT: pand %xmm8, %xmm3
601 ; SSE-NEXT: pand %xmm8, %xmm2
602 ; SSE-NEXT: packuswb %xmm3, %xmm2
603 ; SSE-NEXT: pand %xmm8, %xmm1
604 ; SSE-NEXT: pand %xmm8, %xmm0
605 ; SSE-NEXT: packuswb %xmm1, %xmm0
606 ; SSE-NEXT: packuswb %xmm2, %xmm0
607 ; SSE-NEXT: packuswb %xmm4, %xmm0
608 ; SSE-NEXT: paddb {{.*}}(%rip), %xmm0
609 ; SSE-NEXT: retq
610 ;
611 ; AVX1-LABEL: trunc_add_const_v16i64_v16i8:
612 ; AVX1: # BB#0:
613 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
614 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
615 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
616 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
617 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
618 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
619 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
620 ; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
621 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
622 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
623 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
624 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
625 ; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
626 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
627 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
628 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
629 ; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
630 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
631 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
632 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
633 ; AVX1-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
634 ; AVX1-NEXT: vzeroupper
635 ; AVX1-NEXT: retq
636 ;
637 ; AVX2-LABEL: trunc_add_const_v16i64_v16i8:
638 ; AVX2: # BB#0:
639 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
640 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
641 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
642 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
643 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
644 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
645 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
646 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
647 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
648 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
649 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
650 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
651 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
652 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
653 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
654 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
655 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
656 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
657 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
658 ; AVX2-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
659 ; AVX2-NEXT: vzeroupper
660 ; AVX2-NEXT: retq
661 ;
662 ; AVX512-LABEL: trunc_add_const_v16i64_v16i8:
663 ; AVX512: # BB#0:
664 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
665 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
666 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
667 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
668 ; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
669 ; AVX512-NEXT: vzeroupper
670 ; AVX512-NEXT: retq
671 %1 = add <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
672 %2 = trunc <16 x i64> %1 to <16 x i8>
673 ret <16 x i8> %2
674 }
676 define <16 x i8> @trunc_add_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
677 ; SSE-LABEL: trunc_add_const_v16i32_v16i8:
678 ; SSE: # BB#0:
679 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
680 ; SSE-NEXT: pand %xmm4, %xmm3
681 ; SSE-NEXT: pand %xmm4, %xmm2
682 ; SSE-NEXT: packuswb %xmm3, %xmm2
683 ; SSE-NEXT: pand %xmm4, %xmm1
684 ; SSE-NEXT: pand %xmm4, %xmm0
685 ; SSE-NEXT: packuswb %xmm1, %xmm0
686 ; SSE-NEXT: packuswb %xmm2, %xmm0
687 ; SSE-NEXT: paddb {{.*}}(%rip), %xmm0
688 ; SSE-NEXT: retq
689 ;
690 ; AVX1-LABEL: trunc_add_const_v16i32_v16i8:
691 ; AVX1: # BB#0:
692 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
693 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
694 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
695 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
696 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
697 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
698 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
699 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
700 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
701 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
702 ; AVX1-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
703 ; AVX1-NEXT: vzeroupper
704 ; AVX1-NEXT: retq
705 ;
706 ; AVX2-LABEL: trunc_add_const_v16i32_v16i8:
707 ; AVX2: # BB#0:
708 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
709 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
710 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
711 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
712 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
713 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
714 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
715 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
716 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
717 ; AVX2-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
718 ; AVX2-NEXT: vzeroupper
719 ; AVX2-NEXT: retq
720 ;
721 ; AVX512-LABEL: trunc_add_const_v16i32_v16i8:
722 ; AVX512: # BB#0:
723 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
724 ; AVX512-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
725 ; AVX512-NEXT: vzeroupper
726 ; AVX512-NEXT: retq
727 %1 = add <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
728 %2 = trunc <16 x i32> %1 to <16 x i8>
729 ret <16 x i8> %2
730 }
732 define <16 x i8> @trunc_add_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
733 ; SSE-LABEL: trunc_add_const_v16i16_v16i8:
734 ; SSE: # BB#0:
735 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
736 ; SSE-NEXT: pand %xmm2, %xmm1
737 ; SSE-NEXT: pand %xmm2, %xmm0
738 ; SSE-NEXT: packuswb %xmm1, %xmm0
739 ; SSE-NEXT: paddb {{.*}}(%rip), %xmm0
740 ; SSE-NEXT: retq
741 ;
742 ; AVX1-LABEL: trunc_add_const_v16i16_v16i8:
743 ; AVX1: # BB#0:
744 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
745 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
746 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
747 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
748 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
749 ; AVX1-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
750 ; AVX1-NEXT: vzeroupper
751 ; AVX1-NEXT: retq
752 ;
753 ; AVX2-LABEL: trunc_add_const_v16i16_v16i8:
754 ; AVX2: # BB#0:
755 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
756 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
757 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
758 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
759 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
760 ; AVX2-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
761 ; AVX2-NEXT: vzeroupper
762 ; AVX2-NEXT: retq
763 ;
764 ; AVX512F-LABEL: trunc_add_const_v16i16_v16i8:
765 ; AVX512F: # BB#0:
766 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
767 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
768 ; AVX512F-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
769 ; AVX512F-NEXT: vzeroupper
770 ; AVX512F-NEXT: retq
771 ;
772 ; AVX512BW-LABEL: trunc_add_const_v16i16_v16i8:
773 ; AVX512BW: # BB#0:
774 ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
775 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
776 ; AVX512BW-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
777 ; AVX512BW-NEXT: vzeroupper
778 ; AVX512BW-NEXT: retq
779 ;
780 ; AVX512DQ-LABEL: trunc_add_const_v16i16_v16i8:
781 ; AVX512DQ: # BB#0:
782 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
783 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
784 ; AVX512DQ-NEXT: vpaddb {{.*}}(%rip), %xmm0, %xmm0
785 ; AVX512DQ-NEXT: vzeroupper
786 ; AVX512DQ-NEXT: retq
787 %1 = add <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
788 %2 = trunc <16 x i16> %1 to <16 x i8>
789 ret <16 x i8> %2
790 }
792 ;
793 ; sub
794 ;
796 define <4 x i32> @trunc_sub_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
797 ; SSE-LABEL: trunc_sub_v4i64_v4i32:
798 ; SSE: # BB#0:
799 ; SSE-NEXT: psubq %xmm3, %xmm1
800 ; SSE-NEXT: psubq %xmm2, %xmm0
801 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
802 ; SSE-NEXT: retq
803 ;
804 ; AVX1-LABEL: trunc_sub_v4i64_v4i32:
805 ; AVX1: # BB#0:
806 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
807 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
808 ; AVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2
809 ; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm0
810 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
811 ; AVX1-NEXT: vzeroupper
812 ; AVX1-NEXT: retq
813 ;
814 ; AVX2-LABEL: trunc_sub_v4i64_v4i32:
815 ; AVX2: # BB#0:
816 ; AVX2-NEXT: vpsubq %ymm1, %ymm0, %ymm0
817 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
818 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
819 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
820 ; AVX2-NEXT: vzeroupper
821 ; AVX2-NEXT: retq
822 ;
823 ; AVX512-LABEL: trunc_sub_v4i64_v4i32:
824 ; AVX512: # BB#0:
825 ; AVX512-NEXT: vpsubq %ymm1, %ymm0, %ymm0
826 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
827 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
828 ; AVX512-NEXT: vzeroupper
829 ; AVX512-NEXT: retq
830 %1 = sub <4 x i64> %a0, %a1
831 %2 = trunc <4 x i64> %1 to <4 x i32>
832 ret <4 x i32> %2
833 }
835 define <8 x i16> @trunc_sub_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
836 ; SSE-LABEL: trunc_sub_v8i64_v8i16:
837 ; SSE: # BB#0:
838 ; SSE-NEXT: psubq %xmm6, %xmm2
839 ; SSE-NEXT: psubq %xmm7, %xmm3
840 ; SSE-NEXT: psubq %xmm4, %xmm0
841 ; SSE-NEXT: psubq %xmm5, %xmm1
842 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
843 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
844 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
845 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
846 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
847 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
848 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
849 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
850 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
851 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
852 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
853 ; SSE-NEXT: retq
854 ;
855 ; AVX1-LABEL: trunc_sub_v8i64_v8i16:
856 ; AVX1: # BB#0:
857 ; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm4
858 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
859 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
860 ; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm0
861 ; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm2
862 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
863 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
864 ; AVX1-NEXT: vpsubq %xmm3, %xmm1, %xmm1
865 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
866 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
867 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
868 ; AVX1-NEXT: vpackusdw %xmm1, %xmm2, %xmm1
869 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
870 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm4[0],xmm3[1,2,3],xmm4[4],xmm3[5,6,7]
871 ; AVX1-NEXT: vpackusdw %xmm0, %xmm2, %xmm0
872 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
873 ; AVX1-NEXT: vzeroupper
874 ; AVX1-NEXT: retq
875 ;
876 ; AVX2-LABEL: trunc_sub_v8i64_v8i16:
877 ; AVX2: # BB#0:
878 ; AVX2-NEXT: vpsubq %ymm3, %ymm1, %ymm1
879 ; AVX2-NEXT: vpsubq %ymm2, %ymm0, %ymm0
880 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
881 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
882 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
883 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
884 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
885 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
886 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
887 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
888 ; AVX2-NEXT: vzeroupper
889 ; AVX2-NEXT: retq
890 ;
891 ; AVX512-LABEL: trunc_sub_v8i64_v8i16:
892 ; AVX512: # BB#0:
893 ; AVX512-NEXT: vpsubq %zmm1, %zmm0, %zmm0
894 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
895 ; AVX512-NEXT: vzeroupper
896 ; AVX512-NEXT: retq
897 %1 = sub <8 x i64> %a0, %a1
898 %2 = trunc <8 x i64> %1 to <8 x i16>
899 ret <8 x i16> %2
900 }
902 define <8 x i16> @trunc_sub_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
903 ; SSE-LABEL: trunc_sub_v8i32_v8i16:
904 ; SSE: # BB#0:
905 ; SSE-NEXT: psubd %xmm2, %xmm0
906 ; SSE-NEXT: psubd %xmm3, %xmm1
907 ; SSE-NEXT: pslld $16, %xmm1
908 ; SSE-NEXT: psrad $16, %xmm1
909 ; SSE-NEXT: pslld $16, %xmm0
910 ; SSE-NEXT: psrad $16, %xmm0
911 ; SSE-NEXT: packssdw %xmm1, %xmm0
912 ; SSE-NEXT: retq
913 ;
914 ; AVX1-LABEL: trunc_sub_v8i32_v8i16:
915 ; AVX1: # BB#0:
916 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm2
917 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
918 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
919 ; AVX1-NEXT: vpsubd %xmm1, %xmm0, %xmm0
920 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
921 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
922 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
923 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
924 ; AVX1-NEXT: vzeroupper
925 ; AVX1-NEXT: retq
926 ;
927 ; AVX2-LABEL: trunc_sub_v8i32_v8i16:
928 ; AVX2: # BB#0:
929 ; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0
930 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
931 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
932 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
933 ; AVX2-NEXT: vzeroupper
934 ; AVX2-NEXT: retq
935 ;
936 ; AVX512-LABEL: trunc_sub_v8i32_v8i16:
937 ; AVX512: # BB#0:
938 ; AVX512-NEXT: vpsubd %ymm1, %ymm0, %ymm0
939 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
940 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
941 ; AVX512-NEXT: vzeroupper
942 ; AVX512-NEXT: retq
943 %1 = sub <8 x i32> %a0, %a1
944 %2 = trunc <8 x i32> %1 to <8 x i16>
945 ret <8 x i16> %2
946 }
948 define <16 x i8> @trunc_sub_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
949 ; SSE-LABEL: trunc_sub_v16i64_v16i8:
950 ; SSE: # BB#0:
951 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm0
952 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm1
953 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm2
954 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm3
955 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm4
956 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm5
957 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm6
958 ; SSE-NEXT: psubq {{[0-9]+}}(%rsp), %xmm7
959 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
960 ; SSE-NEXT: pand %xmm8, %xmm7
961 ; SSE-NEXT: pand %xmm8, %xmm6
962 ; SSE-NEXT: packuswb %xmm7, %xmm6
963 ; SSE-NEXT: pand %xmm8, %xmm5
964 ; SSE-NEXT: pand %xmm8, %xmm4
965 ; SSE-NEXT: packuswb %xmm5, %xmm4
966 ; SSE-NEXT: packuswb %xmm6, %xmm4
967 ; SSE-NEXT: pand %xmm8, %xmm3
968 ; SSE-NEXT: pand %xmm8, %xmm2
969 ; SSE-NEXT: packuswb %xmm3, %xmm2
970 ; SSE-NEXT: pand %xmm8, %xmm1
971 ; SSE-NEXT: pand %xmm8, %xmm0
972 ; SSE-NEXT: packuswb %xmm1, %xmm0
973 ; SSE-NEXT: packuswb %xmm2, %xmm0
974 ; SSE-NEXT: packuswb %xmm4, %xmm0
975 ; SSE-NEXT: retq
976 ;
977 ; AVX1-LABEL: trunc_sub_v16i64_v16i8:
978 ; AVX1: # BB#0:
979 ; AVX1-NEXT: vpsubq %xmm4, %xmm0, %xmm8
980 ; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm4
981 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
982 ; AVX1-NEXT: vpsubq %xmm4, %xmm0, %xmm0
983 ; AVX1-NEXT: vpsubq %xmm5, %xmm1, %xmm4
984 ; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm5
985 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
986 ; AVX1-NEXT: vpsubq %xmm5, %xmm1, %xmm1
987 ; AVX1-NEXT: vpsubq %xmm6, %xmm2, %xmm5
988 ; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm6
989 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
990 ; AVX1-NEXT: vpsubq %xmm6, %xmm2, %xmm2
991 ; AVX1-NEXT: vpsubq %xmm7, %xmm3, %xmm6
992 ; AVX1-NEXT: vextractf128 $1, %ymm7, %xmm7
993 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
994 ; AVX1-NEXT: vpsubq %xmm7, %xmm3, %xmm3
995 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm7 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
996 ; AVX1-NEXT: vpand %xmm7, %xmm3, %xmm3
997 ; AVX1-NEXT: vpand %xmm7, %xmm6, %xmm6
998 ; AVX1-NEXT: vpackuswb %xmm3, %xmm6, %xmm3
999 ; AVX1-NEXT: vpand %xmm7, %xmm2, %xmm2
1000 ; AVX1-NEXT: vpand %xmm7, %xmm5, %xmm5
1001 ; AVX1-NEXT: vpackuswb %xmm2, %xmm5, %xmm2
1002 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
1003 ; AVX1-NEXT: vpand %xmm7, %xmm1, %xmm1
1004 ; AVX1-NEXT: vpand %xmm7, %xmm4, %xmm3
1005 ; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
1006 ; AVX1-NEXT: vpand %xmm7, %xmm0, %xmm0
1007 ; AVX1-NEXT: vpand %xmm7, %xmm8, %xmm3
1008 ; AVX1-NEXT: vpackuswb %xmm0, %xmm3, %xmm0
1009 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1010 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
1011 ; AVX1-NEXT: vzeroupper
1012 ; AVX1-NEXT: retq
1013 ;
1014 ; AVX2-LABEL: trunc_sub_v16i64_v16i8:
1015 ; AVX2: # BB#0:
1016 ; AVX2-NEXT: vpsubq %ymm5, %ymm1, %ymm1
1017 ; AVX2-NEXT: vpsubq %ymm4, %ymm0, %ymm0
1018 ; AVX2-NEXT: vpsubq %ymm7, %ymm3, %ymm3
1019 ; AVX2-NEXT: vpsubq %ymm6, %ymm2, %ymm2
1020 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
1021 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1022 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
1023 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
1024 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
1025 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1026 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
1027 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1028 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1029 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
1030 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1031 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1032 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
1033 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1034 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
1035 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
1036 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1037 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
1038 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
1039 ; AVX2-NEXT: vzeroupper
1040 ; AVX2-NEXT: retq
1041 ;
1042 ; AVX512-LABEL: trunc_sub_v16i64_v16i8:
1043 ; AVX512: # BB#0:
1044 ; AVX512-NEXT: vpsubq %zmm3, %zmm1, %zmm1
1045 ; AVX512-NEXT: vpsubq %zmm2, %zmm0, %zmm0
1046 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
1047 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
1048 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
1049 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
1050 ; AVX512-NEXT: vzeroupper
1051 ; AVX512-NEXT: retq
1052 %1 = sub <16 x i64> %a0, %a1
1053 %2 = trunc <16 x i64> %1 to <16 x i8>
1054 ret <16 x i8> %2
1055 }
1057 define <16 x i8> @trunc_sub_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
1058 ; SSE-LABEL: trunc_sub_v16i32_v16i8:
1059 ; SSE: # BB#0:
1060 ; SSE-NEXT: psubd %xmm4, %xmm0
1061 ; SSE-NEXT: psubd %xmm5, %xmm1
1062 ; SSE-NEXT: psubd %xmm6, %xmm2
1063 ; SSE-NEXT: psubd %xmm7, %xmm3
1064 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
1065 ; SSE-NEXT: pand %xmm4, %xmm3
1066 ; SSE-NEXT: pand %xmm4, %xmm2
1067 ; SSE-NEXT: packuswb %xmm3, %xmm2
1068 ; SSE-NEXT: pand %xmm4, %xmm1
1069 ; SSE-NEXT: pand %xmm4, %xmm0
1070 ; SSE-NEXT: packuswb %xmm1, %xmm0
1071 ; SSE-NEXT: packuswb %xmm2, %xmm0
1072 ; SSE-NEXT: retq
1073 ;
1074 ; AVX1-LABEL: trunc_sub_v16i32_v16i8:
1075 ; AVX1: # BB#0:
1076 ; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm4
1077 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
1078 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1079 ; AVX1-NEXT: vpsubd %xmm2, %xmm0, %xmm0
1080 ; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm2
1081 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
1082 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1083 ; AVX1-NEXT: vpsubd %xmm3, %xmm1, %xmm1
1084 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
1085 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
1086 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
1087 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
1088 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
1089 ; AVX1-NEXT: vpand %xmm3, %xmm4, %xmm2
1090 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
1091 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1092 ; AVX1-NEXT: vzeroupper
1093 ; AVX1-NEXT: retq
1094 ;
1095 ; AVX2-LABEL: trunc_sub_v16i32_v16i8:
1096 ; AVX2: # BB#0:
1097 ; AVX2-NEXT: vpsubd %ymm2, %ymm0, %ymm0
1098 ; AVX2-NEXT: vpsubd %ymm3, %ymm1, %ymm1
1099 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1100 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
1101 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1102 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1103 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
1104 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
1105 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1106 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
1107 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1108 ; AVX2-NEXT: vzeroupper
1109 ; AVX2-NEXT: retq
1110 ;
1111 ; AVX512-LABEL: trunc_sub_v16i32_v16i8:
1112 ; AVX512: # BB#0:
1113 ; AVX512-NEXT: vpsubd %zmm1, %zmm0, %zmm0
1114 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
1115 ; AVX512-NEXT: vzeroupper
1116 ; AVX512-NEXT: retq
1117 %1 = sub <16 x i32> %a0, %a1
1118 %2 = trunc <16 x i32> %1 to <16 x i8>
1119 ret <16 x i8> %2
1120 }
1122 define <16 x i8> @trunc_sub_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
1123 ; SSE-LABEL: trunc_sub_v16i16_v16i8:
1124 ; SSE: # BB#0:
1125 ; SSE-NEXT: psubw %xmm2, %xmm0
1126 ; SSE-NEXT: psubw %xmm3, %xmm1
1127 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
1128 ; SSE-NEXT: pand %xmm2, %xmm1
1129 ; SSE-NEXT: pand %xmm2, %xmm0
1130 ; SSE-NEXT: packuswb %xmm1, %xmm0
1131 ; SSE-NEXT: retq
1132 ;
1133 ; AVX1-LABEL: trunc_sub_v16i16_v16i8:
1134 ; AVX1: # BB#0:
1135 ; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm2
1136 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1137 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1138 ; AVX1-NEXT: vpsubw %xmm1, %xmm0, %xmm0
1139 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1140 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
1141 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
1142 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
1143 ; AVX1-NEXT: vzeroupper
1144 ; AVX1-NEXT: retq
1145 ;
1146 ; AVX2-LABEL: trunc_sub_v16i16_v16i8:
1147 ; AVX2: # BB#0:
1148 ; AVX2-NEXT: vpsubw %ymm1, %ymm0, %ymm0
1149 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1150 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1151 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
1152 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
1153 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1154 ; AVX2-NEXT: vzeroupper
1155 ; AVX2-NEXT: retq
1156 ;
1157 ; AVX512F-LABEL: trunc_sub_v16i16_v16i8:
1158 ; AVX512F: # BB#0:
1159 ; AVX512F-NEXT: vpsubw %ymm1, %ymm0, %ymm0
1160 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
1161 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
1162 ; AVX512F-NEXT: vzeroupper
1163 ; AVX512F-NEXT: retq
1164 ;
1165 ; AVX512BW-LABEL: trunc_sub_v16i16_v16i8:
1166 ; AVX512BW: # BB#0:
1167 ; AVX512BW-NEXT: vpsubw %ymm1, %ymm0, %ymm0
1168 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
1169 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1170 ; AVX512BW-NEXT: vzeroupper
1171 ; AVX512BW-NEXT: retq
1172 ;
1173 ; AVX512DQ-LABEL: trunc_sub_v16i16_v16i8:
1174 ; AVX512DQ: # BB#0:
1175 ; AVX512DQ-NEXT: vpsubw %ymm1, %ymm0, %ymm0
1176 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
1177 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
1178 ; AVX512DQ-NEXT: vzeroupper
1179 ; AVX512DQ-NEXT: retq
1180 %1 = sub <16 x i16> %a0, %a1
1181 %2 = trunc <16 x i16> %1 to <16 x i8>
1182 ret <16 x i8> %2
1183 }
1185 ;
1186 ; sub to constant
1187 ;
1189 define <4 x i32> @trunc_sub_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
1190 ; SSE-LABEL: trunc_sub_const_v4i64_v4i32:
1191 ; SSE: # BB#0:
1192 ; SSE-NEXT: movl $1, %eax
1193 ; SSE-NEXT: movq %rax, %xmm2
1194 ; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
1195 ; SSE-NEXT: psubq %xmm2, %xmm0
1196 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm1
1197 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
1198 ; SSE-NEXT: retq
1199 ;
1200 ; AVX1-LABEL: trunc_sub_const_v4i64_v4i32:
1201 ; AVX1: # BB#0:
1202 ; AVX1-NEXT: movl $1, %eax
1203 ; AVX1-NEXT: vmovq %rax, %xmm1
1204 ; AVX1-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1,2,3,4,5,6,7]
1205 ; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm1
1206 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1207 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm0, %xmm0
1208 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm1[0,2],xmm0[0,2]
1209 ; AVX1-NEXT: vzeroupper
1210 ; AVX1-NEXT: retq
1211 ;
1212 ; AVX2-LABEL: trunc_sub_const_v4i64_v4i32:
1213 ; AVX2: # BB#0:
1214 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0
1215 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1216 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1217 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1218 ; AVX2-NEXT: vzeroupper
1219 ; AVX2-NEXT: retq
1220 ;
1221 ; AVX512-LABEL: trunc_sub_const_v4i64_v4i32:
1222 ; AVX512: # BB#0:
1223 ; AVX512-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0
1224 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
1225 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1226 ; AVX512-NEXT: vzeroupper
1227 ; AVX512-NEXT: retq
1228 %1 = sub <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
1229 %2 = trunc <4 x i64> %1 to <4 x i32>
1230 ret <4 x i32> %2
1231 }
1233 define <8 x i16> @trunc_sub_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
1234 ; SSE-LABEL: trunc_sub_const_v8i64_v8i16:
1235 ; SSE: # BB#0:
1236 ; SSE-NEXT: movl $1, %eax
1237 ; SSE-NEXT: movq %rax, %xmm4
1238 ; SSE-NEXT: pslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
1239 ; SSE-NEXT: psubq %xmm4, %xmm0
1240 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm1
1241 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm2
1242 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm3
1243 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
1244 ; SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm3[0,1,0,2,4,5,6,7]
1245 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
1246 ; SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm2[0,1,0,2,4,5,6,7]
1247 ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
1248 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1249 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
1250 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1251 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
1252 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1253 ; SSE-NEXT: movsd {{.*#+}} xmm2 = xmm0[0],xmm2[1]
1254 ; SSE-NEXT: movapd %xmm2, %xmm0
1255 ; SSE-NEXT: retq
1256 ;
1257 ; AVX1-LABEL: trunc_sub_const_v8i64_v8i16:
1258 ; AVX1: # BB#0:
1259 ; AVX1-NEXT: movl $1, %eax
1260 ; AVX1-NEXT: vmovq %rax, %xmm2
1261 ; AVX1-NEXT: vpslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
1262 ; AVX1-NEXT: vpsubq %xmm2, %xmm0, %xmm2
1263 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1264 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm0, %xmm0
1265 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm3
1266 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1267 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm1
1268 ; AVX1-NEXT: vpxor %xmm4, %xmm4, %xmm4
1269 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm4[1,2,3],xmm1[4],xmm4[5,6,7]
1270 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm4[1,2,3],xmm3[4],xmm4[5,6,7]
1271 ; AVX1-NEXT: vpackusdw %xmm1, %xmm3, %xmm1
1272 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm4[1,2,3],xmm0[4],xmm4[5,6,7]
1273 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm4[1,2,3],xmm2[4],xmm4[5,6,7]
1274 ; AVX1-NEXT: vpackusdw %xmm0, %xmm2, %xmm0
1275 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
1276 ; AVX1-NEXT: vzeroupper
1277 ; AVX1-NEXT: retq
1278 ;
1279 ; AVX2-LABEL: trunc_sub_const_v8i64_v8i16:
1280 ; AVX2: # BB#0:
1281 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm1, %ymm1
1282 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0
1283 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1284 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1285 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
1286 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1287 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
1288 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1289 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1290 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1291 ; AVX2-NEXT: vzeroupper
1292 ; AVX2-NEXT: retq
1293 ;
1294 ; AVX512-LABEL: trunc_sub_const_v8i64_v8i16:
1295 ; AVX512: # BB#0:
1296 ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm0, %zmm0
1297 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
1298 ; AVX512-NEXT: vzeroupper
1299 ; AVX512-NEXT: retq
1300 %1 = sub <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
1301 %2 = trunc <8 x i64> %1 to <8 x i16>
1302 ret <8 x i16> %2
1303 }
1305 define <8 x i16> @trunc_sub_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
1306 ; SSE-LABEL: trunc_sub_const_v8i32_v8i16:
1307 ; SSE: # BB#0:
1308 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm0
1309 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm1
1310 ; SSE-NEXT: pslld $16, %xmm1
1311 ; SSE-NEXT: psrad $16, %xmm1
1312 ; SSE-NEXT: pslld $16, %xmm0
1313 ; SSE-NEXT: psrad $16, %xmm0
1314 ; SSE-NEXT: packssdw %xmm1, %xmm0
1315 ; SSE-NEXT: retq
1316 ;
1317 ; AVX1-LABEL: trunc_sub_const_v8i32_v8i16:
1318 ; AVX1: # BB#0:
1319 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm1
1320 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1321 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
1322 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
1323 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
1324 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
1325 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
1326 ; AVX1-NEXT: vzeroupper
1327 ; AVX1-NEXT: retq
1328 ;
1329 ; AVX2-LABEL: trunc_sub_const_v8i32_v8i16:
1330 ; AVX2: # BB#0:
1331 ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0
1332 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1333 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1334 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1335 ; AVX2-NEXT: vzeroupper
1336 ; AVX2-NEXT: retq
1337 ;
1338 ; AVX512-LABEL: trunc_sub_const_v8i32_v8i16:
1339 ; AVX512: # BB#0:
1340 ; AVX512-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0
1341 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
1342 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1343 ; AVX512-NEXT: vzeroupper
1344 ; AVX512-NEXT: retq
1345 %1 = sub <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
1346 %2 = trunc <8 x i32> %1 to <8 x i16>
1347 ret <8 x i16> %2
1348 }
1350 define <16 x i8> @trunc_sub_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
1351 ; SSE-LABEL: trunc_sub_const_v16i64_v16i8:
1352 ; SSE: # BB#0:
1353 ; SSE-NEXT: movl $1, %eax
1354 ; SSE-NEXT: movq %rax, %xmm8
1355 ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7]
1356 ; SSE-NEXT: psubq %xmm8, %xmm0
1357 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm1
1358 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm2
1359 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm3
1360 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm4
1361 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm5
1362 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm6
1363 ; SSE-NEXT: psubq {{.*}}(%rip), %xmm7
1364 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
1365 ; SSE-NEXT: pand %xmm8, %xmm7
1366 ; SSE-NEXT: pand %xmm8, %xmm6
1367 ; SSE-NEXT: packuswb %xmm7, %xmm6
1368 ; SSE-NEXT: pand %xmm8, %xmm5
1369 ; SSE-NEXT: pand %xmm8, %xmm4
1370 ; SSE-NEXT: packuswb %xmm5, %xmm4
1371 ; SSE-NEXT: packuswb %xmm6, %xmm4
1372 ; SSE-NEXT: pand %xmm8, %xmm3
1373 ; SSE-NEXT: pand %xmm8, %xmm2
1374 ; SSE-NEXT: packuswb %xmm3, %xmm2
1375 ; SSE-NEXT: pand %xmm8, %xmm1
1376 ; SSE-NEXT: pand %xmm8, %xmm0
1377 ; SSE-NEXT: packuswb %xmm1, %xmm0
1378 ; SSE-NEXT: packuswb %xmm2, %xmm0
1379 ; SSE-NEXT: packuswb %xmm4, %xmm0
1380 ; SSE-NEXT: retq
1381 ;
1382 ; AVX1-LABEL: trunc_sub_const_v16i64_v16i8:
1383 ; AVX1: # BB#0:
1384 ; AVX1-NEXT: movl $1, %eax
1385 ; AVX1-NEXT: vmovq %rax, %xmm4
1386 ; AVX1-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
1387 ; AVX1-NEXT: vpsubq %xmm4, %xmm0, %xmm8
1388 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1389 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm0, %xmm0
1390 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm5
1391 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1392 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm1, %xmm1
1393 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm2, %xmm6
1394 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
1395 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm2, %xmm2
1396 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm3, %xmm7
1397 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
1398 ; AVX1-NEXT: vpsubq {{.*}}(%rip), %xmm3, %xmm3
1399 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
1400 ; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
1401 ; AVX1-NEXT: vpand %xmm4, %xmm7, %xmm7
1402 ; AVX1-NEXT: vpackuswb %xmm3, %xmm7, %xmm3
1403 ; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
1404 ; AVX1-NEXT: vpand %xmm4, %xmm6, %xmm6
1405 ; AVX1-NEXT: vpackuswb %xmm2, %xmm6, %xmm2
1406 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
1407 ; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
1408 ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm3
1409 ; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
1410 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
1411 ; AVX1-NEXT: vpand %xmm4, %xmm8, %xmm3
1412 ; AVX1-NEXT: vpackuswb %xmm0, %xmm3, %xmm0
1413 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1414 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
1415 ; AVX1-NEXT: vzeroupper
1416 ; AVX1-NEXT: retq
1417 ;
1418 ; AVX2-LABEL: trunc_sub_const_v16i64_v16i8:
1419 ; AVX2: # BB#0:
1420 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm1, %ymm1
1421 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm0, %ymm0
1422 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm3, %ymm3
1423 ; AVX2-NEXT: vpsubq {{.*}}(%rip), %ymm2, %ymm2
1424 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
1425 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1426 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
1427 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
1428 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
1429 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1430 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
1431 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1432 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1433 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
1434 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1435 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1436 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
1437 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1438 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
1439 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
1440 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1441 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
1442 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
1443 ; AVX2-NEXT: vzeroupper
1444 ; AVX2-NEXT: retq
1445 ;
1446 ; AVX512-LABEL: trunc_sub_const_v16i64_v16i8:
1447 ; AVX512: # BB#0:
1448 ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm1, %zmm1
1449 ; AVX512-NEXT: vpsubq {{.*}}(%rip), %zmm0, %zmm0
1450 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
1451 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
1452 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
1453 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
1454 ; AVX512-NEXT: vzeroupper
1455 ; AVX512-NEXT: retq
1456 %1 = sub <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
1457 %2 = trunc <16 x i64> %1 to <16 x i8>
1458 ret <16 x i8> %2
1459 }
1461 define <16 x i8> @trunc_sub_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
1462 ; SSE-LABEL: trunc_sub_const_v16i32_v16i8:
1463 ; SSE: # BB#0:
1464 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm0
1465 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm1
1466 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm2
1467 ; SSE-NEXT: psubd {{.*}}(%rip), %xmm3
1468 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
1469 ; SSE-NEXT: pand %xmm4, %xmm3
1470 ; SSE-NEXT: pand %xmm4, %xmm2
1471 ; SSE-NEXT: packuswb %xmm3, %xmm2
1472 ; SSE-NEXT: pand %xmm4, %xmm1
1473 ; SSE-NEXT: pand %xmm4, %xmm0
1474 ; SSE-NEXT: packuswb %xmm1, %xmm0
1475 ; SSE-NEXT: packuswb %xmm2, %xmm0
1476 ; SSE-NEXT: retq
1477 ;
1478 ; AVX1-LABEL: trunc_sub_const_v16i32_v16i8:
1479 ; AVX1: # BB#0:
1480 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm2
1481 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1482 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm0, %xmm0
1483 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm1, %xmm3
1484 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1485 ; AVX1-NEXT: vpsubd {{.*}}(%rip), %xmm1, %xmm1
1486 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
1487 ; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
1488 ; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
1489 ; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
1490 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
1491 ; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
1492 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
1493 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1494 ; AVX1-NEXT: vzeroupper
1495 ; AVX1-NEXT: retq
1496 ;
1497 ; AVX2-LABEL: trunc_sub_const_v16i32_v16i8:
1498 ; AVX2: # BB#0:
1499 ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm0, %ymm0
1500 ; AVX2-NEXT: vpsubd {{.*}}(%rip), %ymm1, %ymm1
1501 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1502 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
1503 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1504 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1505 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
1506 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
1507 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1508 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
1509 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1510 ; AVX2-NEXT: vzeroupper
1511 ; AVX2-NEXT: retq
1512 ;
1513 ; AVX512-LABEL: trunc_sub_const_v16i32_v16i8:
1514 ; AVX512: # BB#0:
1515 ; AVX512-NEXT: vpsubd {{.*}}(%rip), %zmm0, %zmm0
1516 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
1517 ; AVX512-NEXT: vzeroupper
1518 ; AVX512-NEXT: retq
1519 %1 = sub <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
1520 %2 = trunc <16 x i32> %1 to <16 x i8>
1521 ret <16 x i8> %2
1522 }
1524 define <16 x i8> @trunc_sub_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
1525 ; SSE-LABEL: trunc_sub_const_v16i16_v16i8:
1526 ; SSE: # BB#0:
1527 ; SSE-NEXT: psubw {{.*}}(%rip), %xmm0
1528 ; SSE-NEXT: psubw {{.*}}(%rip), %xmm1
1529 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
1530 ; SSE-NEXT: pand %xmm2, %xmm1
1531 ; SSE-NEXT: pand %xmm2, %xmm0
1532 ; SSE-NEXT: packuswb %xmm1, %xmm0
1533 ; SSE-NEXT: retq
1534 ;
1535 ; AVX1-LABEL: trunc_sub_const_v16i16_v16i8:
1536 ; AVX1: # BB#0:
1537 ; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm1
1538 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1539 ; AVX1-NEXT: vpsubw {{.*}}(%rip), %xmm0, %xmm0
1540 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1541 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
1542 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
1543 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
1544 ; AVX1-NEXT: vzeroupper
1545 ; AVX1-NEXT: retq
1546 ;
1547 ; AVX2-LABEL: trunc_sub_const_v16i16_v16i8:
1548 ; AVX2: # BB#0:
1549 ; AVX2-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
1550 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1551 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
1552 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
1553 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
1554 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
1555 ; AVX2-NEXT: vzeroupper
1556 ; AVX2-NEXT: retq
1557 ;
1558 ; AVX512F-LABEL: trunc_sub_const_v16i16_v16i8:
1559 ; AVX512F: # BB#0:
1560 ; AVX512F-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
1561 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
1562 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
1563 ; AVX512F-NEXT: vzeroupper
1564 ; AVX512F-NEXT: retq
1565 ;
1566 ; AVX512BW-LABEL: trunc_sub_const_v16i16_v16i8:
1567 ; AVX512BW: # BB#0:
1568 ; AVX512BW-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
1569 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
1570 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1571 ; AVX512BW-NEXT: vzeroupper
1572 ; AVX512BW-NEXT: retq
1573 ;
1574 ; AVX512DQ-LABEL: trunc_sub_const_v16i16_v16i8:
1575 ; AVX512DQ: # BB#0:
1576 ; AVX512DQ-NEXT: vpsubw {{.*}}(%rip), %ymm0, %ymm0
1577 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
1578 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
1579 ; AVX512DQ-NEXT: vzeroupper
1580 ; AVX512DQ-NEXT: retq
1581 %1 = sub <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
1582 %2 = trunc <16 x i16> %1 to <16 x i8>
1583 ret <16 x i8> %2
1584 }
1586 ;
1587 ; mul
1588 ;
1590 define <4 x i32> @trunc_mul_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
1591 ; SSE-LABEL: trunc_mul_v4i64_v4i32:
1592 ; SSE: # BB#0:
1593 ; SSE-NEXT: movdqa %xmm1, %xmm4
1594 ; SSE-NEXT: psrlq $32, %xmm4
1595 ; SSE-NEXT: pmuludq %xmm3, %xmm4
1596 ; SSE-NEXT: movdqa %xmm3, %xmm5
1597 ; SSE-NEXT: psrlq $32, %xmm5
1598 ; SSE-NEXT: pmuludq %xmm1, %xmm5
1599 ; SSE-NEXT: paddq %xmm4, %xmm5
1600 ; SSE-NEXT: psllq $32, %xmm5
1601 ; SSE-NEXT: pmuludq %xmm3, %xmm1
1602 ; SSE-NEXT: paddq %xmm5, %xmm1
1603 ; SSE-NEXT: movdqa %xmm0, %xmm3
1604 ; SSE-NEXT: psrlq $32, %xmm3
1605 ; SSE-NEXT: pmuludq %xmm2, %xmm3
1606 ; SSE-NEXT: movdqa %xmm2, %xmm4
1607 ; SSE-NEXT: psrlq $32, %xmm4
1608 ; SSE-NEXT: pmuludq %xmm0, %xmm4
1609 ; SSE-NEXT: paddq %xmm3, %xmm4
1610 ; SSE-NEXT: psllq $32, %xmm4
1611 ; SSE-NEXT: pmuludq %xmm2, %xmm0
1612 ; SSE-NEXT: paddq %xmm4, %xmm0
1613 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
1614 ; SSE-NEXT: retq
1615 ;
1616 ; AVX1-LABEL: trunc_mul_v4i64_v4i32:
1617 ; AVX1: # BB#0:
1618 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
1619 ; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,2],xmm2[0,2]
1620 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
1621 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
1622 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1623 ; AVX1-NEXT: vzeroupper
1624 ; AVX1-NEXT: retq
1625 ;
1626 ; AVX2-LABEL: trunc_mul_v4i64_v4i32:
1627 ; AVX2: # BB#0:
1628 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
1629 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1630 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1631 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1632 ; AVX2-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1633 ; AVX2-NEXT: vzeroupper
1634 ; AVX2-NEXT: retq
1635 ;
1636 ; AVX512F-LABEL: trunc_mul_v4i64_v4i32:
1637 ; AVX512F: # BB#0:
1638 ; AVX512F-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
1639 ; AVX512F-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
1640 ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1
1641 ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
1642 ; AVX512F-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1643 ; AVX512F-NEXT: vzeroupper
1644 ; AVX512F-NEXT: retq
1645 ;
1646 ; AVX512BW-LABEL: trunc_mul_v4i64_v4i32:
1647 ; AVX512BW: # BB#0:
1648 ; AVX512BW-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
1649 ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
1650 ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1
1651 ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
1652 ; AVX512BW-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1653 ; AVX512BW-NEXT: vzeroupper
1654 ; AVX512BW-NEXT: retq
1655 ;
1656 ; AVX512DQ-LABEL: trunc_mul_v4i64_v4i32:
1657 ; AVX512DQ: # BB#0:
1658 ; AVX512DQ-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
1659 ; AVX512DQ-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
1660 ; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0
1661 ; AVX512DQ-NEXT: vpmovqd %zmm0, %ymm0
1662 ; AVX512DQ-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1663 ; AVX512DQ-NEXT: vzeroupper
1664 ; AVX512DQ-NEXT: retq
1665 %1 = mul <4 x i64> %a0, %a1
1666 %2 = trunc <4 x i64> %1 to <4 x i32>
1667 ret <4 x i32> %2
1668 }
1670 define <8 x i16> @trunc_mul_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
1671 ; SSE-LABEL: trunc_mul_v8i64_v8i16:
1672 ; SSE: # BB#0:
1673 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[0,2,2,3]
1674 ; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,2,2,3,4,5,6,7]
1675 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
1676 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm4[0,2,2,3,4,5,6,7]
1677 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm5[0],xmm4[1],xmm5[1]
1678 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[0,2,2,3]
1679 ; SSE-NEXT: pshuflw {{.*#+}} xmm5 = xmm5[0,1,0,2,4,5,6,7]
1680 ; SSE-NEXT: pshufd {{.*#+}} xmm6 = xmm6[0,2,2,3]
1681 ; SSE-NEXT: pshuflw {{.*#+}} xmm6 = xmm6[0,1,0,2,4,5,6,7]
1682 ; SSE-NEXT: punpckldq {{.*#+}} xmm6 = xmm6[0],xmm5[0],xmm6[1],xmm5[1]
1683 ; SSE-NEXT: movsd {{.*#+}} xmm6 = xmm4[0],xmm6[1]
1684 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1685 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
1686 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1687 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
1688 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
1689 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
1690 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
1691 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
1692 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
1693 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
1694 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
1695 ; SSE-NEXT: pmullw %xmm6, %xmm0
1696 ; SSE-NEXT: retq
1697 ;
1698 ; AVX1-LABEL: trunc_mul_v8i64_v8i16:
1699 ; AVX1: # BB#0:
1700 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
1701 ; AVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5
1702 ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3],xmm4[4],xmm5[5,6,7]
1703 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm5[1,2,3],xmm3[4],xmm5[5,6,7]
1704 ; AVX1-NEXT: vpackusdw %xmm4, %xmm3, %xmm3
1705 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
1706 ; AVX1-NEXT: vpblendw {{.*#+}} xmm4 = xmm4[0],xmm5[1,2,3],xmm4[4],xmm5[5,6,7]
1707 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm5[1,2,3],xmm2[4],xmm5[5,6,7]
1708 ; AVX1-NEXT: vpackusdw %xmm4, %xmm2, %xmm2
1709 ; AVX1-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
1710 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
1711 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm5[1,2,3],xmm3[4],xmm5[5,6,7]
1712 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm5[1,2,3],xmm1[4],xmm5[5,6,7]
1713 ; AVX1-NEXT: vpackusdw %xmm3, %xmm1, %xmm1
1714 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
1715 ; AVX1-NEXT: vpblendw {{.*#+}} xmm3 = xmm3[0],xmm5[1,2,3],xmm3[4],xmm5[5,6,7]
1716 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm5[1,2,3],xmm0[4],xmm5[5,6,7]
1717 ; AVX1-NEXT: vpackusdw %xmm3, %xmm0, %xmm0
1718 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
1719 ; AVX1-NEXT: vpmullw %xmm2, %xmm0, %xmm0
1720 ; AVX1-NEXT: vzeroupper
1721 ; AVX1-NEXT: retq
1722 ;
1723 ; AVX2-LABEL: trunc_mul_v8i64_v8i16:
1724 ; AVX2: # BB#0:
1725 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
1726 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1727 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
1728 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
1729 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
1730 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1731 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
1732 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
1733 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
1734 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1735 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
1736 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
1737 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
1738 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
1739 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1740 ; AVX2-NEXT: vpmullw %xmm2, %xmm0, %xmm0
1741 ; AVX2-NEXT: vzeroupper
1742 ; AVX2-NEXT: retq
1743 ;
1744 ; AVX512F-LABEL: trunc_mul_v8i64_v8i16:
1745 ; AVX512F: # BB#0:
1746 ; AVX512F-NEXT: vpmovqw %zmm1, %xmm1
1747 ; AVX512F-NEXT: vpmovqw %zmm0, %xmm0
1748 ; AVX512F-NEXT: vpmullw %xmm1, %xmm0, %xmm0
1749 ; AVX512F-NEXT: vzeroupper
1750 ; AVX512F-NEXT: retq
1751 ;
1752 ; AVX512BW-LABEL: trunc_mul_v8i64_v8i16:
1753 ; AVX512BW: # BB#0:
1754 ; AVX512BW-NEXT: vpmovqw %zmm1, %xmm1
1755 ; AVX512BW-NEXT: vpmovqw %zmm0, %xmm0
1756 ; AVX512BW-NEXT: vpmullw %xmm1, %xmm0, %xmm0
1757 ; AVX512BW-NEXT: vzeroupper
1758 ; AVX512BW-NEXT: retq
1759 ;
1760 ; AVX512DQ-LABEL: trunc_mul_v8i64_v8i16:
1761 ; AVX512DQ: # BB#0:
1762 ; AVX512DQ-NEXT: vpmullq %zmm1, %zmm0, %zmm0
1763 ; AVX512DQ-NEXT: vpmovqw %zmm0, %xmm0
1764 ; AVX512DQ-NEXT: vzeroupper
1765 ; AVX512DQ-NEXT: retq
1766 %1 = mul <8 x i64> %a0, %a1
1767 %2 = trunc <8 x i64> %1 to <8 x i16>
1768 ret <8 x i16> %2
1769 }
1771 define <8 x i16> @trunc_mul_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
1772 ; SSE-LABEL: trunc_mul_v8i32_v8i16:
1773 ; SSE: # BB#0:
1774 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm0[1,1,3,3]
1775 ; SSE-NEXT: pmuludq %xmm2, %xmm0
1776 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
1777 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[1,1,3,3]
1778 ; SSE-NEXT: pmuludq %xmm4, %xmm2
1779 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
1780 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
1781 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,3,3]
1782 ; SSE-NEXT: pmuludq %xmm3, %xmm1
1783 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
1784 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[1,1,3,3]
1785 ; SSE-NEXT: pmuludq %xmm2, %xmm3
1786 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm3[0,2,2,3]
1787 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1]
1788 ; SSE-NEXT: pslld $16, %xmm1
1789 ; SSE-NEXT: psrad $16, %xmm1
1790 ; SSE-NEXT: pslld $16, %xmm0
1791 ; SSE-NEXT: psrad $16, %xmm0
1792 ; SSE-NEXT: packssdw %xmm1, %xmm0
1793 ; SSE-NEXT: retq
1794 ;
1795 ; AVX1-LABEL: trunc_mul_v8i32_v8i16:
1796 ; AVX1: # BB#0:
1797 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm2
1798 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1799 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1800 ; AVX1-NEXT: vpmulld %xmm1, %xmm0, %xmm0
1801 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
1802 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
1803 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
1804 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
1805 ; AVX1-NEXT: vzeroupper
1806 ; AVX1-NEXT: retq
1807 ;
1808 ; AVX2-LABEL: trunc_mul_v8i32_v8i16:
1809 ; AVX2: # BB#0:
1810 ; AVX2-NEXT: vpmulld %ymm1, %ymm0, %ymm0
1811 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
1812 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
1813 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1814 ; AVX2-NEXT: vzeroupper
1815 ; AVX2-NEXT: retq
1816 ;
1817 ; AVX512-LABEL: trunc_mul_v8i32_v8i16:
1818 ; AVX512: # BB#0:
1819 ; AVX512-NEXT: vpmulld %ymm1, %ymm0, %ymm0
1820 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
1821 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
1822 ; AVX512-NEXT: vzeroupper
1823 ; AVX512-NEXT: retq
1824 %1 = mul <8 x i32> %a0, %a1
1825 %2 = trunc <8 x i32> %1 to <8 x i16>
1826 ret <8 x i16> %2
1827 }
1829 define <16 x i8> @trunc_mul_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
1830 ; SSE-LABEL: trunc_mul_v16i64_v16i8:
1831 ; SSE: # BB#0:
1832 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
1833 ; SSE-NEXT: movdqa %xmm0, %xmm9
1834 ; SSE-NEXT: psrlq $32, %xmm9
1835 ; SSE-NEXT: pmuludq %xmm8, %xmm9
1836 ; SSE-NEXT: movdqa %xmm8, %xmm10
1837 ; SSE-NEXT: psrlq $32, %xmm10
1838 ; SSE-NEXT: pmuludq %xmm0, %xmm10
1839 ; SSE-NEXT: paddq %xmm9, %xmm10
1840 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
1841 ; SSE-NEXT: psllq $32, %xmm10
1842 ; SSE-NEXT: pmuludq %xmm8, %xmm0
1843 ; SSE-NEXT: paddq %xmm10, %xmm0
1844 ; SSE-NEXT: movdqa %xmm1, %xmm8
1845 ; SSE-NEXT: psrlq $32, %xmm8
1846 ; SSE-NEXT: pmuludq %xmm9, %xmm8
1847 ; SSE-NEXT: movdqa %xmm9, %xmm10
1848 ; SSE-NEXT: psrlq $32, %xmm10
1849 ; SSE-NEXT: pmuludq %xmm1, %xmm10
1850 ; SSE-NEXT: paddq %xmm8, %xmm10
1851 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
1852 ; SSE-NEXT: psllq $32, %xmm10
1853 ; SSE-NEXT: pmuludq %xmm9, %xmm1
1854 ; SSE-NEXT: paddq %xmm10, %xmm1
1855 ; SSE-NEXT: movdqa %xmm2, %xmm9
1856 ; SSE-NEXT: psrlq $32, %xmm9
1857 ; SSE-NEXT: pmuludq %xmm8, %xmm9
1858 ; SSE-NEXT: movdqa %xmm8, %xmm10
1859 ; SSE-NEXT: psrlq $32, %xmm10
1860 ; SSE-NEXT: pmuludq %xmm2, %xmm10
1861 ; SSE-NEXT: paddq %xmm9, %xmm10
1862 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
1863 ; SSE-NEXT: psllq $32, %xmm10
1864 ; SSE-NEXT: pmuludq %xmm8, %xmm2
1865 ; SSE-NEXT: paddq %xmm10, %xmm2
1866 ; SSE-NEXT: movdqa %xmm3, %xmm8
1867 ; SSE-NEXT: psrlq $32, %xmm8
1868 ; SSE-NEXT: pmuludq %xmm9, %xmm8
1869 ; SSE-NEXT: movdqa %xmm9, %xmm10
1870 ; SSE-NEXT: psrlq $32, %xmm10
1871 ; SSE-NEXT: pmuludq %xmm3, %xmm10
1872 ; SSE-NEXT: paddq %xmm8, %xmm10
1873 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
1874 ; SSE-NEXT: psllq $32, %xmm10
1875 ; SSE-NEXT: pmuludq %xmm9, %xmm3
1876 ; SSE-NEXT: paddq %xmm10, %xmm3
1877 ; SSE-NEXT: movdqa %xmm4, %xmm9
1878 ; SSE-NEXT: psrlq $32, %xmm9
1879 ; SSE-NEXT: pmuludq %xmm8, %xmm9
1880 ; SSE-NEXT: movdqa %xmm8, %xmm10
1881 ; SSE-NEXT: psrlq $32, %xmm10
1882 ; SSE-NEXT: pmuludq %xmm4, %xmm10
1883 ; SSE-NEXT: paddq %xmm9, %xmm10
1884 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
1885 ; SSE-NEXT: psllq $32, %xmm10
1886 ; SSE-NEXT: pmuludq %xmm8, %xmm4
1887 ; SSE-NEXT: paddq %xmm10, %xmm4
1888 ; SSE-NEXT: movdqa %xmm5, %xmm8
1889 ; SSE-NEXT: psrlq $32, %xmm8
1890 ; SSE-NEXT: pmuludq %xmm9, %xmm8
1891 ; SSE-NEXT: movdqa %xmm9, %xmm10
1892 ; SSE-NEXT: psrlq $32, %xmm10
1893 ; SSE-NEXT: pmuludq %xmm5, %xmm10
1894 ; SSE-NEXT: paddq %xmm8, %xmm10
1895 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm8
1896 ; SSE-NEXT: psllq $32, %xmm10
1897 ; SSE-NEXT: pmuludq %xmm9, %xmm5
1898 ; SSE-NEXT: paddq %xmm10, %xmm5
1899 ; SSE-NEXT: movdqa %xmm6, %xmm9
1900 ; SSE-NEXT: psrlq $32, %xmm9
1901 ; SSE-NEXT: pmuludq %xmm8, %xmm9
1902 ; SSE-NEXT: movdqa %xmm8, %xmm10
1903 ; SSE-NEXT: psrlq $32, %xmm10
1904 ; SSE-NEXT: pmuludq %xmm6, %xmm10
1905 ; SSE-NEXT: paddq %xmm9, %xmm10
1906 ; SSE-NEXT: movdqa {{[0-9]+}}(%rsp), %xmm9
1907 ; SSE-NEXT: psllq $32, %xmm10
1908 ; SSE-NEXT: pmuludq %xmm8, %xmm6
1909 ; SSE-NEXT: paddq %xmm10, %xmm6
1910 ; SSE-NEXT: movdqa %xmm7, %xmm8
1911 ; SSE-NEXT: psrlq $32, %xmm8
1912 ; SSE-NEXT: pmuludq %xmm9, %xmm8
1913 ; SSE-NEXT: movdqa %xmm9, %xmm10
1914 ; SSE-NEXT: psrlq $32, %xmm10
1915 ; SSE-NEXT: pmuludq %xmm7, %xmm10
1916 ; SSE-NEXT: paddq %xmm8, %xmm10
1917 ; SSE-NEXT: pmuludq %xmm9, %xmm7
1918 ; SSE-NEXT: psllq $32, %xmm10
1919 ; SSE-NEXT: paddq %xmm10, %xmm7
1920 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
1921 ; SSE-NEXT: pand %xmm8, %xmm7
1922 ; SSE-NEXT: pand %xmm8, %xmm6
1923 ; SSE-NEXT: packuswb %xmm7, %xmm6
1924 ; SSE-NEXT: pand %xmm8, %xmm5
1925 ; SSE-NEXT: pand %xmm8, %xmm4
1926 ; SSE-NEXT: packuswb %xmm5, %xmm4
1927 ; SSE-NEXT: packuswb %xmm6, %xmm4
1928 ; SSE-NEXT: pand %xmm8, %xmm3
1929 ; SSE-NEXT: pand %xmm8, %xmm2
1930 ; SSE-NEXT: packuswb %xmm3, %xmm2
1931 ; SSE-NEXT: pand %xmm8, %xmm1
1932 ; SSE-NEXT: pand %xmm8, %xmm0
1933 ; SSE-NEXT: packuswb %xmm1, %xmm0
1934 ; SSE-NEXT: packuswb %xmm2, %xmm0
1935 ; SSE-NEXT: packuswb %xmm4, %xmm0
1936 ; SSE-NEXT: retq
1937 ;
1938 ; AVX1-LABEL: trunc_mul_v16i64_v16i8:
1939 ; AVX1: # BB#0:
1940 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm8
1941 ; AVX1-NEXT: vpmuludq %xmm4, %xmm8, %xmm8
1942 ; AVX1-NEXT: vpsrlq $32, %xmm4, %xmm9
1943 ; AVX1-NEXT: vpmuludq %xmm9, %xmm0, %xmm9
1944 ; AVX1-NEXT: vpaddq %xmm8, %xmm9, %xmm8
1945 ; AVX1-NEXT: vpsllq $32, %xmm8, %xmm8
1946 ; AVX1-NEXT: vpmuludq %xmm4, %xmm0, %xmm9
1947 ; AVX1-NEXT: vpaddq %xmm8, %xmm9, %xmm8
1948 ; AVX1-NEXT: vextractf128 $1, %ymm4, %xmm9
1949 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
1950 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm4
1951 ; AVX1-NEXT: vpmuludq %xmm9, %xmm4, %xmm10
1952 ; AVX1-NEXT: vpsrlq $32, %xmm9, %xmm4
1953 ; AVX1-NEXT: vpmuludq %xmm4, %xmm0, %xmm4
1954 ; AVX1-NEXT: vpaddq %xmm10, %xmm4, %xmm4
1955 ; AVX1-NEXT: vpsllq $32, %xmm4, %xmm4
1956 ; AVX1-NEXT: vpmuludq %xmm9, %xmm0, %xmm0
1957 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm9
1958 ; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm4
1959 ; AVX1-NEXT: vpmuludq %xmm5, %xmm4, %xmm4
1960 ; AVX1-NEXT: vpsrlq $32, %xmm5, %xmm0
1961 ; AVX1-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
1962 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm0
1963 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
1964 ; AVX1-NEXT: vpmuludq %xmm5, %xmm1, %xmm4
1965 ; AVX1-NEXT: vpaddq %xmm0, %xmm4, %xmm10
1966 ; AVX1-NEXT: vextractf128 $1, %ymm5, %xmm0
1967 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
1968 ; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm5
1969 ; AVX1-NEXT: vpmuludq %xmm0, %xmm5, %xmm5
1970 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm4
1971 ; AVX1-NEXT: vpmuludq %xmm4, %xmm1, %xmm4
1972 ; AVX1-NEXT: vpaddq %xmm5, %xmm4, %xmm4
1973 ; AVX1-NEXT: vpsllq $32, %xmm4, %xmm4
1974 ; AVX1-NEXT: vpmuludq %xmm0, %xmm1, %xmm0
1975 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm1
1976 ; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm0
1977 ; AVX1-NEXT: vpmuludq %xmm6, %xmm0, %xmm0
1978 ; AVX1-NEXT: vpsrlq $32, %xmm6, %xmm4
1979 ; AVX1-NEXT: vpmuludq %xmm4, %xmm2, %xmm4
1980 ; AVX1-NEXT: vpaddq %xmm0, %xmm4, %xmm0
1981 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
1982 ; AVX1-NEXT: vpmuludq %xmm6, %xmm2, %xmm4
1983 ; AVX1-NEXT: vpaddq %xmm0, %xmm4, %xmm5
1984 ; AVX1-NEXT: vextractf128 $1, %ymm6, %xmm0
1985 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
1986 ; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm4
1987 ; AVX1-NEXT: vpmuludq %xmm0, %xmm4, %xmm4
1988 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm6
1989 ; AVX1-NEXT: vpmuludq %xmm6, %xmm2, %xmm6
1990 ; AVX1-NEXT: vpaddq %xmm4, %xmm6, %xmm4
1991 ; AVX1-NEXT: vpsllq $32, %xmm4, %xmm4
1992 ; AVX1-NEXT: vpmuludq %xmm0, %xmm2, %xmm0
1993 ; AVX1-NEXT: vpaddq %xmm4, %xmm0, %xmm0
1994 ; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm2
1995 ; AVX1-NEXT: vpmuludq %xmm7, %xmm2, %xmm2
1996 ; AVX1-NEXT: vpsrlq $32, %xmm7, %xmm4
1997 ; AVX1-NEXT: vpmuludq %xmm4, %xmm3, %xmm4
1998 ; AVX1-NEXT: vpaddq %xmm2, %xmm4, %xmm2
1999 ; AVX1-NEXT: vpsllq $32, %xmm2, %xmm2
2000 ; AVX1-NEXT: vpmuludq %xmm7, %xmm3, %xmm4
2001 ; AVX1-NEXT: vpaddq %xmm2, %xmm4, %xmm2
2002 ; AVX1-NEXT: vextractf128 $1, %ymm7, %xmm4
2003 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
2004 ; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm6
2005 ; AVX1-NEXT: vpmuludq %xmm4, %xmm6, %xmm6
2006 ; AVX1-NEXT: vpsrlq $32, %xmm4, %xmm7
2007 ; AVX1-NEXT: vpmuludq %xmm7, %xmm3, %xmm7
2008 ; AVX1-NEXT: vpaddq %xmm6, %xmm7, %xmm6
2009 ; AVX1-NEXT: vpsllq $32, %xmm6, %xmm6
2010 ; AVX1-NEXT: vpmuludq %xmm4, %xmm3, %xmm3
2011 ; AVX1-NEXT: vpaddq %xmm6, %xmm3, %xmm3
2012 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
2013 ; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
2014 ; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
2015 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
2016 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
2017 ; AVX1-NEXT: vpand %xmm4, %xmm5, %xmm3
2018 ; AVX1-NEXT: vpackuswb %xmm0, %xmm3, %xmm0
2019 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
2020 ; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
2021 ; AVX1-NEXT: vpand %xmm4, %xmm10, %xmm2
2022 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
2023 ; AVX1-NEXT: vpand %xmm4, %xmm9, %xmm2
2024 ; AVX1-NEXT: vpand %xmm4, %xmm8, %xmm3
2025 ; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
2026 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
2027 ; AVX1-NEXT: vpackuswb %xmm0, %xmm1, %xmm0
2028 ; AVX1-NEXT: vzeroupper
2029 ; AVX1-NEXT: retq
2030 ;
2031 ; AVX2-LABEL: trunc_mul_v16i64_v16i8:
2032 ; AVX2: # BB#0:
2033 ; AVX2-NEXT: vpshufd {{.*#+}} ymm7 = ymm7[0,2,2,3,4,6,6,7]
2034 ; AVX2-NEXT: vpermq {{.*#+}} ymm7 = ymm7[0,2,2,3]
2035 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
2036 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
2037 ; AVX2-NEXT: vpmulld %xmm7, %xmm3, %xmm3
2038 ; AVX2-NEXT: vpshufd {{.*#+}} ymm6 = ymm6[0,2,2,3,4,6,6,7]
2039 ; AVX2-NEXT: vpermq {{.*#+}} ymm6 = ymm6[0,2,2,3]
2040 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
2041 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
2042 ; AVX2-NEXT: vpmulld %xmm6, %xmm2, %xmm2
2043 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
2044 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2045 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
2046 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
2047 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm6 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2048 ; AVX2-NEXT: vpshufb %xmm6, %xmm2, %xmm2
2049 ; AVX2-NEXT: vpshufd {{.*#+}} ymm5 = ymm5[0,2,2,3,4,6,6,7]
2050 ; AVX2-NEXT: vpermq {{.*#+}} ymm5 = ymm5[0,2,2,3]
2051 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
2052 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2053 ; AVX2-NEXT: vpmulld %xmm5, %xmm1, %xmm1
2054 ; AVX2-NEXT: vpshufd {{.*#+}} ymm4 = ymm4[0,2,2,3,4,6,6,7]
2055 ; AVX2-NEXT: vpermq {{.*#+}} ymm4 = ymm4[0,2,2,3]
2056 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2057 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2058 ; AVX2-NEXT: vpmulld %xmm4, %xmm0, %xmm0
2059 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
2060 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
2061 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2062 ; AVX2-NEXT: vpshufb %xmm6, %xmm0, %xmm0
2063 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
2064 ; AVX2-NEXT: vzeroupper
2065 ; AVX2-NEXT: retq
2066 ;
2067 ; AVX512F-LABEL: trunc_mul_v16i64_v16i8:
2068 ; AVX512F: # BB#0:
2069 ; AVX512F-NEXT: vpmovqd %zmm3, %ymm3
2070 ; AVX512F-NEXT: vpmovqd %zmm1, %ymm1
2071 ; AVX512F-NEXT: vpmulld %ymm3, %ymm1, %ymm1
2072 ; AVX512F-NEXT: vpmovqd %zmm2, %ymm2
2073 ; AVX512F-NEXT: vpmovqd %zmm0, %ymm0
2074 ; AVX512F-NEXT: vpmulld %ymm2, %ymm0, %ymm0
2075 ; AVX512F-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
2076 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
2077 ; AVX512F-NEXT: vzeroupper
2078 ; AVX512F-NEXT: retq
2079 ;
2080 ; AVX512BW-LABEL: trunc_mul_v16i64_v16i8:
2081 ; AVX512BW: # BB#0:
2082 ; AVX512BW-NEXT: vpmovqd %zmm3, %ymm3
2083 ; AVX512BW-NEXT: vpmovqd %zmm1, %ymm1
2084 ; AVX512BW-NEXT: vpmulld %ymm3, %ymm1, %ymm1
2085 ; AVX512BW-NEXT: vpmovqd %zmm2, %ymm2
2086 ; AVX512BW-NEXT: vpmovqd %zmm0, %ymm0
2087 ; AVX512BW-NEXT: vpmulld %ymm2, %ymm0, %ymm0
2088 ; AVX512BW-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
2089 ; AVX512BW-NEXT: vpmovdb %zmm0, %xmm0
2090 ; AVX512BW-NEXT: vzeroupper
2091 ; AVX512BW-NEXT: retq
2092 ;
2093 ; AVX512DQ-LABEL: trunc_mul_v16i64_v16i8:
2094 ; AVX512DQ: # BB#0:
2095 ; AVX512DQ-NEXT: vpmullq %zmm3, %zmm1, %zmm1
2096 ; AVX512DQ-NEXT: vpmullq %zmm2, %zmm0, %zmm0
2097 ; AVX512DQ-NEXT: vpmovqd %zmm0, %ymm0
2098 ; AVX512DQ-NEXT: vpmovqd %zmm1, %ymm1
2099 ; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
2100 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
2101 ; AVX512DQ-NEXT: vzeroupper
2102 ; AVX512DQ-NEXT: retq
2103 %1 = mul <16 x i64> %a0, %a1
2104 %2 = trunc <16 x i64> %1 to <16 x i8>
2105 ret <16 x i8> %2
2106 }
2108 define <16 x i8> @trunc_mul_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
2109 ; SSE-LABEL: trunc_mul_v16i32_v16i8:
2110 ; SSE: # BB#0:
2111 ; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm0[1,1,3,3]
2112 ; SSE-NEXT: pmuludq %xmm4, %xmm0
2113 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
2114 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
2115 ; SSE-NEXT: pmuludq %xmm8, %xmm4
2116 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
2117 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
2118 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[1,1,3,3]
2119 ; SSE-NEXT: pmuludq %xmm5, %xmm1
2120 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
2121 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm5[1,1,3,3]
2122 ; SSE-NEXT: pmuludq %xmm4, %xmm5
2123 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,2,2,3]
2124 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
2125 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm2[1,1,3,3]
2126 ; SSE-NEXT: pmuludq %xmm6, %xmm2
2127 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
2128 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm6[1,1,3,3]
2129 ; SSE-NEXT: pmuludq %xmm4, %xmm5
2130 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,2,2,3]
2131 ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
2132 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm3[1,1,3,3]
2133 ; SSE-NEXT: pmuludq %xmm7, %xmm3
2134 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
2135 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm7[1,1,3,3]
2136 ; SSE-NEXT: pmuludq %xmm4, %xmm5
2137 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm5[0,2,2,3]
2138 ; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
2139 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
2140 ; SSE-NEXT: pand %xmm4, %xmm3
2141 ; SSE-NEXT: pand %xmm4, %xmm2
2142 ; SSE-NEXT: packuswb %xmm3, %xmm2
2143 ; SSE-NEXT: pand %xmm4, %xmm1
2144 ; SSE-NEXT: pand %xmm4, %xmm0
2145 ; SSE-NEXT: packuswb %xmm1, %xmm0
2146 ; SSE-NEXT: packuswb %xmm2, %xmm0
2147 ; SSE-NEXT: retq
2148 ;
2149 ; AVX1-LABEL: trunc_mul_v16i32_v16i8:
2150 ; AVX1: # BB#0:
2151 ; AVX1-NEXT: vpmulld %xmm2, %xmm0, %xmm4
2152 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
2153 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2154 ; AVX1-NEXT: vpmulld %xmm2, %xmm0, %xmm0
2155 ; AVX1-NEXT: vpmulld %xmm3, %xmm1, %xmm2
2156 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
2157 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2158 ; AVX1-NEXT: vpmulld %xmm3, %xmm1, %xmm1
2159 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
2160 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
2161 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
2162 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
2163 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
2164 ; AVX1-NEXT: vpand %xmm3, %xmm4, %xmm2
2165 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
2166 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
2167 ; AVX1-NEXT: vzeroupper
2168 ; AVX1-NEXT: retq
2169 ;
2170 ; AVX2-LABEL: trunc_mul_v16i32_v16i8:
2171 ; AVX2: # BB#0:
2172 ; AVX2-NEXT: vpmulld %ymm2, %ymm0, %ymm0
2173 ; AVX2-NEXT: vpmulld %ymm3, %ymm1, %ymm1
2174 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2175 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
2176 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2177 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2178 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
2179 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
2180 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2181 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
2182 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2183 ; AVX2-NEXT: vzeroupper
2184 ; AVX2-NEXT: retq
2185 ;
2186 ; AVX512-LABEL: trunc_mul_v16i32_v16i8:
2187 ; AVX512: # BB#0:
2188 ; AVX512-NEXT: vpmulld %zmm1, %zmm0, %zmm0
2189 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
2190 ; AVX512-NEXT: vzeroupper
2191 ; AVX512-NEXT: retq
2192 %1 = mul <16 x i32> %a0, %a1
2193 %2 = trunc <16 x i32> %1 to <16 x i8>
2194 ret <16 x i8> %2
2195 }
2197 define <16 x i8> @trunc_mul_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
2198 ; SSE-LABEL: trunc_mul_v16i16_v16i8:
2199 ; SSE: # BB#0:
2200 ; SSE-NEXT: pmullw %xmm2, %xmm0
2201 ; SSE-NEXT: pmullw %xmm3, %xmm1
2202 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
2203 ; SSE-NEXT: pand %xmm2, %xmm1
2204 ; SSE-NEXT: pand %xmm2, %xmm0
2205 ; SSE-NEXT: packuswb %xmm1, %xmm0
2206 ; SSE-NEXT: retq
2207 ;
2208 ; AVX1-LABEL: trunc_mul_v16i16_v16i8:
2209 ; AVX1: # BB#0:
2210 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm2
2211 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2212 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2213 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
2214 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm1 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2215 ; AVX1-NEXT: vpshufb %xmm1, %xmm0, %xmm0
2216 ; AVX1-NEXT: vpshufb %xmm1, %xmm2, %xmm1
2217 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
2218 ; AVX1-NEXT: vzeroupper
2219 ; AVX1-NEXT: retq
2220 ;
2221 ; AVX2-LABEL: trunc_mul_v16i16_v16i8:
2222 ; AVX2: # BB#0:
2223 ; AVX2-NEXT: vpmullw %ymm1, %ymm0, %ymm0
2224 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
2225 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2226 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
2227 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
2228 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2229 ; AVX2-NEXT: vzeroupper
2230 ; AVX2-NEXT: retq
2231 ;
2232 ; AVX512F-LABEL: trunc_mul_v16i16_v16i8:
2233 ; AVX512F: # BB#0:
2234 ; AVX512F-NEXT: vpmullw %ymm1, %ymm0, %ymm0
2235 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
2236 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
2237 ; AVX512F-NEXT: vzeroupper
2238 ; AVX512F-NEXT: retq
2239 ;
2240 ; AVX512BW-LABEL: trunc_mul_v16i16_v16i8:
2241 ; AVX512BW: # BB#0:
2242 ; AVX512BW-NEXT: vpmullw %ymm1, %ymm0, %ymm0
2243 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
2244 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2245 ; AVX512BW-NEXT: vzeroupper
2246 ; AVX512BW-NEXT: retq
2247 ;
2248 ; AVX512DQ-LABEL: trunc_mul_v16i16_v16i8:
2249 ; AVX512DQ: # BB#0:
2250 ; AVX512DQ-NEXT: vpmullw %ymm1, %ymm0, %ymm0
2251 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
2252 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
2253 ; AVX512DQ-NEXT: vzeroupper
2254 ; AVX512DQ-NEXT: retq
2255 %1 = mul <16 x i16> %a0, %a1
2256 %2 = trunc <16 x i16> %1 to <16 x i8>
2257 ret <16 x i8> %2
2258 }
2260 define <8 x i16> @trunc_mul_v8i32_v8i16_zext_8i8(<16 x i8> %a0, <8 x i32> %a1) {
2261 ; SSE-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
2262 ; SSE: # BB#0:
2263 ; SSE-NEXT: pxor %xmm3, %xmm3
2264 ; SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7]
2265 ; SSE-NEXT: pslld $16, %xmm2
2266 ; SSE-NEXT: psrad $16, %xmm2
2267 ; SSE-NEXT: pslld $16, %xmm1
2268 ; SSE-NEXT: psrad $16, %xmm1
2269 ; SSE-NEXT: packssdw %xmm2, %xmm1
2270 ; SSE-NEXT: pmullw %xmm1, %xmm0
2271 ; SSE-NEXT: retq
2272 ;
2273 ; AVX1-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
2274 ; AVX1: # BB#0:
2275 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
2276 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
2277 ; AVX1-NEXT: vpshufb %xmm3, %xmm2, %xmm2
2278 ; AVX1-NEXT: vpshufb %xmm3, %xmm1, %xmm1
2279 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm2[0]
2280 ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
2281 ; AVX1-NEXT: vpmullw %xmm1, %xmm0, %xmm0
2282 ; AVX1-NEXT: vzeroupper
2283 ; AVX1-NEXT: retq
2284 ;
2285 ; AVX2-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
2286 ; AVX2: # BB#0:
2287 ; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
2288 ; AVX2-NEXT: vpshufb {{.*#+}} ymm1 = ymm1[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2289 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2290 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
2291 ; AVX2-NEXT: vzeroupper
2292 ; AVX2-NEXT: retq
2293 ;
2294 ; AVX512-LABEL: trunc_mul_v8i32_v8i16_zext_8i8:
2295 ; AVX512: # BB#0:
2296 ; AVX512-NEXT: # kill: %ymm1<def> %ymm1<kill> %zmm1<def>
2297 ; AVX512-NEXT: vpmovdw %zmm1, %ymm1
2298 ; AVX512-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
2299 ; AVX512-NEXT: vpmullw %xmm1, %xmm0, %xmm0
2300 ; AVX512-NEXT: vzeroupper
2301 ; AVX512-NEXT: retq
2302 %1 = shufflevector <16 x i8> %a0, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
2303 %2 = zext <8 x i8> %1 to <8 x i32>
2304 %3 = mul <8 x i32> %2, %a1
2305 %4 = trunc <8 x i32> %3 to <8 x i16>
2306 ret <8 x i16> %4
2307 }
2309 ;
2310 ; mul to constant
2311 ;
2313 define <4 x i32> @trunc_mul_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
2314 ; SSE-LABEL: trunc_mul_const_v4i64_v4i32:
2315 ; SSE: # BB#0:
2316 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [2,3]
2317 ; SSE-NEXT: movdqa %xmm1, %xmm3
2318 ; SSE-NEXT: pmuludq %xmm2, %xmm3
2319 ; SSE-NEXT: psrlq $32, %xmm1
2320 ; SSE-NEXT: pmuludq %xmm2, %xmm1
2321 ; SSE-NEXT: psllq $32, %xmm1
2322 ; SSE-NEXT: paddq %xmm3, %xmm1
2323 ; SSE-NEXT: movl $1, %eax
2324 ; SSE-NEXT: movq %rax, %xmm2
2325 ; SSE-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1,2,3,4,5,6,7]
2326 ; SSE-NEXT: movdqa %xmm0, %xmm3
2327 ; SSE-NEXT: pmuludq %xmm2, %xmm3
2328 ; SSE-NEXT: psrlq $32, %xmm0
2329 ; SSE-NEXT: pmuludq %xmm2, %xmm0
2330 ; SSE-NEXT: psllq $32, %xmm0
2331 ; SSE-NEXT: paddq %xmm3, %xmm0
2332 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
2333 ; SSE-NEXT: retq
2334 ;
2335 ; AVX1-LABEL: trunc_mul_const_v4i64_v4i32:
2336 ; AVX1: # BB#0:
2337 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
2338 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
2339 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
2340 ; AVX1-NEXT: vzeroupper
2341 ; AVX1-NEXT: retq
2342 ;
2343 ; AVX2-LABEL: trunc_mul_const_v4i64_v4i32:
2344 ; AVX2: # BB#0:
2345 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2346 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2347 ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
2348 ; AVX2-NEXT: vzeroupper
2349 ; AVX2-NEXT: retq
2350 ;
2351 ; AVX512-LABEL: trunc_mul_const_v4i64_v4i32:
2352 ; AVX512: # BB#0:
2353 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
2354 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
2355 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
2356 ; AVX512-NEXT: vzeroupper
2357 ; AVX512-NEXT: retq
2358 %1 = mul <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
2359 %2 = trunc <4 x i64> %1 to <4 x i32>
2360 ret <4 x i32> %2
2361 }
2363 define <8 x i16> @trunc_mul_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
2364 ; SSE-LABEL: trunc_mul_const_v8i64_v8i16:
2365 ; SSE: # BB#0:
2366 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
2367 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
2368 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
2369 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
2370 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
2371 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
2372 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
2373 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
2374 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
2375 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2376 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
2377 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
2378 ; SSE-NEXT: retq
2379 ;
2380 ; AVX1-LABEL: trunc_mul_const_v8i64_v8i16:
2381 ; AVX1: # BB#0:
2382 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
2383 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
2384 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
2385 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
2386 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
2387 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
2388 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
2389 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
2390 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
2391 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
2392 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2393 ; AVX1-NEXT: vzeroupper
2394 ; AVX1-NEXT: retq
2395 ;
2396 ; AVX2-LABEL: trunc_mul_const_v8i64_v8i16:
2397 ; AVX2: # BB#0:
2398 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2399 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2400 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
2401 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2402 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
2403 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2404 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2405 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2406 ; AVX2-NEXT: vzeroupper
2407 ; AVX2-NEXT: retq
2408 ;
2409 ; AVX512-LABEL: trunc_mul_const_v8i64_v8i16:
2410 ; AVX512: # BB#0:
2411 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
2412 ; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2413 ; AVX512-NEXT: vzeroupper
2414 ; AVX512-NEXT: retq
2415 %1 = mul <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
2416 %2 = trunc <8 x i64> %1 to <8 x i16>
2417 ret <8 x i16> %2
2418 }
2420 define <8 x i16> @trunc_mul_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
2421 ; SSE-LABEL: trunc_mul_const_v8i32_v8i16:
2422 ; SSE: # BB#0:
2423 ; SSE-NEXT: pslld $16, %xmm1
2424 ; SSE-NEXT: psrad $16, %xmm1
2425 ; SSE-NEXT: pslld $16, %xmm0
2426 ; SSE-NEXT: psrad $16, %xmm0
2427 ; SSE-NEXT: packssdw %xmm1, %xmm0
2428 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
2429 ; SSE-NEXT: retq
2430 ;
2431 ; AVX1-LABEL: trunc_mul_const_v8i32_v8i16:
2432 ; AVX1: # BB#0:
2433 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
2434 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
2435 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
2436 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
2437 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2438 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2439 ; AVX1-NEXT: vzeroupper
2440 ; AVX1-NEXT: retq
2441 ;
2442 ; AVX2-LABEL: trunc_mul_const_v8i32_v8i16:
2443 ; AVX2: # BB#0:
2444 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2445 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2446 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2447 ; AVX2-NEXT: vzeroupper
2448 ; AVX2-NEXT: retq
2449 ;
2450 ; AVX512-LABEL: trunc_mul_const_v8i32_v8i16:
2451 ; AVX512: # BB#0:
2452 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
2453 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
2454 ; AVX512-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2455 ; AVX512-NEXT: vzeroupper
2456 ; AVX512-NEXT: retq
2457 %1 = mul <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
2458 %2 = trunc <8 x i32> %1 to <8 x i16>
2459 ret <8 x i16> %2
2460 }
2462 define <16 x i8> @trunc_mul_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
2463 ; SSE-LABEL: trunc_mul_const_v16i64_v16i8:
2464 ; SSE: # BB#0:
2465 ; SSE-NEXT: movl $1, %eax
2466 ; SSE-NEXT: movq %rax, %xmm8
2467 ; SSE-NEXT: pslldq {{.*#+}} xmm8 = zero,zero,zero,zero,zero,zero,zero,zero,xmm8[0,1,2,3,4,5,6,7]
2468 ; SSE-NEXT: movdqa %xmm0, %xmm9
2469 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2470 ; SSE-NEXT: psrlq $32, %xmm0
2471 ; SSE-NEXT: pmuludq %xmm8, %xmm0
2472 ; SSE-NEXT: psllq $32, %xmm0
2473 ; SSE-NEXT: paddq %xmm9, %xmm0
2474 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [2,3]
2475 ; SSE-NEXT: movdqa %xmm1, %xmm9
2476 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2477 ; SSE-NEXT: psrlq $32, %xmm1
2478 ; SSE-NEXT: pmuludq %xmm8, %xmm1
2479 ; SSE-NEXT: psllq $32, %xmm1
2480 ; SSE-NEXT: paddq %xmm9, %xmm1
2481 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [4,5]
2482 ; SSE-NEXT: movdqa %xmm2, %xmm9
2483 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2484 ; SSE-NEXT: psrlq $32, %xmm2
2485 ; SSE-NEXT: pmuludq %xmm8, %xmm2
2486 ; SSE-NEXT: psllq $32, %xmm2
2487 ; SSE-NEXT: paddq %xmm9, %xmm2
2488 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [6,7]
2489 ; SSE-NEXT: movdqa %xmm3, %xmm9
2490 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2491 ; SSE-NEXT: psrlq $32, %xmm3
2492 ; SSE-NEXT: pmuludq %xmm8, %xmm3
2493 ; SSE-NEXT: psllq $32, %xmm3
2494 ; SSE-NEXT: paddq %xmm9, %xmm3
2495 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [8,9]
2496 ; SSE-NEXT: movdqa %xmm4, %xmm9
2497 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2498 ; SSE-NEXT: psrlq $32, %xmm4
2499 ; SSE-NEXT: pmuludq %xmm8, %xmm4
2500 ; SSE-NEXT: psllq $32, %xmm4
2501 ; SSE-NEXT: paddq %xmm9, %xmm4
2502 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [10,11]
2503 ; SSE-NEXT: movdqa %xmm5, %xmm9
2504 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2505 ; SSE-NEXT: psrlq $32, %xmm5
2506 ; SSE-NEXT: pmuludq %xmm8, %xmm5
2507 ; SSE-NEXT: psllq $32, %xmm5
2508 ; SSE-NEXT: paddq %xmm9, %xmm5
2509 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [12,13]
2510 ; SSE-NEXT: movdqa %xmm6, %xmm9
2511 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2512 ; SSE-NEXT: psrlq $32, %xmm6
2513 ; SSE-NEXT: pmuludq %xmm8, %xmm6
2514 ; SSE-NEXT: psllq $32, %xmm6
2515 ; SSE-NEXT: paddq %xmm9, %xmm6
2516 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [14,15]
2517 ; SSE-NEXT: movdqa %xmm7, %xmm9
2518 ; SSE-NEXT: pmuludq %xmm8, %xmm9
2519 ; SSE-NEXT: psrlq $32, %xmm7
2520 ; SSE-NEXT: pmuludq %xmm8, %xmm7
2521 ; SSE-NEXT: psllq $32, %xmm7
2522 ; SSE-NEXT: paddq %xmm9, %xmm7
2523 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
2524 ; SSE-NEXT: pand %xmm8, %xmm7
2525 ; SSE-NEXT: pand %xmm8, %xmm6
2526 ; SSE-NEXT: packuswb %xmm7, %xmm6
2527 ; SSE-NEXT: pand %xmm8, %xmm5
2528 ; SSE-NEXT: pand %xmm8, %xmm4
2529 ; SSE-NEXT: packuswb %xmm5, %xmm4
2530 ; SSE-NEXT: packuswb %xmm6, %xmm4
2531 ; SSE-NEXT: pand %xmm8, %xmm3
2532 ; SSE-NEXT: pand %xmm8, %xmm2
2533 ; SSE-NEXT: packuswb %xmm3, %xmm2
2534 ; SSE-NEXT: pand %xmm8, %xmm1
2535 ; SSE-NEXT: pand %xmm8, %xmm0
2536 ; SSE-NEXT: packuswb %xmm1, %xmm0
2537 ; SSE-NEXT: packuswb %xmm2, %xmm0
2538 ; SSE-NEXT: packuswb %xmm4, %xmm0
2539 ; SSE-NEXT: retq
2540 ;
2541 ; AVX1-LABEL: trunc_mul_const_v16i64_v16i8:
2542 ; AVX1: # BB#0:
2543 ; AVX1-NEXT: movl $1, %eax
2544 ; AVX1-NEXT: vmovq %rax, %xmm4
2545 ; AVX1-NEXT: vpslldq {{.*#+}} xmm4 = zero,zero,zero,zero,zero,zero,zero,zero,xmm4[0,1,2,3,4,5,6,7]
2546 ; AVX1-NEXT: vpmuludq %xmm4, %xmm0, %xmm5
2547 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm6
2548 ; AVX1-NEXT: vpmuludq %xmm4, %xmm6, %xmm4
2549 ; AVX1-NEXT: vpsllq $32, %xmm4, %xmm4
2550 ; AVX1-NEXT: vpaddq %xmm4, %xmm5, %xmm8
2551 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2552 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [2,3]
2553 ; AVX1-NEXT: vpmuludq %xmm5, %xmm0, %xmm6
2554 ; AVX1-NEXT: vpsrlq $32, %xmm0, %xmm0
2555 ; AVX1-NEXT: vpmuludq %xmm5, %xmm0, %xmm0
2556 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
2557 ; AVX1-NEXT: vpaddq %xmm0, %xmm6, %xmm9
2558 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [4,5]
2559 ; AVX1-NEXT: vpmuludq %xmm5, %xmm1, %xmm6
2560 ; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm7
2561 ; AVX1-NEXT: vpmuludq %xmm5, %xmm7, %xmm5
2562 ; AVX1-NEXT: vpsllq $32, %xmm5, %xmm5
2563 ; AVX1-NEXT: vpaddq %xmm5, %xmm6, %xmm5
2564 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2565 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [6,7]
2566 ; AVX1-NEXT: vpmuludq %xmm6, %xmm1, %xmm7
2567 ; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm1
2568 ; AVX1-NEXT: vpmuludq %xmm6, %xmm1, %xmm1
2569 ; AVX1-NEXT: vpsllq $32, %xmm1, %xmm1
2570 ; AVX1-NEXT: vpaddq %xmm1, %xmm7, %xmm1
2571 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [8,9]
2572 ; AVX1-NEXT: vpmuludq %xmm6, %xmm2, %xmm7
2573 ; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm4
2574 ; AVX1-NEXT: vpmuludq %xmm6, %xmm4, %xmm4
2575 ; AVX1-NEXT: vpsllq $32, %xmm4, %xmm4
2576 ; AVX1-NEXT: vpaddq %xmm4, %xmm7, %xmm4
2577 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm2
2578 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [10,11]
2579 ; AVX1-NEXT: vpmuludq %xmm6, %xmm2, %xmm7
2580 ; AVX1-NEXT: vpsrlq $32, %xmm2, %xmm2
2581 ; AVX1-NEXT: vpmuludq %xmm6, %xmm2, %xmm2
2582 ; AVX1-NEXT: vpsllq $32, %xmm2, %xmm2
2583 ; AVX1-NEXT: vpaddq %xmm2, %xmm7, %xmm2
2584 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [12,13]
2585 ; AVX1-NEXT: vpmuludq %xmm6, %xmm3, %xmm7
2586 ; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm0
2587 ; AVX1-NEXT: vpmuludq %xmm6, %xmm0, %xmm0
2588 ; AVX1-NEXT: vpsllq $32, %xmm0, %xmm0
2589 ; AVX1-NEXT: vpaddq %xmm0, %xmm7, %xmm0
2590 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm3
2591 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [14,15]
2592 ; AVX1-NEXT: vpmuludq %xmm6, %xmm3, %xmm7
2593 ; AVX1-NEXT: vpsrlq $32, %xmm3, %xmm3
2594 ; AVX1-NEXT: vpmuludq %xmm6, %xmm3, %xmm3
2595 ; AVX1-NEXT: vpsllq $32, %xmm3, %xmm3
2596 ; AVX1-NEXT: vpaddq %xmm3, %xmm7, %xmm3
2597 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm6 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
2598 ; AVX1-NEXT: vpand %xmm6, %xmm3, %xmm3
2599 ; AVX1-NEXT: vpand %xmm6, %xmm0, %xmm0
2600 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
2601 ; AVX1-NEXT: vpand %xmm6, %xmm2, %xmm2
2602 ; AVX1-NEXT: vpand %xmm6, %xmm4, %xmm3
2603 ; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
2604 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
2605 ; AVX1-NEXT: vpand %xmm6, %xmm1, %xmm1
2606 ; AVX1-NEXT: vpand %xmm6, %xmm5, %xmm2
2607 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
2608 ; AVX1-NEXT: vpand %xmm6, %xmm9, %xmm2
2609 ; AVX1-NEXT: vpand %xmm6, %xmm8, %xmm3
2610 ; AVX1-NEXT: vpackuswb %xmm2, %xmm3, %xmm2
2611 ; AVX1-NEXT: vpackuswb %xmm1, %xmm2, %xmm1
2612 ; AVX1-NEXT: vpackuswb %xmm0, %xmm1, %xmm0
2613 ; AVX1-NEXT: vzeroupper
2614 ; AVX1-NEXT: retq
2615 ;
2616 ; AVX2-LABEL: trunc_mul_const_v16i64_v16i8:
2617 ; AVX2: # BB#0:
2618 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
2619 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
2620 ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm2, %xmm2
2621 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
2622 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
2623 ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm3, %xmm3
2624 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
2625 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2626 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
2627 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
2628 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2629 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
2630 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2631 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2632 ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
2633 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
2634 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2635 ; AVX2-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
2636 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
2637 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
2638 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2639 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
2640 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
2641 ; AVX2-NEXT: vzeroupper
2642 ; AVX2-NEXT: retq
2643 ;
2644 ; AVX512-LABEL: trunc_mul_const_v16i64_v16i8:
2645 ; AVX512: # BB#0:
2646 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
2647 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %ymm0, %ymm0
2648 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
2649 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %ymm1, %ymm1
2650 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
2651 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
2652 ; AVX512-NEXT: vzeroupper
2653 ; AVX512-NEXT: retq
2654 %1 = mul <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
2655 %2 = trunc <16 x i64> %1 to <16 x i8>
2656 ret <16 x i8> %2
2657 }
2659 define <16 x i8> @trunc_mul_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
2660 ; SSE-LABEL: trunc_mul_const_v16i32_v16i8:
2661 ; SSE: # BB#0:
2662 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [0,1,2,3]
2663 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm0[1,1,3,3]
2664 ; SSE-NEXT: pmuludq %xmm4, %xmm0
2665 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
2666 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
2667 ; SSE-NEXT: pmuludq %xmm5, %xmm4
2668 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
2669 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm4[0],xmm0[1],xmm4[1]
2670 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [4,5,6,7]
2671 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm1[1,1,3,3]
2672 ; SSE-NEXT: pmuludq %xmm4, %xmm1
2673 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
2674 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
2675 ; SSE-NEXT: pmuludq %xmm5, %xmm4
2676 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
2677 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
2678 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [8,9,10,11]
2679 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm2[1,1,3,3]
2680 ; SSE-NEXT: pmuludq %xmm4, %xmm2
2681 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[0,2,2,3]
2682 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
2683 ; SSE-NEXT: pmuludq %xmm5, %xmm4
2684 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
2685 ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm4[0],xmm2[1],xmm4[1]
2686 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [12,13,14,15]
2687 ; SSE-NEXT: pshufd {{.*#+}} xmm5 = xmm3[1,1,3,3]
2688 ; SSE-NEXT: pmuludq %xmm4, %xmm3
2689 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm3[0,2,2,3]
2690 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[1,1,3,3]
2691 ; SSE-NEXT: pmuludq %xmm5, %xmm4
2692 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
2693 ; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
2694 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
2695 ; SSE-NEXT: pand %xmm4, %xmm3
2696 ; SSE-NEXT: pand %xmm4, %xmm2
2697 ; SSE-NEXT: packuswb %xmm3, %xmm2
2698 ; SSE-NEXT: pand %xmm4, %xmm1
2699 ; SSE-NEXT: pand %xmm4, %xmm0
2700 ; SSE-NEXT: packuswb %xmm1, %xmm0
2701 ; SSE-NEXT: packuswb %xmm2, %xmm0
2702 ; SSE-NEXT: retq
2703 ;
2704 ; AVX1-LABEL: trunc_mul_const_v16i32_v16i8:
2705 ; AVX1: # BB#0:
2706 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm2
2707 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2708 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm0, %xmm0
2709 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm3
2710 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1
2711 ; AVX1-NEXT: vpmulld {{.*}}(%rip), %xmm1, %xmm1
2712 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
2713 ; AVX1-NEXT: vpand %xmm4, %xmm1, %xmm1
2714 ; AVX1-NEXT: vpand %xmm4, %xmm3, %xmm3
2715 ; AVX1-NEXT: vpackuswb %xmm1, %xmm3, %xmm1
2716 ; AVX1-NEXT: vpand %xmm4, %xmm0, %xmm0
2717 ; AVX1-NEXT: vpand %xmm4, %xmm2, %xmm2
2718 ; AVX1-NEXT: vpackuswb %xmm0, %xmm2, %xmm0
2719 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
2720 ; AVX1-NEXT: vzeroupper
2721 ; AVX1-NEXT: retq
2722 ;
2723 ; AVX2-LABEL: trunc_mul_const_v16i32_v16i8:
2724 ; AVX2: # BB#0:
2725 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2726 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
2727 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2728 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
2729 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2730 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
2731 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
2732 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2733 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2734 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
2735 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2736 ; AVX2-NEXT: vzeroupper
2737 ; AVX2-NEXT: retq
2738 ;
2739 ; AVX512-LABEL: trunc_mul_const_v16i32_v16i8:
2740 ; AVX512: # BB#0:
2741 ; AVX512-NEXT: vpmulld {{.*}}(%rip), %zmm0, %zmm0
2742 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
2743 ; AVX512-NEXT: vzeroupper
2744 ; AVX512-NEXT: retq
2745 %1 = mul <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
2746 %2 = trunc <16 x i32> %1 to <16 x i8>
2747 ret <16 x i8> %2
2748 }
2750 define <16 x i8> @trunc_mul_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
2751 ; SSE-LABEL: trunc_mul_const_v16i16_v16i8:
2752 ; SSE: # BB#0:
2753 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm0
2754 ; SSE-NEXT: pmullw {{.*}}(%rip), %xmm1
2755 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
2756 ; SSE-NEXT: pand %xmm2, %xmm1
2757 ; SSE-NEXT: pand %xmm2, %xmm0
2758 ; SSE-NEXT: packuswb %xmm1, %xmm0
2759 ; SSE-NEXT: retq
2760 ;
2761 ; AVX1-LABEL: trunc_mul_const_v16i16_v16i8:
2762 ; AVX1: # BB#0:
2763 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm1
2764 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0
2765 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
2766 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2767 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
2768 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
2769 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
2770 ; AVX1-NEXT: vzeroupper
2771 ; AVX1-NEXT: retq
2772 ;
2773 ; AVX2-LABEL: trunc_mul_const_v16i16_v16i8:
2774 ; AVX2: # BB#0:
2775 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
2776 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
2777 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
2778 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
2779 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
2780 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2781 ; AVX2-NEXT: vzeroupper
2782 ; AVX2-NEXT: retq
2783 ;
2784 ; AVX512F-LABEL: trunc_mul_const_v16i16_v16i8:
2785 ; AVX512F: # BB#0:
2786 ; AVX512F-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
2787 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
2788 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
2789 ; AVX512F-NEXT: vzeroupper
2790 ; AVX512F-NEXT: retq
2791 ;
2792 ; AVX512BW-LABEL: trunc_mul_const_v16i16_v16i8:
2793 ; AVX512BW: # BB#0:
2794 ; AVX512BW-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
2795 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
2796 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2797 ; AVX512BW-NEXT: vzeroupper
2798 ; AVX512BW-NEXT: retq
2799 ;
2800 ; AVX512DQ-LABEL: trunc_mul_const_v16i16_v16i8:
2801 ; AVX512DQ: # BB#0:
2802 ; AVX512DQ-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
2803 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
2804 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
2805 ; AVX512DQ-NEXT: vzeroupper
2806 ; AVX512DQ-NEXT: retq
2807 %1 = mul <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
2808 %2 = trunc <16 x i16> %1 to <16 x i8>
2809 ret <16 x i8> %2
2810 }
2812 ;
2813 ; and
2814 ;
2816 define <4 x i32> @trunc_and_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
2817 ; SSE-LABEL: trunc_and_v4i64_v4i32:
2818 ; SSE: # BB#0:
2819 ; SSE-NEXT: andps %xmm3, %xmm1
2820 ; SSE-NEXT: andps %xmm2, %xmm0
2821 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
2822 ; SSE-NEXT: retq
2823 ;
2824 ; AVX1-LABEL: trunc_and_v4i64_v4i32:
2825 ; AVX1: # BB#0:
2826 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
2827 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
2828 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
2829 ; AVX1-NEXT: vzeroupper
2830 ; AVX1-NEXT: retq
2831 ;
2832 ; AVX2-LABEL: trunc_and_v4i64_v4i32:
2833 ; AVX2: # BB#0:
2834 ; AVX2-NEXT: vandps %ymm1, %ymm0, %ymm0
2835 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2836 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
2837 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2838 ; AVX2-NEXT: vzeroupper
2839 ; AVX2-NEXT: retq
2840 ;
2841 ; AVX512-LABEL: trunc_and_v4i64_v4i32:
2842 ; AVX512: # BB#0:
2843 ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
2844 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
2845 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2846 ; AVX512-NEXT: vzeroupper
2847 ; AVX512-NEXT: retq
2848 %1 = and <4 x i64> %a0, %a1
2849 %2 = trunc <4 x i64> %1 to <4 x i32>
2850 ret <4 x i32> %2
2851 }
2853 define <8 x i16> @trunc_and_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
2854 ; SSE-LABEL: trunc_and_v8i64_v8i16:
2855 ; SSE: # BB#0:
2856 ; SSE-NEXT: pand %xmm6, %xmm2
2857 ; SSE-NEXT: pand %xmm7, %xmm3
2858 ; SSE-NEXT: pand %xmm4, %xmm0
2859 ; SSE-NEXT: pand %xmm5, %xmm1
2860 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
2861 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
2862 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
2863 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
2864 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
2865 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
2866 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
2867 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
2868 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
2869 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
2870 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
2871 ; SSE-NEXT: retq
2872 ;
2873 ; AVX1-LABEL: trunc_and_v8i64_v8i16:
2874 ; AVX1: # BB#0:
2875 ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
2876 ; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1
2877 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
2878 ; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
2879 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
2880 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
2881 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
2882 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
2883 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
2884 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
2885 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
2886 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
2887 ; AVX1-NEXT: vzeroupper
2888 ; AVX1-NEXT: retq
2889 ;
2890 ; AVX2-LABEL: trunc_and_v8i64_v8i16:
2891 ; AVX2: # BB#0:
2892 ; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1
2893 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
2894 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
2895 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2896 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
2897 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
2898 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
2899 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2900 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2901 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2902 ; AVX2-NEXT: vzeroupper
2903 ; AVX2-NEXT: retq
2904 ;
2905 ; AVX512-LABEL: trunc_and_v8i64_v8i16:
2906 ; AVX512: # BB#0:
2907 ; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
2908 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
2909 ; AVX512-NEXT: vzeroupper
2910 ; AVX512-NEXT: retq
2911 %1 = and <8 x i64> %a0, %a1
2912 %2 = trunc <8 x i64> %1 to <8 x i16>
2913 ret <8 x i16> %2
2914 }
2916 define <8 x i16> @trunc_and_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
2917 ; SSE-LABEL: trunc_and_v8i32_v8i16:
2918 ; SSE: # BB#0:
2919 ; SSE-NEXT: pand %xmm3, %xmm1
2920 ; SSE-NEXT: pslld $16, %xmm1
2921 ; SSE-NEXT: psrad $16, %xmm1
2922 ; SSE-NEXT: pand %xmm2, %xmm0
2923 ; SSE-NEXT: pslld $16, %xmm0
2924 ; SSE-NEXT: psrad $16, %xmm0
2925 ; SSE-NEXT: packssdw %xmm1, %xmm0
2926 ; SSE-NEXT: retq
2927 ;
2928 ; AVX1-LABEL: trunc_and_v8i32_v8i16:
2929 ; AVX1: # BB#0:
2930 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
2931 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
2932 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
2933 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
2934 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
2935 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
2936 ; AVX1-NEXT: vzeroupper
2937 ; AVX1-NEXT: retq
2938 ;
2939 ; AVX2-LABEL: trunc_and_v8i32_v8i16:
2940 ; AVX2: # BB#0:
2941 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
2942 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
2943 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
2944 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2945 ; AVX2-NEXT: vzeroupper
2946 ; AVX2-NEXT: retq
2947 ;
2948 ; AVX512-LABEL: trunc_and_v8i32_v8i16:
2949 ; AVX512: # BB#0:
2950 ; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0
2951 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
2952 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
2953 ; AVX512-NEXT: vzeroupper
2954 ; AVX512-NEXT: retq
2955 %1 = and <8 x i32> %a0, %a1
2956 %2 = trunc <8 x i32> %1 to <8 x i16>
2957 ret <8 x i16> %2
2958 }
2960 define <16 x i8> @trunc_and_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
2961 ; SSE-LABEL: trunc_and_v16i64_v16i8:
2962 ; SSE: # BB#0:
2963 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm0
2964 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm1
2965 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm2
2966 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm3
2967 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm4
2968 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm5
2969 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm6
2970 ; SSE-NEXT: pand {{[0-9]+}}(%rsp), %xmm7
2971 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
2972 ; SSE-NEXT: pand %xmm8, %xmm7
2973 ; SSE-NEXT: pand %xmm8, %xmm6
2974 ; SSE-NEXT: packuswb %xmm7, %xmm6
2975 ; SSE-NEXT: pand %xmm8, %xmm5
2976 ; SSE-NEXT: pand %xmm8, %xmm4
2977 ; SSE-NEXT: packuswb %xmm5, %xmm4
2978 ; SSE-NEXT: packuswb %xmm6, %xmm4
2979 ; SSE-NEXT: pand %xmm8, %xmm3
2980 ; SSE-NEXT: pand %xmm8, %xmm2
2981 ; SSE-NEXT: packuswb %xmm3, %xmm2
2982 ; SSE-NEXT: pand %xmm8, %xmm1
2983 ; SSE-NEXT: pand %xmm8, %xmm0
2984 ; SSE-NEXT: packuswb %xmm1, %xmm0
2985 ; SSE-NEXT: packuswb %xmm2, %xmm0
2986 ; SSE-NEXT: packuswb %xmm4, %xmm0
2987 ; SSE-NEXT: retq
2988 ;
2989 ; AVX1-LABEL: trunc_and_v16i64_v16i8:
2990 ; AVX1: # BB#0:
2991 ; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0
2992 ; AVX1-NEXT: vandps %ymm5, %ymm1, %ymm1
2993 ; AVX1-NEXT: vandps %ymm6, %ymm2, %ymm2
2994 ; AVX1-NEXT: vandps %ymm7, %ymm3, %ymm3
2995 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
2996 ; AVX1-NEXT: vmovaps {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
2997 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
2998 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
2999 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
3000 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
3001 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
3002 ; AVX1-NEXT: vandps %xmm5, %xmm2, %xmm2
3003 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
3004 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
3005 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
3006 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
3007 ; AVX1-NEXT: vandps %xmm5, %xmm1, %xmm1
3008 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
3009 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
3010 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
3011 ; AVX1-NEXT: vandps %xmm5, %xmm0, %xmm0
3012 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
3013 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3014 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3015 ; AVX1-NEXT: vzeroupper
3016 ; AVX1-NEXT: retq
3017 ;
3018 ; AVX2-LABEL: trunc_and_v16i64_v16i8:
3019 ; AVX2: # BB#0:
3020 ; AVX2-NEXT: vpand %ymm5, %ymm1, %ymm1
3021 ; AVX2-NEXT: vpand %ymm4, %ymm0, %ymm0
3022 ; AVX2-NEXT: vpand %ymm7, %ymm3, %ymm3
3023 ; AVX2-NEXT: vpand %ymm6, %ymm2, %ymm2
3024 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
3025 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3026 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
3027 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
3028 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
3029 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3030 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
3031 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3032 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3033 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
3034 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3035 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3036 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3037 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3038 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3039 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
3040 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3041 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
3042 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
3043 ; AVX2-NEXT: vzeroupper
3044 ; AVX2-NEXT: retq
3045 ;
3046 ; AVX512-LABEL: trunc_and_v16i64_v16i8:
3047 ; AVX512: # BB#0:
3048 ; AVX512-NEXT: vpandq %zmm3, %zmm1, %zmm1
3049 ; AVX512-NEXT: vpandq %zmm2, %zmm0, %zmm0
3050 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3051 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
3052 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
3053 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3054 ; AVX512-NEXT: vzeroupper
3055 ; AVX512-NEXT: retq
3056 %1 = and <16 x i64> %a0, %a1
3057 %2 = trunc <16 x i64> %1 to <16 x i8>
3058 ret <16 x i8> %2
3059 }
3061 define <16 x i8> @trunc_and_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
3062 ; SSE-LABEL: trunc_and_v16i32_v16i8:
3063 ; SSE: # BB#0:
3064 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3065 ; SSE-NEXT: pand %xmm8, %xmm7
3066 ; SSE-NEXT: pand %xmm3, %xmm7
3067 ; SSE-NEXT: pand %xmm8, %xmm6
3068 ; SSE-NEXT: pand %xmm2, %xmm6
3069 ; SSE-NEXT: packuswb %xmm7, %xmm6
3070 ; SSE-NEXT: pand %xmm8, %xmm5
3071 ; SSE-NEXT: pand %xmm1, %xmm5
3072 ; SSE-NEXT: pand %xmm8, %xmm4
3073 ; SSE-NEXT: pand %xmm4, %xmm0
3074 ; SSE-NEXT: packuswb %xmm5, %xmm0
3075 ; SSE-NEXT: packuswb %xmm6, %xmm0
3076 ; SSE-NEXT: retq
3077 ;
3078 ; AVX1-LABEL: trunc_and_v16i32_v16i8:
3079 ; AVX1: # BB#0:
3080 ; AVX1-NEXT: vandps %ymm2, %ymm0, %ymm0
3081 ; AVX1-NEXT: vandps %ymm3, %ymm1, %ymm1
3082 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3083 ; AVX1-NEXT: vmovaps {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3084 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
3085 ; AVX1-NEXT: vandps %xmm3, %xmm1, %xmm1
3086 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
3087 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3088 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
3089 ; AVX1-NEXT: vandps %xmm3, %xmm0, %xmm0
3090 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3091 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3092 ; AVX1-NEXT: vzeroupper
3093 ; AVX1-NEXT: retq
3094 ;
3095 ; AVX2-LABEL: trunc_and_v16i32_v16i8:
3096 ; AVX2: # BB#0:
3097 ; AVX2-NEXT: vpand %ymm2, %ymm0, %ymm0
3098 ; AVX2-NEXT: vpand %ymm3, %ymm1, %ymm1
3099 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3100 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
3101 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3102 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3103 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
3104 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
3105 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3106 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
3107 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3108 ; AVX2-NEXT: vzeroupper
3109 ; AVX2-NEXT: retq
3110 ;
3111 ; AVX512-LABEL: trunc_and_v16i32_v16i8:
3112 ; AVX512: # BB#0:
3113 ; AVX512-NEXT: vpandq %zmm1, %zmm0, %zmm0
3114 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3115 ; AVX512-NEXT: vzeroupper
3116 ; AVX512-NEXT: retq
3117 %1 = and <16 x i32> %a0, %a1
3118 %2 = trunc <16 x i32> %1 to <16 x i8>
3119 ret <16 x i8> %2
3120 }
3122 define <16 x i8> @trunc_and_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
3123 ; SSE-LABEL: trunc_and_v16i16_v16i8:
3124 ; SSE: # BB#0:
3125 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255]
3126 ; SSE-NEXT: pand %xmm4, %xmm3
3127 ; SSE-NEXT: pand %xmm1, %xmm3
3128 ; SSE-NEXT: pand %xmm4, %xmm2
3129 ; SSE-NEXT: pand %xmm2, %xmm0
3130 ; SSE-NEXT: packuswb %xmm3, %xmm0
3131 ; SSE-NEXT: retq
3132 ;
3133 ; AVX1-LABEL: trunc_and_v16i16_v16i8:
3134 ; AVX1: # BB#0:
3135 ; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0
3136 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3137 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3138 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3139 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3140 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3141 ; AVX1-NEXT: vzeroupper
3142 ; AVX1-NEXT: retq
3143 ;
3144 ; AVX2-LABEL: trunc_and_v16i16_v16i8:
3145 ; AVX2: # BB#0:
3146 ; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0
3147 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
3148 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3149 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3150 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3151 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3152 ; AVX2-NEXT: vzeroupper
3153 ; AVX2-NEXT: retq
3154 ;
3155 ; AVX512F-LABEL: trunc_and_v16i16_v16i8:
3156 ; AVX512F: # BB#0:
3157 ; AVX512F-NEXT: vpand %ymm1, %ymm0, %ymm0
3158 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
3159 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
3160 ; AVX512F-NEXT: vzeroupper
3161 ; AVX512F-NEXT: retq
3162 ;
3163 ; AVX512BW-LABEL: trunc_and_v16i16_v16i8:
3164 ; AVX512BW: # BB#0:
3165 ; AVX512BW-NEXT: vpand %ymm1, %ymm0, %ymm0
3166 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
3167 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3168 ; AVX512BW-NEXT: vzeroupper
3169 ; AVX512BW-NEXT: retq
3170 ;
3171 ; AVX512DQ-LABEL: trunc_and_v16i16_v16i8:
3172 ; AVX512DQ: # BB#0:
3173 ; AVX512DQ-NEXT: vpand %ymm1, %ymm0, %ymm0
3174 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
3175 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
3176 ; AVX512DQ-NEXT: vzeroupper
3177 ; AVX512DQ-NEXT: retq
3178 %1 = and <16 x i16> %a0, %a1
3179 %2 = trunc <16 x i16> %1 to <16 x i8>
3180 ret <16 x i8> %2
3181 }
3183 ;
3184 ; and to constant
3185 ;
3187 define <4 x i32> @trunc_and_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
3188 ; SSE-LABEL: trunc_and_const_v4i64_v4i32:
3189 ; SSE: # BB#0:
3190 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3191 ; SSE-NEXT: andps {{.*}}(%rip), %xmm0
3192 ; SSE-NEXT: retq
3193 ;
3194 ; AVX1-LABEL: trunc_and_const_v4i64_v4i32:
3195 ; AVX1: # BB#0:
3196 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3197 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3198 ; AVX1-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
3199 ; AVX1-NEXT: vzeroupper
3200 ; AVX1-NEXT: retq
3201 ;
3202 ; AVX2-LABEL: trunc_and_const_v4i64_v4i32:
3203 ; AVX2: # BB#0:
3204 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3205 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
3206 ; AVX2-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
3207 ; AVX2-NEXT: vzeroupper
3208 ; AVX2-NEXT: retq
3209 ;
3210 ; AVX512-LABEL: trunc_and_const_v4i64_v4i32:
3211 ; AVX512: # BB#0:
3212 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
3213 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3214 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3215 ; AVX512-NEXT: vzeroupper
3216 ; AVX512-NEXT: retq
3217 %1 = and <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
3218 %2 = trunc <4 x i64> %1 to <4 x i32>
3219 ret <4 x i32> %2
3220 }
3222 define <8 x i16> @trunc_and_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
3223 ; SSE-LABEL: trunc_and_const_v8i64_v8i16:
3224 ; SSE: # BB#0:
3225 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
3226 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
3227 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
3228 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
3229 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
3230 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
3231 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
3232 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
3233 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
3234 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
3235 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
3236 ; SSE-NEXT: andpd {{.*}}(%rip), %xmm0
3237 ; SSE-NEXT: retq
3238 ;
3239 ; AVX1-LABEL: trunc_and_const_v8i64_v8i16:
3240 ; AVX1: # BB#0:
3241 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3242 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
3243 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3244 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
3245 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
3246 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3247 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3248 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
3249 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
3250 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
3251 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3252 ; AVX1-NEXT: vzeroupper
3253 ; AVX1-NEXT: retq
3254 ;
3255 ; AVX2-LABEL: trunc_and_const_v8i64_v8i16:
3256 ; AVX2: # BB#0:
3257 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3258 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3259 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3260 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3261 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3262 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3263 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3264 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3265 ; AVX2-NEXT: vzeroupper
3266 ; AVX2-NEXT: retq
3267 ;
3268 ; AVX512-LABEL: trunc_and_const_v8i64_v8i16:
3269 ; AVX512: # BB#0:
3270 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
3271 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3272 ; AVX512-NEXT: vzeroupper
3273 ; AVX512-NEXT: retq
3274 %1 = and <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
3275 %2 = trunc <8 x i64> %1 to <8 x i16>
3276 ret <8 x i16> %2
3277 }
3279 define <8 x i16> @trunc_and_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
3280 ; SSE-LABEL: trunc_and_const_v8i32_v8i16:
3281 ; SSE: # BB#0:
3282 ; SSE-NEXT: pslld $16, %xmm1
3283 ; SSE-NEXT: psrad $16, %xmm1
3284 ; SSE-NEXT: pslld $16, %xmm0
3285 ; SSE-NEXT: psrad $16, %xmm0
3286 ; SSE-NEXT: packssdw %xmm1, %xmm0
3287 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
3288 ; SSE-NEXT: retq
3289 ;
3290 ; AVX1-LABEL: trunc_and_const_v8i32_v8i16:
3291 ; AVX1: # BB#0:
3292 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3293 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
3294 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3295 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3296 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3297 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3298 ; AVX1-NEXT: vzeroupper
3299 ; AVX1-NEXT: retq
3300 ;
3301 ; AVX2-LABEL: trunc_and_const_v8i32_v8i16:
3302 ; AVX2: # BB#0:
3303 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3304 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3305 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3306 ; AVX2-NEXT: vzeroupper
3307 ; AVX2-NEXT: retq
3308 ;
3309 ; AVX512-LABEL: trunc_and_const_v8i32_v8i16:
3310 ; AVX512: # BB#0:
3311 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
3312 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
3313 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3314 ; AVX512-NEXT: vzeroupper
3315 ; AVX512-NEXT: retq
3316 %1 = and <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
3317 %2 = trunc <8 x i32> %1 to <8 x i16>
3318 ret <8 x i16> %2
3319 }
3321 define <16 x i8> @trunc_and_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
3322 ; SSE-LABEL: trunc_and_const_v16i64_v16i8:
3323 ; SSE: # BB#0:
3324 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
3325 ; SSE-NEXT: pand %xmm8, %xmm7
3326 ; SSE-NEXT: pand %xmm8, %xmm6
3327 ; SSE-NEXT: packuswb %xmm7, %xmm6
3328 ; SSE-NEXT: pand %xmm8, %xmm5
3329 ; SSE-NEXT: pand %xmm8, %xmm4
3330 ; SSE-NEXT: packuswb %xmm5, %xmm4
3331 ; SSE-NEXT: packuswb %xmm6, %xmm4
3332 ; SSE-NEXT: pand %xmm8, %xmm3
3333 ; SSE-NEXT: pand %xmm8, %xmm2
3334 ; SSE-NEXT: packuswb %xmm3, %xmm2
3335 ; SSE-NEXT: pand %xmm8, %xmm1
3336 ; SSE-NEXT: pand %xmm8, %xmm0
3337 ; SSE-NEXT: packuswb %xmm1, %xmm0
3338 ; SSE-NEXT: packuswb %xmm2, %xmm0
3339 ; SSE-NEXT: packuswb %xmm4, %xmm0
3340 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
3341 ; SSE-NEXT: retq
3342 ;
3343 ; AVX1-LABEL: trunc_and_const_v16i64_v16i8:
3344 ; AVX1: # BB#0:
3345 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
3346 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
3347 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
3348 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
3349 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
3350 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
3351 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
3352 ; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
3353 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
3354 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
3355 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
3356 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
3357 ; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
3358 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
3359 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
3360 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
3361 ; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
3362 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
3363 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3364 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3365 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3366 ; AVX1-NEXT: vzeroupper
3367 ; AVX1-NEXT: retq
3368 ;
3369 ; AVX2-LABEL: trunc_and_const_v16i64_v16i8:
3370 ; AVX2: # BB#0:
3371 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
3372 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3373 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
3374 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
3375 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
3376 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3377 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
3378 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3379 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3380 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
3381 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3382 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3383 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3384 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3385 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3386 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
3387 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3388 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
3389 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
3390 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3391 ; AVX2-NEXT: vzeroupper
3392 ; AVX2-NEXT: retq
3393 ;
3394 ; AVX512-LABEL: trunc_and_const_v16i64_v16i8:
3395 ; AVX512: # BB#0:
3396 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3397 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
3398 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
3399 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3400 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3401 ; AVX512-NEXT: vzeroupper
3402 ; AVX512-NEXT: retq
3403 %1 = and <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
3404 %2 = trunc <16 x i64> %1 to <16 x i8>
3405 ret <16 x i8> %2
3406 }
3408 define <16 x i8> @trunc_and_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
3409 ; SSE-LABEL: trunc_and_const_v16i32_v16i8:
3410 ; SSE: # BB#0:
3411 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3412 ; SSE-NEXT: pand %xmm4, %xmm3
3413 ; SSE-NEXT: pand %xmm4, %xmm2
3414 ; SSE-NEXT: packuswb %xmm3, %xmm2
3415 ; SSE-NEXT: pand %xmm4, %xmm1
3416 ; SSE-NEXT: pand %xmm4, %xmm0
3417 ; SSE-NEXT: packuswb %xmm1, %xmm0
3418 ; SSE-NEXT: packuswb %xmm2, %xmm0
3419 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
3420 ; SSE-NEXT: retq
3421 ;
3422 ; AVX1-LABEL: trunc_and_const_v16i32_v16i8:
3423 ; AVX1: # BB#0:
3424 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3425 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3426 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
3427 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
3428 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
3429 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3430 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
3431 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
3432 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3433 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3434 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3435 ; AVX1-NEXT: vzeroupper
3436 ; AVX1-NEXT: retq
3437 ;
3438 ; AVX2-LABEL: trunc_and_const_v16i32_v16i8:
3439 ; AVX2: # BB#0:
3440 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3441 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
3442 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3443 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3444 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
3445 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
3446 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3447 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
3448 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3449 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3450 ; AVX2-NEXT: vzeroupper
3451 ; AVX2-NEXT: retq
3452 ;
3453 ; AVX512-LABEL: trunc_and_const_v16i32_v16i8:
3454 ; AVX512: # BB#0:
3455 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3456 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3457 ; AVX512-NEXT: vzeroupper
3458 ; AVX512-NEXT: retq
3459 %1 = and <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
3460 %2 = trunc <16 x i32> %1 to <16 x i8>
3461 ret <16 x i8> %2
3462 }
3464 define <16 x i8> @trunc_and_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
3465 ; SSE-LABEL: trunc_and_const_v16i16_v16i8:
3466 ; SSE: # BB#0:
3467 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
3468 ; SSE-NEXT: pand %xmm2, %xmm1
3469 ; SSE-NEXT: pand %xmm2, %xmm0
3470 ; SSE-NEXT: packuswb %xmm1, %xmm0
3471 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
3472 ; SSE-NEXT: retq
3473 ;
3474 ; AVX1-LABEL: trunc_and_const_v16i16_v16i8:
3475 ; AVX1: # BB#0:
3476 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3477 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3478 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3479 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3480 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3481 ; AVX1-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3482 ; AVX1-NEXT: vzeroupper
3483 ; AVX1-NEXT: retq
3484 ;
3485 ; AVX2-LABEL: trunc_and_const_v16i16_v16i8:
3486 ; AVX2: # BB#0:
3487 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
3488 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3489 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3490 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3491 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3492 ; AVX2-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3493 ; AVX2-NEXT: vzeroupper
3494 ; AVX2-NEXT: retq
3495 ;
3496 ; AVX512F-LABEL: trunc_and_const_v16i16_v16i8:
3497 ; AVX512F: # BB#0:
3498 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
3499 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
3500 ; AVX512F-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3501 ; AVX512F-NEXT: vzeroupper
3502 ; AVX512F-NEXT: retq
3503 ;
3504 ; AVX512BW-LABEL: trunc_and_const_v16i16_v16i8:
3505 ; AVX512BW: # BB#0:
3506 ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
3507 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
3508 ; AVX512BW-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3509 ; AVX512BW-NEXT: vzeroupper
3510 ; AVX512BW-NEXT: retq
3511 ;
3512 ; AVX512DQ-LABEL: trunc_and_const_v16i16_v16i8:
3513 ; AVX512DQ: # BB#0:
3514 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
3515 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
3516 ; AVX512DQ-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
3517 ; AVX512DQ-NEXT: vzeroupper
3518 ; AVX512DQ-NEXT: retq
3519 %1 = and <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
3520 %2 = trunc <16 x i16> %1 to <16 x i8>
3521 ret <16 x i8> %2
3522 }
3524 ;
3525 ; xor
3526 ;
3528 define <4 x i32> @trunc_xor_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
3529 ; SSE-LABEL: trunc_xor_v4i64_v4i32:
3530 ; SSE: # BB#0:
3531 ; SSE-NEXT: xorps %xmm3, %xmm1
3532 ; SSE-NEXT: xorps %xmm2, %xmm0
3533 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3534 ; SSE-NEXT: retq
3535 ;
3536 ; AVX1-LABEL: trunc_xor_v4i64_v4i32:
3537 ; AVX1: # BB#0:
3538 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
3539 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3540 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3541 ; AVX1-NEXT: vzeroupper
3542 ; AVX1-NEXT: retq
3543 ;
3544 ; AVX2-LABEL: trunc_xor_v4i64_v4i32:
3545 ; AVX2: # BB#0:
3546 ; AVX2-NEXT: vxorps %ymm1, %ymm0, %ymm0
3547 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3548 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
3549 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3550 ; AVX2-NEXT: vzeroupper
3551 ; AVX2-NEXT: retq
3552 ;
3553 ; AVX512-LABEL: trunc_xor_v4i64_v4i32:
3554 ; AVX512: # BB#0:
3555 ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
3556 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3557 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3558 ; AVX512-NEXT: vzeroupper
3559 ; AVX512-NEXT: retq
3560 %1 = xor <4 x i64> %a0, %a1
3561 %2 = trunc <4 x i64> %1 to <4 x i32>
3562 ret <4 x i32> %2
3563 }
3565 define <8 x i16> @trunc_xor_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
3566 ; SSE-LABEL: trunc_xor_v8i64_v8i16:
3567 ; SSE: # BB#0:
3568 ; SSE-NEXT: pxor %xmm6, %xmm2
3569 ; SSE-NEXT: pxor %xmm7, %xmm3
3570 ; SSE-NEXT: pxor %xmm4, %xmm0
3571 ; SSE-NEXT: pxor %xmm5, %xmm1
3572 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
3573 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
3574 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
3575 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
3576 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
3577 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
3578 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
3579 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
3580 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
3581 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
3582 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
3583 ; SSE-NEXT: retq
3584 ;
3585 ; AVX1-LABEL: trunc_xor_v8i64_v8i16:
3586 ; AVX1: # BB#0:
3587 ; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0
3588 ; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1
3589 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3590 ; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
3591 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3592 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
3593 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
3594 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3595 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3596 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
3597 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
3598 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
3599 ; AVX1-NEXT: vzeroupper
3600 ; AVX1-NEXT: retq
3601 ;
3602 ; AVX2-LABEL: trunc_xor_v8i64_v8i16:
3603 ; AVX2: # BB#0:
3604 ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
3605 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
3606 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3607 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3608 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3609 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3610 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3611 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3612 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3613 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3614 ; AVX2-NEXT: vzeroupper
3615 ; AVX2-NEXT: retq
3616 ;
3617 ; AVX512-LABEL: trunc_xor_v8i64_v8i16:
3618 ; AVX512: # BB#0:
3619 ; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
3620 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
3621 ; AVX512-NEXT: vzeroupper
3622 ; AVX512-NEXT: retq
3623 %1 = xor <8 x i64> %a0, %a1
3624 %2 = trunc <8 x i64> %1 to <8 x i16>
3625 ret <8 x i16> %2
3626 }
3628 define <8 x i16> @trunc_xor_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
3629 ; SSE-LABEL: trunc_xor_v8i32_v8i16:
3630 ; SSE: # BB#0:
3631 ; SSE-NEXT: pxor %xmm3, %xmm1
3632 ; SSE-NEXT: pslld $16, %xmm1
3633 ; SSE-NEXT: psrad $16, %xmm1
3634 ; SSE-NEXT: pxor %xmm2, %xmm0
3635 ; SSE-NEXT: pslld $16, %xmm0
3636 ; SSE-NEXT: psrad $16, %xmm0
3637 ; SSE-NEXT: packssdw %xmm1, %xmm0
3638 ; SSE-NEXT: retq
3639 ;
3640 ; AVX1-LABEL: trunc_xor_v8i32_v8i16:
3641 ; AVX1: # BB#0:
3642 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
3643 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3644 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
3645 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3646 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3647 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3648 ; AVX1-NEXT: vzeroupper
3649 ; AVX1-NEXT: retq
3650 ;
3651 ; AVX2-LABEL: trunc_xor_v8i32_v8i16:
3652 ; AVX2: # BB#0:
3653 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
3654 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3655 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3656 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3657 ; AVX2-NEXT: vzeroupper
3658 ; AVX2-NEXT: retq
3659 ;
3660 ; AVX512-LABEL: trunc_xor_v8i32_v8i16:
3661 ; AVX512: # BB#0:
3662 ; AVX512-NEXT: vpxor %ymm1, %ymm0, %ymm0
3663 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
3664 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3665 ; AVX512-NEXT: vzeroupper
3666 ; AVX512-NEXT: retq
3667 %1 = xor <8 x i32> %a0, %a1
3668 %2 = trunc <8 x i32> %1 to <8 x i16>
3669 ret <8 x i16> %2
3670 }
3672 define <16 x i8> @trunc_xor_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
3673 ; SSE-LABEL: trunc_xor_v16i64_v16i8:
3674 ; SSE: # BB#0:
3675 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm0
3676 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm1
3677 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm2
3678 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm3
3679 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm4
3680 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm5
3681 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm6
3682 ; SSE-NEXT: pxor {{[0-9]+}}(%rsp), %xmm7
3683 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
3684 ; SSE-NEXT: pand %xmm8, %xmm7
3685 ; SSE-NEXT: pand %xmm8, %xmm6
3686 ; SSE-NEXT: packuswb %xmm7, %xmm6
3687 ; SSE-NEXT: pand %xmm8, %xmm5
3688 ; SSE-NEXT: pand %xmm8, %xmm4
3689 ; SSE-NEXT: packuswb %xmm5, %xmm4
3690 ; SSE-NEXT: packuswb %xmm6, %xmm4
3691 ; SSE-NEXT: pand %xmm8, %xmm3
3692 ; SSE-NEXT: pand %xmm8, %xmm2
3693 ; SSE-NEXT: packuswb %xmm3, %xmm2
3694 ; SSE-NEXT: pand %xmm8, %xmm1
3695 ; SSE-NEXT: pand %xmm8, %xmm0
3696 ; SSE-NEXT: packuswb %xmm1, %xmm0
3697 ; SSE-NEXT: packuswb %xmm2, %xmm0
3698 ; SSE-NEXT: packuswb %xmm4, %xmm0
3699 ; SSE-NEXT: retq
3700 ;
3701 ; AVX1-LABEL: trunc_xor_v16i64_v16i8:
3702 ; AVX1: # BB#0:
3703 ; AVX1-NEXT: vxorps %ymm4, %ymm0, %ymm0
3704 ; AVX1-NEXT: vxorps %ymm5, %ymm1, %ymm1
3705 ; AVX1-NEXT: vxorps %ymm6, %ymm2, %ymm2
3706 ; AVX1-NEXT: vxorps %ymm7, %ymm3, %ymm3
3707 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
3708 ; AVX1-NEXT: vmovaps {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
3709 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
3710 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
3711 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
3712 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
3713 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
3714 ; AVX1-NEXT: vandps %xmm5, %xmm2, %xmm2
3715 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
3716 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
3717 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
3718 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
3719 ; AVX1-NEXT: vandps %xmm5, %xmm1, %xmm1
3720 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
3721 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
3722 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
3723 ; AVX1-NEXT: vandps %xmm5, %xmm0, %xmm0
3724 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
3725 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3726 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3727 ; AVX1-NEXT: vzeroupper
3728 ; AVX1-NEXT: retq
3729 ;
3730 ; AVX2-LABEL: trunc_xor_v16i64_v16i8:
3731 ; AVX2: # BB#0:
3732 ; AVX2-NEXT: vpxor %ymm5, %ymm1, %ymm1
3733 ; AVX2-NEXT: vpxor %ymm4, %ymm0, %ymm0
3734 ; AVX2-NEXT: vpxor %ymm7, %ymm3, %ymm3
3735 ; AVX2-NEXT: vpxor %ymm6, %ymm2, %ymm2
3736 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
3737 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3738 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
3739 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
3740 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
3741 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3742 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
3743 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
3744 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3745 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
3746 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3747 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3748 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3749 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3750 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3751 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
3752 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3753 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
3754 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
3755 ; AVX2-NEXT: vzeroupper
3756 ; AVX2-NEXT: retq
3757 ;
3758 ; AVX512-LABEL: trunc_xor_v16i64_v16i8:
3759 ; AVX512: # BB#0:
3760 ; AVX512-NEXT: vpxorq %zmm3, %zmm1, %zmm1
3761 ; AVX512-NEXT: vpxorq %zmm2, %zmm0, %zmm0
3762 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3763 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
3764 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
3765 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3766 ; AVX512-NEXT: vzeroupper
3767 ; AVX512-NEXT: retq
3768 %1 = xor <16 x i64> %a0, %a1
3769 %2 = trunc <16 x i64> %1 to <16 x i8>
3770 ret <16 x i8> %2
3771 }
3773 define <16 x i8> @trunc_xor_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
3774 ; SSE-LABEL: trunc_xor_v16i32_v16i8:
3775 ; SSE: # BB#0:
3776 ; SSE-NEXT: pxor %xmm4, %xmm0
3777 ; SSE-NEXT: pxor %xmm5, %xmm1
3778 ; SSE-NEXT: pxor %xmm6, %xmm2
3779 ; SSE-NEXT: pxor %xmm7, %xmm3
3780 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3781 ; SSE-NEXT: pand %xmm4, %xmm3
3782 ; SSE-NEXT: pand %xmm4, %xmm2
3783 ; SSE-NEXT: packuswb %xmm3, %xmm2
3784 ; SSE-NEXT: pand %xmm4, %xmm1
3785 ; SSE-NEXT: pand %xmm4, %xmm0
3786 ; SSE-NEXT: packuswb %xmm1, %xmm0
3787 ; SSE-NEXT: packuswb %xmm2, %xmm0
3788 ; SSE-NEXT: retq
3789 ;
3790 ; AVX1-LABEL: trunc_xor_v16i32_v16i8:
3791 ; AVX1: # BB#0:
3792 ; AVX1-NEXT: vxorps %ymm2, %ymm0, %ymm0
3793 ; AVX1-NEXT: vxorps %ymm3, %ymm1, %ymm1
3794 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3795 ; AVX1-NEXT: vmovaps {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
3796 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
3797 ; AVX1-NEXT: vandps %xmm3, %xmm1, %xmm1
3798 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
3799 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3800 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
3801 ; AVX1-NEXT: vandps %xmm3, %xmm0, %xmm0
3802 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
3803 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
3804 ; AVX1-NEXT: vzeroupper
3805 ; AVX1-NEXT: retq
3806 ;
3807 ; AVX2-LABEL: trunc_xor_v16i32_v16i8:
3808 ; AVX2: # BB#0:
3809 ; AVX2-NEXT: vpxor %ymm2, %ymm0, %ymm0
3810 ; AVX2-NEXT: vpxor %ymm3, %ymm1, %ymm1
3811 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3812 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
3813 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3814 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3815 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
3816 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
3817 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3818 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
3819 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3820 ; AVX2-NEXT: vzeroupper
3821 ; AVX2-NEXT: retq
3822 ;
3823 ; AVX512-LABEL: trunc_xor_v16i32_v16i8:
3824 ; AVX512: # BB#0:
3825 ; AVX512-NEXT: vpxorq %zmm1, %zmm0, %zmm0
3826 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
3827 ; AVX512-NEXT: vzeroupper
3828 ; AVX512-NEXT: retq
3829 %1 = xor <16 x i32> %a0, %a1
3830 %2 = trunc <16 x i32> %1 to <16 x i8>
3831 ret <16 x i8> %2
3832 }
3834 define <16 x i8> @trunc_xor_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
3835 ; SSE-LABEL: trunc_xor_v16i16_v16i8:
3836 ; SSE: # BB#0:
3837 ; SSE-NEXT: pxor %xmm2, %xmm0
3838 ; SSE-NEXT: pxor %xmm3, %xmm1
3839 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
3840 ; SSE-NEXT: pand %xmm2, %xmm1
3841 ; SSE-NEXT: pand %xmm2, %xmm0
3842 ; SSE-NEXT: packuswb %xmm1, %xmm0
3843 ; SSE-NEXT: retq
3844 ;
3845 ; AVX1-LABEL: trunc_xor_v16i16_v16i8:
3846 ; AVX1: # BB#0:
3847 ; AVX1-NEXT: vxorps %ymm1, %ymm0, %ymm0
3848 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3849 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3850 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3851 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3852 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3853 ; AVX1-NEXT: vzeroupper
3854 ; AVX1-NEXT: retq
3855 ;
3856 ; AVX2-LABEL: trunc_xor_v16i16_v16i8:
3857 ; AVX2: # BB#0:
3858 ; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0
3859 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
3860 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
3861 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
3862 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
3863 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
3864 ; AVX2-NEXT: vzeroupper
3865 ; AVX2-NEXT: retq
3866 ;
3867 ; AVX512F-LABEL: trunc_xor_v16i16_v16i8:
3868 ; AVX512F: # BB#0:
3869 ; AVX512F-NEXT: vpxor %ymm1, %ymm0, %ymm0
3870 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
3871 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
3872 ; AVX512F-NEXT: vzeroupper
3873 ; AVX512F-NEXT: retq
3874 ;
3875 ; AVX512BW-LABEL: trunc_xor_v16i16_v16i8:
3876 ; AVX512BW: # BB#0:
3877 ; AVX512BW-NEXT: vpxor %ymm1, %ymm0, %ymm0
3878 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
3879 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
3880 ; AVX512BW-NEXT: vzeroupper
3881 ; AVX512BW-NEXT: retq
3882 ;
3883 ; AVX512DQ-LABEL: trunc_xor_v16i16_v16i8:
3884 ; AVX512DQ: # BB#0:
3885 ; AVX512DQ-NEXT: vpxor %ymm1, %ymm0, %ymm0
3886 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
3887 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
3888 ; AVX512DQ-NEXT: vzeroupper
3889 ; AVX512DQ-NEXT: retq
3890 %1 = xor <16 x i16> %a0, %a1
3891 %2 = trunc <16 x i16> %1 to <16 x i8>
3892 ret <16 x i8> %2
3893 }
3895 ;
3896 ; xor to constant
3897 ;
3899 define <4 x i32> @trunc_xor_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
3900 ; SSE-LABEL: trunc_xor_const_v4i64_v4i32:
3901 ; SSE: # BB#0:
3902 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3903 ; SSE-NEXT: xorps {{.*}}(%rip), %xmm0
3904 ; SSE-NEXT: retq
3905 ;
3906 ; AVX1-LABEL: trunc_xor_const_v4i64_v4i32:
3907 ; AVX1: # BB#0:
3908 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
3909 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
3910 ; AVX1-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
3911 ; AVX1-NEXT: vzeroupper
3912 ; AVX1-NEXT: retq
3913 ;
3914 ; AVX2-LABEL: trunc_xor_const_v4i64_v4i32:
3915 ; AVX2: # BB#0:
3916 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3917 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
3918 ; AVX2-NEXT: vxorps {{.*}}(%rip), %xmm0, %xmm0
3919 ; AVX2-NEXT: vzeroupper
3920 ; AVX2-NEXT: retq
3921 ;
3922 ; AVX512-LABEL: trunc_xor_const_v4i64_v4i32:
3923 ; AVX512: # BB#0:
3924 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
3925 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
3926 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
3927 ; AVX512-NEXT: vzeroupper
3928 ; AVX512-NEXT: retq
3929 %1 = xor <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
3930 %2 = trunc <4 x i64> %1 to <4 x i32>
3931 ret <4 x i32> %2
3932 }
3934 define <8 x i16> @trunc_xor_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
3935 ; SSE-LABEL: trunc_xor_const_v8i64_v8i16:
3936 ; SSE: # BB#0:
3937 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
3938 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
3939 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
3940 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
3941 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
3942 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
3943 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
3944 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
3945 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
3946 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
3947 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
3948 ; SSE-NEXT: xorpd {{.*}}(%rip), %xmm0
3949 ; SSE-NEXT: retq
3950 ;
3951 ; AVX1-LABEL: trunc_xor_const_v8i64_v8i16:
3952 ; AVX1: # BB#0:
3953 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
3954 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
3955 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3956 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
3957 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
3958 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
3959 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
3960 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
3961 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
3962 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
3963 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
3964 ; AVX1-NEXT: vzeroupper
3965 ; AVX1-NEXT: retq
3966 ;
3967 ; AVX2-LABEL: trunc_xor_const_v8i64_v8i16:
3968 ; AVX2: # BB#0:
3969 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
3970 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3971 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
3972 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
3973 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
3974 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
3975 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
3976 ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
3977 ; AVX2-NEXT: vzeroupper
3978 ; AVX2-NEXT: retq
3979 ;
3980 ; AVX512-LABEL: trunc_xor_const_v8i64_v8i16:
3981 ; AVX512: # BB#0:
3982 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
3983 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
3984 ; AVX512-NEXT: vzeroupper
3985 ; AVX512-NEXT: retq
3986 %1 = xor <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
3987 %2 = trunc <8 x i64> %1 to <8 x i16>
3988 ret <8 x i16> %2
3989 }
3991 define <8 x i16> @trunc_xor_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
3992 ; SSE-LABEL: trunc_xor_const_v8i32_v8i16:
3993 ; SSE: # BB#0:
3994 ; SSE-NEXT: pslld $16, %xmm1
3995 ; SSE-NEXT: psrad $16, %xmm1
3996 ; SSE-NEXT: pslld $16, %xmm0
3997 ; SSE-NEXT: psrad $16, %xmm0
3998 ; SSE-NEXT: packssdw %xmm1, %xmm0
3999 ; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
4000 ; SSE-NEXT: retq
4001 ;
4002 ; AVX1-LABEL: trunc_xor_const_v8i32_v8i16:
4003 ; AVX1: # BB#0:
4004 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4005 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
4006 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4007 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4008 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4009 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4010 ; AVX1-NEXT: vzeroupper
4011 ; AVX1-NEXT: retq
4012 ;
4013 ; AVX2-LABEL: trunc_xor_const_v8i32_v8i16:
4014 ; AVX2: # BB#0:
4015 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4016 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4017 ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4018 ; AVX2-NEXT: vzeroupper
4019 ; AVX2-NEXT: retq
4020 ;
4021 ; AVX512-LABEL: trunc_xor_const_v8i32_v8i16:
4022 ; AVX512: # BB#0:
4023 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
4024 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
4025 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4026 ; AVX512-NEXT: vzeroupper
4027 ; AVX512-NEXT: retq
4028 %1 = xor <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
4029 %2 = trunc <8 x i32> %1 to <8 x i16>
4030 ret <8 x i16> %2
4031 }
4033 define <16 x i8> @trunc_xor_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
4034 ; SSE-LABEL: trunc_xor_const_v16i64_v16i8:
4035 ; SSE: # BB#0:
4036 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4037 ; SSE-NEXT: pand %xmm8, %xmm7
4038 ; SSE-NEXT: pand %xmm8, %xmm6
4039 ; SSE-NEXT: packuswb %xmm7, %xmm6
4040 ; SSE-NEXT: pand %xmm8, %xmm5
4041 ; SSE-NEXT: pand %xmm8, %xmm4
4042 ; SSE-NEXT: packuswb %xmm5, %xmm4
4043 ; SSE-NEXT: packuswb %xmm6, %xmm4
4044 ; SSE-NEXT: pand %xmm8, %xmm3
4045 ; SSE-NEXT: pand %xmm8, %xmm2
4046 ; SSE-NEXT: packuswb %xmm3, %xmm2
4047 ; SSE-NEXT: pand %xmm8, %xmm1
4048 ; SSE-NEXT: pand %xmm8, %xmm0
4049 ; SSE-NEXT: packuswb %xmm1, %xmm0
4050 ; SSE-NEXT: packuswb %xmm2, %xmm0
4051 ; SSE-NEXT: packuswb %xmm4, %xmm0
4052 ; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
4053 ; SSE-NEXT: retq
4054 ;
4055 ; AVX1-LABEL: trunc_xor_const_v16i64_v16i8:
4056 ; AVX1: # BB#0:
4057 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
4058 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4059 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
4060 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4061 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
4062 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
4063 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
4064 ; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
4065 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
4066 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
4067 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
4068 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4069 ; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
4070 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
4071 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
4072 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4073 ; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
4074 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
4075 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4076 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4077 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4078 ; AVX1-NEXT: vzeroupper
4079 ; AVX1-NEXT: retq
4080 ;
4081 ; AVX2-LABEL: trunc_xor_const_v16i64_v16i8:
4082 ; AVX2: # BB#0:
4083 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
4084 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4085 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
4086 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
4087 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
4088 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4089 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
4090 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4091 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4092 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
4093 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4094 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4095 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
4096 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4097 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
4098 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
4099 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4100 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
4101 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
4102 ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4103 ; AVX2-NEXT: vzeroupper
4104 ; AVX2-NEXT: retq
4105 ;
4106 ; AVX512-LABEL: trunc_xor_const_v16i64_v16i8:
4107 ; AVX512: # BB#0:
4108 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
4109 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
4110 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
4111 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4112 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4113 ; AVX512-NEXT: vzeroupper
4114 ; AVX512-NEXT: retq
4115 %1 = xor <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
4116 %2 = trunc <16 x i64> %1 to <16 x i8>
4117 ret <16 x i8> %2
4118 }
4120 define <16 x i8> @trunc_xor_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
4121 ; SSE-LABEL: trunc_xor_const_v16i32_v16i8:
4122 ; SSE: # BB#0:
4123 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4124 ; SSE-NEXT: pand %xmm4, %xmm3
4125 ; SSE-NEXT: pand %xmm4, %xmm2
4126 ; SSE-NEXT: packuswb %xmm3, %xmm2
4127 ; SSE-NEXT: pand %xmm4, %xmm1
4128 ; SSE-NEXT: pand %xmm4, %xmm0
4129 ; SSE-NEXT: packuswb %xmm1, %xmm0
4130 ; SSE-NEXT: packuswb %xmm2, %xmm0
4131 ; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
4132 ; SSE-NEXT: retq
4133 ;
4134 ; AVX1-LABEL: trunc_xor_const_v16i32_v16i8:
4135 ; AVX1: # BB#0:
4136 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
4137 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4138 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
4139 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
4140 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
4141 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
4142 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
4143 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
4144 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4145 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4146 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4147 ; AVX1-NEXT: vzeroupper
4148 ; AVX1-NEXT: retq
4149 ;
4150 ; AVX2-LABEL: trunc_xor_const_v16i32_v16i8:
4151 ; AVX2: # BB#0:
4152 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4153 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
4154 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4155 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4156 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
4157 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
4158 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4159 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
4160 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4161 ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4162 ; AVX2-NEXT: vzeroupper
4163 ; AVX2-NEXT: retq
4164 ;
4165 ; AVX512-LABEL: trunc_xor_const_v16i32_v16i8:
4166 ; AVX512: # BB#0:
4167 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4168 ; AVX512-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4169 ; AVX512-NEXT: vzeroupper
4170 ; AVX512-NEXT: retq
4171 %1 = xor <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
4172 %2 = trunc <16 x i32> %1 to <16 x i8>
4173 ret <16 x i8> %2
4174 }
4176 define <16 x i8> @trunc_xor_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
4177 ; SSE-LABEL: trunc_xor_const_v16i16_v16i8:
4178 ; SSE: # BB#0:
4179 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
4180 ; SSE-NEXT: pand %xmm2, %xmm1
4181 ; SSE-NEXT: pand %xmm2, %xmm0
4182 ; SSE-NEXT: packuswb %xmm1, %xmm0
4183 ; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
4184 ; SSE-NEXT: retq
4185 ;
4186 ; AVX1-LABEL: trunc_xor_const_v16i16_v16i8:
4187 ; AVX1: # BB#0:
4188 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4189 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4190 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4191 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4192 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4193 ; AVX1-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4194 ; AVX1-NEXT: vzeroupper
4195 ; AVX1-NEXT: retq
4196 ;
4197 ; AVX2-LABEL: trunc_xor_const_v16i16_v16i8:
4198 ; AVX2: # BB#0:
4199 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
4200 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4201 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4202 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4203 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4204 ; AVX2-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4205 ; AVX2-NEXT: vzeroupper
4206 ; AVX2-NEXT: retq
4207 ;
4208 ; AVX512F-LABEL: trunc_xor_const_v16i16_v16i8:
4209 ; AVX512F: # BB#0:
4210 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
4211 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
4212 ; AVX512F-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4213 ; AVX512F-NEXT: vzeroupper
4214 ; AVX512F-NEXT: retq
4215 ;
4216 ; AVX512BW-LABEL: trunc_xor_const_v16i16_v16i8:
4217 ; AVX512BW: # BB#0:
4218 ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
4219 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
4220 ; AVX512BW-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4221 ; AVX512BW-NEXT: vzeroupper
4222 ; AVX512BW-NEXT: retq
4223 ;
4224 ; AVX512DQ-LABEL: trunc_xor_const_v16i16_v16i8:
4225 ; AVX512DQ: # BB#0:
4226 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
4227 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
4228 ; AVX512DQ-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
4229 ; AVX512DQ-NEXT: vzeroupper
4230 ; AVX512DQ-NEXT: retq
4231 %1 = xor <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
4232 %2 = trunc <16 x i16> %1 to <16 x i8>
4233 ret <16 x i8> %2
4234 }
4236 ;
4237 ; or
4238 ;
4240 define <4 x i32> @trunc_or_v4i64_v4i32(<4 x i64> %a0, <4 x i64> %a1) nounwind {
4241 ; SSE-LABEL: trunc_or_v4i64_v4i32:
4242 ; SSE: # BB#0:
4243 ; SSE-NEXT: orps %xmm3, %xmm1
4244 ; SSE-NEXT: orps %xmm2, %xmm0
4245 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
4246 ; SSE-NEXT: retq
4247 ;
4248 ; AVX1-LABEL: trunc_or_v4i64_v4i32:
4249 ; AVX1: # BB#0:
4250 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
4251 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4252 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
4253 ; AVX1-NEXT: vzeroupper
4254 ; AVX1-NEXT: retq
4255 ;
4256 ; AVX2-LABEL: trunc_or_v4i64_v4i32:
4257 ; AVX2: # BB#0:
4258 ; AVX2-NEXT: vorps %ymm1, %ymm0, %ymm0
4259 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4260 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
4261 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4262 ; AVX2-NEXT: vzeroupper
4263 ; AVX2-NEXT: retq
4264 ;
4265 ; AVX512-LABEL: trunc_or_v4i64_v4i32:
4266 ; AVX512: # BB#0:
4267 ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
4268 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
4269 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4270 ; AVX512-NEXT: vzeroupper
4271 ; AVX512-NEXT: retq
4272 %1 = or <4 x i64> %a0, %a1
4273 %2 = trunc <4 x i64> %1 to <4 x i32>
4274 ret <4 x i32> %2
4275 }
4277 define <8 x i16> @trunc_or_v8i64_v8i16(<8 x i64> %a0, <8 x i64> %a1) nounwind {
4278 ; SSE-LABEL: trunc_or_v8i64_v8i16:
4279 ; SSE: # BB#0:
4280 ; SSE-NEXT: por %xmm6, %xmm2
4281 ; SSE-NEXT: por %xmm7, %xmm3
4282 ; SSE-NEXT: por %xmm4, %xmm0
4283 ; SSE-NEXT: por %xmm5, %xmm1
4284 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
4285 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
4286 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
4287 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
4288 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
4289 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
4290 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
4291 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
4292 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
4293 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
4294 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
4295 ; SSE-NEXT: retq
4296 ;
4297 ; AVX1-LABEL: trunc_or_v8i64_v8i16:
4298 ; AVX1: # BB#0:
4299 ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
4300 ; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
4301 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
4302 ; AVX1-NEXT: vxorps %xmm3, %xmm3, %xmm3
4303 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
4304 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
4305 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
4306 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
4307 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
4308 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
4309 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
4310 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
4311 ; AVX1-NEXT: vzeroupper
4312 ; AVX1-NEXT: retq
4313 ;
4314 ; AVX2-LABEL: trunc_or_v8i64_v8i16:
4315 ; AVX2: # BB#0:
4316 ; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
4317 ; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
4318 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4319 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4320 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
4321 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4322 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
4323 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4324 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4325 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4326 ; AVX2-NEXT: vzeroupper
4327 ; AVX2-NEXT: retq
4328 ;
4329 ; AVX512-LABEL: trunc_or_v8i64_v8i16:
4330 ; AVX512: # BB#0:
4331 ; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
4332 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
4333 ; AVX512-NEXT: vzeroupper
4334 ; AVX512-NEXT: retq
4335 %1 = or <8 x i64> %a0, %a1
4336 %2 = trunc <8 x i64> %1 to <8 x i16>
4337 ret <8 x i16> %2
4338 }
4340 define <8 x i16> @trunc_or_v8i32_v8i16(<8 x i32> %a0, <8 x i32> %a1) nounwind {
4341 ; SSE-LABEL: trunc_or_v8i32_v8i16:
4342 ; SSE: # BB#0:
4343 ; SSE-NEXT: por %xmm3, %xmm1
4344 ; SSE-NEXT: pslld $16, %xmm1
4345 ; SSE-NEXT: psrad $16, %xmm1
4346 ; SSE-NEXT: por %xmm2, %xmm0
4347 ; SSE-NEXT: pslld $16, %xmm0
4348 ; SSE-NEXT: psrad $16, %xmm0
4349 ; SSE-NEXT: packssdw %xmm1, %xmm0
4350 ; SSE-NEXT: retq
4351 ;
4352 ; AVX1-LABEL: trunc_or_v8i32_v8i16:
4353 ; AVX1: # BB#0:
4354 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
4355 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4356 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
4357 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4358 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4359 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4360 ; AVX1-NEXT: vzeroupper
4361 ; AVX1-NEXT: retq
4362 ;
4363 ; AVX2-LABEL: trunc_or_v8i32_v8i16:
4364 ; AVX2: # BB#0:
4365 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
4366 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4367 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4368 ; AVX2-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4369 ; AVX2-NEXT: vzeroupper
4370 ; AVX2-NEXT: retq
4371 ;
4372 ; AVX512-LABEL: trunc_or_v8i32_v8i16:
4373 ; AVX512: # BB#0:
4374 ; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0
4375 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
4376 ; AVX512-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4377 ; AVX512-NEXT: vzeroupper
4378 ; AVX512-NEXT: retq
4379 %1 = or <8 x i32> %a0, %a1
4380 %2 = trunc <8 x i32> %1 to <8 x i16>
4381 ret <8 x i16> %2
4382 }
4384 define <16 x i8> @trunc_or_v16i64_v16i8(<16 x i64> %a0, <16 x i64> %a1) nounwind {
4385 ; SSE-LABEL: trunc_or_v16i64_v16i8:
4386 ; SSE: # BB#0:
4387 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm0
4388 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm1
4389 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm2
4390 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm3
4391 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm4
4392 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm5
4393 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm6
4394 ; SSE-NEXT: por {{[0-9]+}}(%rsp), %xmm7
4395 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4396 ; SSE-NEXT: pand %xmm8, %xmm7
4397 ; SSE-NEXT: pand %xmm8, %xmm6
4398 ; SSE-NEXT: packuswb %xmm7, %xmm6
4399 ; SSE-NEXT: pand %xmm8, %xmm5
4400 ; SSE-NEXT: pand %xmm8, %xmm4
4401 ; SSE-NEXT: packuswb %xmm5, %xmm4
4402 ; SSE-NEXT: packuswb %xmm6, %xmm4
4403 ; SSE-NEXT: pand %xmm8, %xmm3
4404 ; SSE-NEXT: pand %xmm8, %xmm2
4405 ; SSE-NEXT: packuswb %xmm3, %xmm2
4406 ; SSE-NEXT: pand %xmm8, %xmm1
4407 ; SSE-NEXT: pand %xmm8, %xmm0
4408 ; SSE-NEXT: packuswb %xmm1, %xmm0
4409 ; SSE-NEXT: packuswb %xmm2, %xmm0
4410 ; SSE-NEXT: packuswb %xmm4, %xmm0
4411 ; SSE-NEXT: retq
4412 ;
4413 ; AVX1-LABEL: trunc_or_v16i64_v16i8:
4414 ; AVX1: # BB#0:
4415 ; AVX1-NEXT: vorps %ymm4, %ymm0, %ymm0
4416 ; AVX1-NEXT: vorps %ymm5, %ymm1, %ymm1
4417 ; AVX1-NEXT: vorps %ymm6, %ymm2, %ymm2
4418 ; AVX1-NEXT: vorps %ymm7, %ymm3, %ymm3
4419 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
4420 ; AVX1-NEXT: vmovaps {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4421 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
4422 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
4423 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
4424 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
4425 ; AVX1-NEXT: vandps %xmm5, %xmm4, %xmm4
4426 ; AVX1-NEXT: vandps %xmm5, %xmm2, %xmm2
4427 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
4428 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
4429 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
4430 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
4431 ; AVX1-NEXT: vandps %xmm5, %xmm1, %xmm1
4432 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
4433 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
4434 ; AVX1-NEXT: vandps %xmm5, %xmm3, %xmm3
4435 ; AVX1-NEXT: vandps %xmm5, %xmm0, %xmm0
4436 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
4437 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4438 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4439 ; AVX1-NEXT: vzeroupper
4440 ; AVX1-NEXT: retq
4441 ;
4442 ; AVX2-LABEL: trunc_or_v16i64_v16i8:
4443 ; AVX2: # BB#0:
4444 ; AVX2-NEXT: vpor %ymm5, %ymm1, %ymm1
4445 ; AVX2-NEXT: vpor %ymm4, %ymm0, %ymm0
4446 ; AVX2-NEXT: vpor %ymm7, %ymm3, %ymm3
4447 ; AVX2-NEXT: vpor %ymm6, %ymm2, %ymm2
4448 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
4449 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4450 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
4451 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
4452 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
4453 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4454 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
4455 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4456 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4457 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
4458 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4459 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4460 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
4461 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4462 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
4463 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
4464 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4465 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
4466 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
4467 ; AVX2-NEXT: vzeroupper
4468 ; AVX2-NEXT: retq
4469 ;
4470 ; AVX512-LABEL: trunc_or_v16i64_v16i8:
4471 ; AVX512: # BB#0:
4472 ; AVX512-NEXT: vporq %zmm3, %zmm1, %zmm1
4473 ; AVX512-NEXT: vporq %zmm2, %zmm0, %zmm0
4474 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
4475 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
4476 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
4477 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4478 ; AVX512-NEXT: vzeroupper
4479 ; AVX512-NEXT: retq
4480 %1 = or <16 x i64> %a0, %a1
4481 %2 = trunc <16 x i64> %1 to <16 x i8>
4482 ret <16 x i8> %2
4483 }
4485 define <16 x i8> @trunc_or_v16i32_v16i8(<16 x i32> %a0, <16 x i32> %a1) nounwind {
4486 ; SSE-LABEL: trunc_or_v16i32_v16i8:
4487 ; SSE: # BB#0:
4488 ; SSE-NEXT: por %xmm4, %xmm0
4489 ; SSE-NEXT: por %xmm5, %xmm1
4490 ; SSE-NEXT: por %xmm6, %xmm2
4491 ; SSE-NEXT: por %xmm7, %xmm3
4492 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4493 ; SSE-NEXT: pand %xmm4, %xmm3
4494 ; SSE-NEXT: pand %xmm4, %xmm2
4495 ; SSE-NEXT: packuswb %xmm3, %xmm2
4496 ; SSE-NEXT: pand %xmm4, %xmm1
4497 ; SSE-NEXT: pand %xmm4, %xmm0
4498 ; SSE-NEXT: packuswb %xmm1, %xmm0
4499 ; SSE-NEXT: packuswb %xmm2, %xmm0
4500 ; SSE-NEXT: retq
4501 ;
4502 ; AVX1-LABEL: trunc_or_v16i32_v16i8:
4503 ; AVX1: # BB#0:
4504 ; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
4505 ; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
4506 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
4507 ; AVX1-NEXT: vmovaps {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4508 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
4509 ; AVX1-NEXT: vandps %xmm3, %xmm1, %xmm1
4510 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
4511 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
4512 ; AVX1-NEXT: vandps %xmm3, %xmm2, %xmm2
4513 ; AVX1-NEXT: vandps %xmm3, %xmm0, %xmm0
4514 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4515 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4516 ; AVX1-NEXT: vzeroupper
4517 ; AVX1-NEXT: retq
4518 ;
4519 ; AVX2-LABEL: trunc_or_v16i32_v16i8:
4520 ; AVX2: # BB#0:
4521 ; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
4522 ; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
4523 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4524 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
4525 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4526 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4527 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
4528 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
4529 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4530 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
4531 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4532 ; AVX2-NEXT: vzeroupper
4533 ; AVX2-NEXT: retq
4534 ;
4535 ; AVX512-LABEL: trunc_or_v16i32_v16i8:
4536 ; AVX512: # BB#0:
4537 ; AVX512-NEXT: vporq %zmm1, %zmm0, %zmm0
4538 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4539 ; AVX512-NEXT: vzeroupper
4540 ; AVX512-NEXT: retq
4541 %1 = or <16 x i32> %a0, %a1
4542 %2 = trunc <16 x i32> %1 to <16 x i8>
4543 ret <16 x i8> %2
4544 }
4546 define <16 x i8> @trunc_or_v16i16_v16i8(<16 x i16> %a0, <16 x i16> %a1) nounwind {
4547 ; SSE-LABEL: trunc_or_v16i16_v16i8:
4548 ; SSE: # BB#0:
4549 ; SSE-NEXT: por %xmm2, %xmm0
4550 ; SSE-NEXT: por %xmm3, %xmm1
4551 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
4552 ; SSE-NEXT: pand %xmm2, %xmm1
4553 ; SSE-NEXT: pand %xmm2, %xmm0
4554 ; SSE-NEXT: packuswb %xmm1, %xmm0
4555 ; SSE-NEXT: retq
4556 ;
4557 ; AVX1-LABEL: trunc_or_v16i16_v16i8:
4558 ; AVX1: # BB#0:
4559 ; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0
4560 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4561 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4562 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4563 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4564 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4565 ; AVX1-NEXT: vzeroupper
4566 ; AVX1-NEXT: retq
4567 ;
4568 ; AVX2-LABEL: trunc_or_v16i16_v16i8:
4569 ; AVX2: # BB#0:
4570 ; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0
4571 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
4572 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4573 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4574 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4575 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4576 ; AVX2-NEXT: vzeroupper
4577 ; AVX2-NEXT: retq
4578 ;
4579 ; AVX512F-LABEL: trunc_or_v16i16_v16i8:
4580 ; AVX512F: # BB#0:
4581 ; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
4582 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
4583 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
4584 ; AVX512F-NEXT: vzeroupper
4585 ; AVX512F-NEXT: retq
4586 ;
4587 ; AVX512BW-LABEL: trunc_or_v16i16_v16i8:
4588 ; AVX512BW: # BB#0:
4589 ; AVX512BW-NEXT: vpor %ymm1, %ymm0, %ymm0
4590 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
4591 ; AVX512BW-NEXT: # kill: %xmm0<def> %xmm0<kill> %ymm0<kill>
4592 ; AVX512BW-NEXT: vzeroupper
4593 ; AVX512BW-NEXT: retq
4594 ;
4595 ; AVX512DQ-LABEL: trunc_or_v16i16_v16i8:
4596 ; AVX512DQ: # BB#0:
4597 ; AVX512DQ-NEXT: vpor %ymm1, %ymm0, %ymm0
4598 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
4599 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
4600 ; AVX512DQ-NEXT: vzeroupper
4601 ; AVX512DQ-NEXT: retq
4602 %1 = or <16 x i16> %a0, %a1
4603 %2 = trunc <16 x i16> %1 to <16 x i8>
4604 ret <16 x i8> %2
4605 }
4607 ;
4608 ; or to constant
4609 ;
4611 define <4 x i32> @trunc_or_const_v4i64_v4i32(<4 x i64> %a0) nounwind {
4612 ; SSE-LABEL: trunc_or_const_v4i64_v4i32:
4613 ; SSE: # BB#0:
4614 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
4615 ; SSE-NEXT: orps {{.*}}(%rip), %xmm0
4616 ; SSE-NEXT: retq
4617 ;
4618 ; AVX1-LABEL: trunc_or_const_v4i64_v4i32:
4619 ; AVX1: # BB#0:
4620 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4621 ; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[0,2]
4622 ; AVX1-NEXT: vorps {{.*}}(%rip), %xmm0, %xmm0
4623 ; AVX1-NEXT: vzeroupper
4624 ; AVX1-NEXT: retq
4625 ;
4626 ; AVX2-LABEL: trunc_or_const_v4i64_v4i32:
4627 ; AVX2: # BB#0:
4628 ; AVX2-NEXT: vpermilps {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4629 ; AVX2-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[0,2,2,3]
4630 ; AVX2-NEXT: vorps {{.*}}(%rip), %xmm0, %xmm0
4631 ; AVX2-NEXT: vzeroupper
4632 ; AVX2-NEXT: retq
4633 ;
4634 ; AVX512-LABEL: trunc_or_const_v4i64_v4i32:
4635 ; AVX512: # BB#0:
4636 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
4637 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
4638 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4639 ; AVX512-NEXT: vzeroupper
4640 ; AVX512-NEXT: retq
4641 %1 = or <4 x i64> %a0, <i64 0, i64 1, i64 2, i64 3>
4642 %2 = trunc <4 x i64> %1 to <4 x i32>
4643 ret <4 x i32> %2
4644 }
4646 define <8 x i16> @trunc_or_const_v8i64_v8i16(<8 x i64> %a0) nounwind {
4647 ; SSE-LABEL: trunc_or_const_v8i64_v8i16:
4648 ; SSE: # BB#0:
4649 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,2,2,3]
4650 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,2,2,3,4,5,6,7]
4651 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
4652 ; SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm0[0,2,2,3,4,5,6,7]
4653 ; SSE-NEXT: punpckldq {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1]
4654 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3]
4655 ; SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm0[0,1,0,2,4,5,6,7]
4656 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,2,2,3]
4657 ; SSE-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,0,2,4,5,6,7]
4658 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]
4659 ; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm4[0],xmm0[1]
4660 ; SSE-NEXT: orpd {{.*}}(%rip), %xmm0
4661 ; SSE-NEXT: retq
4662 ;
4663 ; AVX1-LABEL: trunc_or_const_v8i64_v8i16:
4664 ; AVX1: # BB#0:
4665 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
4666 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
4667 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
4668 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3],xmm1[4],xmm3[5,6,7]
4669 ; AVX1-NEXT: vpackusdw %xmm2, %xmm1, %xmm1
4670 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
4671 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm2[0],xmm3[1,2,3],xmm2[4],xmm3[5,6,7]
4672 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm3[1,2,3],xmm0[4],xmm3[5,6,7]
4673 ; AVX1-NEXT: vpackusdw %xmm2, %xmm0, %xmm0
4674 ; AVX1-NEXT: vpackusdw %xmm1, %xmm0, %xmm0
4675 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4676 ; AVX1-NEXT: vzeroupper
4677 ; AVX1-NEXT: retq
4678 ;
4679 ; AVX2-LABEL: trunc_or_const_v8i64_v8i16:
4680 ; AVX2: # BB#0:
4681 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4682 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4683 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
4684 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4685 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
4686 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4687 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4688 ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4689 ; AVX2-NEXT: vzeroupper
4690 ; AVX2-NEXT: retq
4691 ;
4692 ; AVX512-LABEL: trunc_or_const_v8i64_v8i16:
4693 ; AVX512: # BB#0:
4694 ; AVX512-NEXT: vpmovqw %zmm0, %xmm0
4695 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4696 ; AVX512-NEXT: vzeroupper
4697 ; AVX512-NEXT: retq
4698 %1 = or <8 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
4699 %2 = trunc <8 x i64> %1 to <8 x i16>
4700 ret <8 x i16> %2
4701 }
4703 define <8 x i16> @trunc_or_const_v8i32_v8i16(<8 x i32> %a0) nounwind {
4704 ; SSE-LABEL: trunc_or_const_v8i32_v8i16:
4705 ; SSE: # BB#0:
4706 ; SSE-NEXT: pslld $16, %xmm1
4707 ; SSE-NEXT: psrad $16, %xmm1
4708 ; SSE-NEXT: pslld $16, %xmm0
4709 ; SSE-NEXT: psrad $16, %xmm0
4710 ; SSE-NEXT: packssdw %xmm1, %xmm0
4711 ; SSE-NEXT: por {{.*}}(%rip), %xmm0
4712 ; SSE-NEXT: retq
4713 ;
4714 ; AVX1-LABEL: trunc_or_const_v8i32_v8i16:
4715 ; AVX1: # BB#0:
4716 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4717 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
4718 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4719 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4720 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4721 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4722 ; AVX1-NEXT: vzeroupper
4723 ; AVX1-NEXT: retq
4724 ;
4725 ; AVX2-LABEL: trunc_or_const_v8i32_v8i16:
4726 ; AVX2: # BB#0:
4727 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4728 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4729 ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4730 ; AVX2-NEXT: vzeroupper
4731 ; AVX2-NEXT: retq
4732 ;
4733 ; AVX512-LABEL: trunc_or_const_v8i32_v8i16:
4734 ; AVX512: # BB#0:
4735 ; AVX512-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
4736 ; AVX512-NEXT: vpmovdw %zmm0, %ymm0
4737 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4738 ; AVX512-NEXT: vzeroupper
4739 ; AVX512-NEXT: retq
4740 %1 = or <8 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
4741 %2 = trunc <8 x i32> %1 to <8 x i16>
4742 ret <8 x i16> %2
4743 }
4745 define <16 x i8> @trunc_or_const_v16i64_v16i8(<16 x i64> %a0) nounwind {
4746 ; SSE-LABEL: trunc_or_const_v16i64_v16i8:
4747 ; SSE: # BB#0:
4748 ; SSE-NEXT: movdqa {{.*#+}} xmm8 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4749 ; SSE-NEXT: pand %xmm8, %xmm7
4750 ; SSE-NEXT: pand %xmm8, %xmm6
4751 ; SSE-NEXT: packuswb %xmm7, %xmm6
4752 ; SSE-NEXT: pand %xmm8, %xmm5
4753 ; SSE-NEXT: pand %xmm8, %xmm4
4754 ; SSE-NEXT: packuswb %xmm5, %xmm4
4755 ; SSE-NEXT: packuswb %xmm6, %xmm4
4756 ; SSE-NEXT: pand %xmm8, %xmm3
4757 ; SSE-NEXT: pand %xmm8, %xmm2
4758 ; SSE-NEXT: packuswb %xmm3, %xmm2
4759 ; SSE-NEXT: pand %xmm8, %xmm1
4760 ; SSE-NEXT: pand %xmm8, %xmm0
4761 ; SSE-NEXT: packuswb %xmm1, %xmm0
4762 ; SSE-NEXT: packuswb %xmm2, %xmm0
4763 ; SSE-NEXT: packuswb %xmm4, %xmm0
4764 ; SSE-NEXT: por {{.*}}(%rip), %xmm0
4765 ; SSE-NEXT: retq
4766 ;
4767 ; AVX1-LABEL: trunc_or_const_v16i64_v16i8:
4768 ; AVX1: # BB#0:
4769 ; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm4
4770 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [255,0,0,0,0,0,0,0,255,0,0,0,0,0,0,0]
4771 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
4772 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4773 ; AVX1-NEXT: vpackuswb %xmm4, %xmm3, %xmm3
4774 ; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
4775 ; AVX1-NEXT: vpand %xmm5, %xmm4, %xmm4
4776 ; AVX1-NEXT: vpand %xmm5, %xmm2, %xmm2
4777 ; AVX1-NEXT: vpackuswb %xmm4, %xmm2, %xmm2
4778 ; AVX1-NEXT: vpackuswb %xmm3, %xmm2, %xmm2
4779 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
4780 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4781 ; AVX1-NEXT: vpand %xmm5, %xmm1, %xmm1
4782 ; AVX1-NEXT: vpackuswb %xmm3, %xmm1, %xmm1
4783 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
4784 ; AVX1-NEXT: vpand %xmm5, %xmm3, %xmm3
4785 ; AVX1-NEXT: vpand %xmm5, %xmm0, %xmm0
4786 ; AVX1-NEXT: vpackuswb %xmm3, %xmm0, %xmm0
4787 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4788 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4789 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4790 ; AVX1-NEXT: vzeroupper
4791 ; AVX1-NEXT: retq
4792 ;
4793 ; AVX2-LABEL: trunc_or_const_v16i64_v16i8:
4794 ; AVX2: # BB#0:
4795 ; AVX2-NEXT: vpshufd {{.*#+}} ymm2 = ymm2[0,2,2,3,4,6,6,7]
4796 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4797 ; AVX2-NEXT: vpshufd {{.*#+}} ymm3 = ymm3[0,2,2,3,4,6,6,7]
4798 ; AVX2-NEXT: vpermq {{.*#+}} ymm3 = ymm3[0,2,2,3]
4799 ; AVX2-NEXT: vinserti128 $1, %xmm3, %ymm2, %ymm2
4800 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4801 ; AVX2-NEXT: vpshufb %ymm3, %ymm2, %ymm2
4802 ; AVX2-NEXT: vpermq {{.*#+}} ymm2 = ymm2[0,2,2,3]
4803 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm4 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4804 ; AVX2-NEXT: vpshufb %xmm4, %xmm2, %xmm2
4805 ; AVX2-NEXT: vpshufd {{.*#+}} ymm0 = ymm0[0,2,2,3,4,6,6,7]
4806 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4807 ; AVX2-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[0,2,2,3,4,6,6,7]
4808 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4809 ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm0, %ymm0
4810 ; AVX2-NEXT: vpshufb %ymm3, %ymm0, %ymm0
4811 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4812 ; AVX2-NEXT: vpshufb %xmm4, %xmm0, %xmm0
4813 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0]
4814 ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4815 ; AVX2-NEXT: vzeroupper
4816 ; AVX2-NEXT: retq
4817 ;
4818 ; AVX512-LABEL: trunc_or_const_v16i64_v16i8:
4819 ; AVX512: # BB#0:
4820 ; AVX512-NEXT: vpmovqd %zmm0, %ymm0
4821 ; AVX512-NEXT: vpmovqd %zmm1, %ymm1
4822 ; AVX512-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
4823 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4824 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4825 ; AVX512-NEXT: vzeroupper
4826 ; AVX512-NEXT: retq
4827 %1 = or <16 x i64> %a0, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7, i64 8, i64 9, i64 10, i64 11, i64 12, i64 13, i64 14, i64 15>
4828 %2 = trunc <16 x i64> %1 to <16 x i8>
4829 ret <16 x i8> %2
4830 }
4832 define <16 x i8> @trunc_or_const_v16i32_v16i8(<16 x i32> %a0) nounwind {
4833 ; SSE-LABEL: trunc_or_const_v16i32_v16i8:
4834 ; SSE: # BB#0:
4835 ; SSE-NEXT: movdqa {{.*#+}} xmm4 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4836 ; SSE-NEXT: pand %xmm4, %xmm3
4837 ; SSE-NEXT: pand %xmm4, %xmm2
4838 ; SSE-NEXT: packuswb %xmm3, %xmm2
4839 ; SSE-NEXT: pand %xmm4, %xmm1
4840 ; SSE-NEXT: pand %xmm4, %xmm0
4841 ; SSE-NEXT: packuswb %xmm1, %xmm0
4842 ; SSE-NEXT: packuswb %xmm2, %xmm0
4843 ; SSE-NEXT: por {{.*}}(%rip), %xmm0
4844 ; SSE-NEXT: retq
4845 ;
4846 ; AVX1-LABEL: trunc_or_const_v16i32_v16i8:
4847 ; AVX1: # BB#0:
4848 ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm2
4849 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [255,0,0,0,255,0,0,0,255,0,0,0,255,0,0,0]
4850 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
4851 ; AVX1-NEXT: vpand %xmm3, %xmm1, %xmm1
4852 ; AVX1-NEXT: vpackuswb %xmm2, %xmm1, %xmm1
4853 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
4854 ; AVX1-NEXT: vpand %xmm3, %xmm2, %xmm2
4855 ; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
4856 ; AVX1-NEXT: vpackuswb %xmm2, %xmm0, %xmm0
4857 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
4858 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4859 ; AVX1-NEXT: vzeroupper
4860 ; AVX1-NEXT: retq
4861 ;
4862 ; AVX2-LABEL: trunc_or_const_v16i32_v16i8:
4863 ; AVX2: # BB#0:
4864 ; AVX2-NEXT: vmovdqa {{.*#+}} ymm2 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
4865 ; AVX2-NEXT: vpshufb %ymm2, %ymm1, %ymm1
4866 ; AVX2-NEXT: vpermq {{.*#+}} ymm1 = ymm1[0,2,2,3]
4867 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4868 ; AVX2-NEXT: vpshufb %xmm3, %xmm1, %xmm1
4869 ; AVX2-NEXT: vpshufb %ymm2, %ymm0, %ymm0
4870 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
4871 ; AVX2-NEXT: vpshufb %xmm3, %xmm0, %xmm0
4872 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4873 ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4874 ; AVX2-NEXT: vzeroupper
4875 ; AVX2-NEXT: retq
4876 ;
4877 ; AVX512-LABEL: trunc_or_const_v16i32_v16i8:
4878 ; AVX512: # BB#0:
4879 ; AVX512-NEXT: vpmovdb %zmm0, %xmm0
4880 ; AVX512-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4881 ; AVX512-NEXT: vzeroupper
4882 ; AVX512-NEXT: retq
4883 %1 = or <16 x i32> %a0, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
4884 %2 = trunc <16 x i32> %1 to <16 x i8>
4885 ret <16 x i8> %2
4886 }
4888 define <16 x i8> @trunc_or_const_v16i16_v16i8(<16 x i16> %a0) nounwind {
4889 ; SSE-LABEL: trunc_or_const_v16i16_v16i8:
4890 ; SSE: # BB#0:
4891 ; SSE-NEXT: movdqa {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
4892 ; SSE-NEXT: pand %xmm2, %xmm1
4893 ; SSE-NEXT: pand %xmm2, %xmm0
4894 ; SSE-NEXT: packuswb %xmm1, %xmm0
4895 ; SSE-NEXT: por {{.*}}(%rip), %xmm0
4896 ; SSE-NEXT: retq
4897 ;
4898 ; AVX1-LABEL: trunc_or_const_v16i16_v16i8:
4899 ; AVX1: # BB#0:
4900 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
4901 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4902 ; AVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4903 ; AVX1-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4904 ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4905 ; AVX1-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4906 ; AVX1-NEXT: vzeroupper
4907 ; AVX1-NEXT: retq
4908 ;
4909 ; AVX2-LABEL: trunc_or_const_v16i16_v16i8:
4910 ; AVX2: # BB#0:
4911 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
4912 ; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = <0,2,4,6,8,10,12,14,u,u,u,u,u,u,u,u>
4913 ; AVX2-NEXT: vpshufb %xmm2, %xmm1, %xmm1
4914 ; AVX2-NEXT: vpshufb %xmm2, %xmm0, %xmm0
4915 ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
4916 ; AVX2-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4917 ; AVX2-NEXT: vzeroupper
4918 ; AVX2-NEXT: retq
4919 ;
4920 ; AVX512F-LABEL: trunc_or_const_v16i16_v16i8:
4921 ; AVX512F: # BB#0:
4922 ; AVX512F-NEXT: vpmovsxwd %ymm0, %zmm0
4923 ; AVX512F-NEXT: vpmovdb %zmm0, %xmm0
4924 ; AVX512F-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4925 ; AVX512F-NEXT: vzeroupper
4926 ; AVX512F-NEXT: retq
4927 ;
4928 ; AVX512BW-LABEL: trunc_or_const_v16i16_v16i8:
4929 ; AVX512BW: # BB#0:
4930 ; AVX512BW-NEXT: # kill: %ymm0<def> %ymm0<kill> %zmm0<def>
4931 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
4932 ; AVX512BW-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4933 ; AVX512BW-NEXT: vzeroupper
4934 ; AVX512BW-NEXT: retq
4935 ;
4936 ; AVX512DQ-LABEL: trunc_or_const_v16i16_v16i8:
4937 ; AVX512DQ: # BB#0:
4938 ; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0
4939 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
4940 ; AVX512DQ-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm0
4941 ; AVX512DQ-NEXT: vzeroupper
4942 ; AVX512DQ-NEXT: retq
4943 %1 = or <16 x i16> %a0, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>
4944 %2 = trunc <16 x i16> %1 to <16 x i8>
4945 ret <16 x i8> %2
4946 }
4948 ;
4949 ; complex patterns - often created by vectorizer
4950 ;
4952 define <4 x i32> @mul_add_const_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
4953 ; SSE-LABEL: mul_add_const_v4i64_v4i32:
4954 ; SSE: # BB#0:
4955 ; SSE-NEXT: movdqa %xmm0, %xmm2
4956 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm2[0,1,1,3]
4957 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,1,3,3]
4958 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[0,1,1,3]
4959 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
4960 ; SSE-NEXT: movdqa %xmm2, %xmm4
4961 ; SSE-NEXT: psrlq $32, %xmm4
4962 ; SSE-NEXT: pmuludq %xmm1, %xmm4
4963 ; SSE-NEXT: movdqa %xmm1, %xmm5
4964 ; SSE-NEXT: psrlq $32, %xmm5
4965 ; SSE-NEXT: pmuludq %xmm2, %xmm5
4966 ; SSE-NEXT: paddq %xmm4, %xmm5
4967 ; SSE-NEXT: psllq $32, %xmm5
4968 ; SSE-NEXT: pmuludq %xmm1, %xmm2
4969 ; SSE-NEXT: paddq %xmm5, %xmm2
4970 ; SSE-NEXT: movdqa %xmm0, %xmm1
4971 ; SSE-NEXT: psrlq $32, %xmm1
4972 ; SSE-NEXT: pmuludq %xmm3, %xmm1
4973 ; SSE-NEXT: movdqa %xmm3, %xmm4
4974 ; SSE-NEXT: psrlq $32, %xmm4
4975 ; SSE-NEXT: pmuludq %xmm0, %xmm4
4976 ; SSE-NEXT: paddq %xmm1, %xmm4
4977 ; SSE-NEXT: psllq $32, %xmm4
4978 ; SSE-NEXT: pmuludq %xmm3, %xmm0
4979 ; SSE-NEXT: paddq %xmm4, %xmm0
4980 ; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm2[0,2]
4981 ; SSE-NEXT: paddd {{.*}}(%rip), %xmm0
4982 ; SSE-NEXT: retq
4983 ;
4984 ; AVX-LABEL: mul_add_const_v4i64_v4i32:
4985 ; AVX: # BB#0:
4986 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
4987 ; AVX-NEXT: vpaddd {{.*}}(%rip), %xmm0, %xmm0
4988 ; AVX-NEXT: retq
4989 %1 = sext <4 x i32> %a0 to <4 x i64>
4990 %2 = sext <4 x i32> %a1 to <4 x i64>
4991 %3 = mul <4 x i64> %1, %2
4992 %4 = add <4 x i64> %3, <i64 -3, i64 -1, i64 1, i64 3>
4993 %5 = trunc <4 x i64> %4 to <4 x i32>
4994 ret <4 x i32> %5
4995 }
4997 define <4 x i32> @mul_add_self_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
4998 ; SSE-LABEL: mul_add_self_v4i64_v4i32:
4999 ; SSE: # BB#0:
5000 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
5001 ; SSE-NEXT: movdqa %xmm2, %xmm3
5002 ; SSE-NEXT: psrad $31, %xmm3
5003 ; SSE-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1]
5004 ; SSE-NEXT: movdqa %xmm0, %xmm3
5005 ; SSE-NEXT: psrad $31, %xmm3
5006 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1]
5007 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
5008 ; SSE-NEXT: movdqa %xmm3, %xmm4
5009 ; SSE-NEXT: psrad $31, %xmm4
5010 ; SSE-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm4[0],xmm3[1],xmm4[1]
5011 ; SSE-NEXT: movdqa %xmm1, %xmm4
5012 ; SSE-NEXT: psrad $31, %xmm4
5013 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1]
5014 ; SSE-NEXT: movdqa %xmm0, %xmm4
5015 ; SSE-NEXT: psrlq $32, %xmm4
5016 ; SSE-NEXT: pmuludq %xmm1, %xmm4
5017 ; SSE-NEXT: movdqa %xmm1, %xmm5
5018 ; SSE-NEXT: psrlq $32, %xmm5
5019 ; SSE-NEXT: pmuludq %xmm0, %xmm5
5020 ; SSE-NEXT: paddq %xmm4, %xmm5
5021 ; SSE-NEXT: psllq $32, %xmm5
5022 ; SSE-NEXT: pmuludq %xmm0, %xmm1
5023 ; SSE-NEXT: paddq %xmm5, %xmm1
5024 ; SSE-NEXT: movdqa %xmm2, %xmm0
5025 ; SSE-NEXT: psrlq $32, %xmm0
5026 ; SSE-NEXT: pmuludq %xmm3, %xmm0
5027 ; SSE-NEXT: movdqa %xmm3, %xmm4
5028 ; SSE-NEXT: psrlq $32, %xmm4
5029 ; SSE-NEXT: pmuludq %xmm2, %xmm4
5030 ; SSE-NEXT: paddq %xmm0, %xmm4
5031 ; SSE-NEXT: psllq $32, %xmm4
5032 ; SSE-NEXT: pmuludq %xmm2, %xmm3
5033 ; SSE-NEXT: paddq %xmm4, %xmm3
5034 ; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,2],xmm3[0,2]
5035 ; SSE-NEXT: paddd %xmm1, %xmm1
5036 ; SSE-NEXT: movdqa %xmm1, %xmm0
5037 ; SSE-NEXT: retq
5038 ;
5039 ; AVX-LABEL: mul_add_self_v4i64_v4i32:
5040 ; AVX: # BB#0:
5041 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm0
5042 ; AVX-NEXT: vpaddd %xmm0, %xmm0, %xmm0
5043 ; AVX-NEXT: retq
5044 %1 = sext <4 x i32> %a0 to <4 x i64>
5045 %2 = sext <4 x i32> %a1 to <4 x i64>
5046 %3 = mul <4 x i64> %1, %2
5047 %4 = add <4 x i64> %3, %3
5048 %5 = trunc <4 x i64> %4 to <4 x i32>
5049 ret <4 x i32> %5
5050 }
5052 define <4 x i32> @mul_add_multiuse_v4i64_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind {
5053 ; SSE-LABEL: mul_add_multiuse_v4i64_v4i32:
5054 ; SSE: # BB#0:
5055 ; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,1,1,3]
5056 ; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3]
5057 ; SSE-NEXT: pshufd {{.*#+}} xmm4 = xmm1[0,1,1,3]
5058 ; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,1,3,3]
5059 ; SSE-NEXT: movdqa %xmm3, %xmm5
5060 ; SSE-NEXT: psrlq $32, %xmm5
5061 ; SSE-NEXT: pmuludq %xmm1, %xmm5
5062 ; SSE-NEXT: movdqa %xmm1, %xmm6
5063 ; SSE-NEXT: psrlq $32, %xmm6
5064 ; SSE-NEXT: pmuludq %xmm3, %xmm6
5065 ; SSE-NEXT: paddq %xmm5, %xmm6
5066 ; SSE-NEXT: psllq $32, %xmm6
5067 ; SSE-NEXT: pmuludq %xmm1, %xmm3
5068 ; SSE-NEXT: paddq %xmm6, %xmm3
5069 ; SSE-NEXT: movdqa %xmm2, %xmm1
5070 ; SSE-NEXT: psrlq $32, %xmm1
5071 ; SSE-NEXT: pmuludq %xmm4, %xmm1
5072 ; SSE-NEXT: movdqa %xmm4, %xmm5
5073 ; SSE-NEXT: psrlq $32, %xmm5
5074 ; SSE-NEXT: pmuludq %xmm2, %xmm5
5075 ; SSE-NEXT: paddq %xmm1, %xmm5
5076 ; SSE-NEXT: psllq $32, %xmm5
5077 ; SSE-NEXT: pmuludq %xmm4, %xmm2
5078 ; SSE-NEXT: paddq %xmm5, %xmm2
5079 ; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,2],xmm3[0,2]
5080 ; SSE-NEXT: paddd %xmm2, %xmm0
5081 ; SSE-NEXT: retq
5082 ;
5083 ; AVX-LABEL: mul_add_multiuse_v4i64_v4i32:
5084 ; AVX: # BB#0:
5085 ; AVX-NEXT: vpmulld %xmm1, %xmm0, %xmm1
5086 ; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
5087 ; AVX-NEXT: retq
5088 %1 = sext <4 x i32> %a0 to <4 x i64>
5089 %2 = sext <4 x i32> %a1 to <4 x i64>
5090 %3 = mul <4 x i64> %1, %2
5091 %4 = add <4 x i64> %1, %3
5092 %5 = trunc <4 x i64> %4 to <4 x i32>
5093 ret <4 x i32> %5
5094 }