[ASan] Make insertion of version mismatch guard configurable
[llvm-core.git] / lib / MC / MCRegisterInfo.cpp
blob7c7376d906f7d9d9742186b8a480148f7543b6ac
1 //===- MC/MCRegisterInfo.cpp - Target Register Description ----------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements MCRegisterInfo functions.
11 //===----------------------------------------------------------------------===//
13 #include "llvm/MC/MCRegisterInfo.h"
14 #include "llvm/ADT/DenseMap.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/Support/ErrorHandling.h"
17 #include <algorithm>
18 #include <cassert>
19 #include <cstdint>
21 using namespace llvm;
23 MCRegister
24 MCRegisterInfo::getMatchingSuperReg(MCRegister Reg, unsigned SubIdx,
25 const MCRegisterClass *RC) const {
26 for (MCSuperRegIterator Supers(Reg, this); Supers.isValid(); ++Supers)
27 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
28 return *Supers;
29 return 0;
32 MCRegister MCRegisterInfo::getSubReg(MCRegister Reg, unsigned Idx) const {
33 assert(Idx && Idx < getNumSubRegIndices() &&
34 "This is not a subregister index");
35 // Get a pointer to the corresponding SubRegIndices list. This list has the
36 // name of each sub-register in the same order as MCSubRegIterator.
37 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
38 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
39 if (*SRI == Idx)
40 return *Subs;
41 return 0;
44 unsigned MCRegisterInfo::getSubRegIndex(MCRegister Reg,
45 MCRegister SubReg) const {
46 assert(SubReg && SubReg < getNumRegs() && "This is not a register");
47 // Get a pointer to the corresponding SubRegIndices list. This list has the
48 // name of each sub-register in the same order as MCSubRegIterator.
49 const uint16_t *SRI = SubRegIndices + get(Reg).SubRegIndices;
50 for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++SRI)
51 if (*Subs == SubReg)
52 return *SRI;
53 return 0;
56 unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const {
57 assert(Idx && Idx < getNumSubRegIndices() &&
58 "This is not a subregister index");
59 return SubRegIdxRanges[Idx].Size;
62 unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const {
63 assert(Idx && Idx < getNumSubRegIndices() &&
64 "This is not a subregister index");
65 return SubRegIdxRanges[Idx].Offset;
68 int MCRegisterInfo::getDwarfRegNum(MCRegister RegNum, bool isEH) const {
69 const DwarfLLVMRegPair *M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
70 unsigned Size = isEH ? EHL2DwarfRegsSize : L2DwarfRegsSize;
72 if (!M)
73 return -1;
74 DwarfLLVMRegPair Key = { RegNum, 0 };
75 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
76 if (I == M+Size || I->FromReg != RegNum)
77 return -1;
78 return I->ToReg;
81 int MCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
82 const DwarfLLVMRegPair *M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
83 unsigned Size = isEH ? EHDwarf2LRegsSize : Dwarf2LRegsSize;
85 if (!M)
86 return -1;
87 DwarfLLVMRegPair Key = { RegNum, 0 };
88 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
89 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum");
90 return I->ToReg;
93 int MCRegisterInfo::getLLVMRegNumFromEH(unsigned RegNum) const {
94 const DwarfLLVMRegPair *M = EHDwarf2LRegs;
95 unsigned Size = EHDwarf2LRegsSize;
97 if (!M)
98 return -1;
99 DwarfLLVMRegPair Key = { RegNum, 0 };
100 const DwarfLLVMRegPair *I = std::lower_bound(M, M+Size, Key);
101 if (I == M+Size || I->FromReg != RegNum)
102 return -1;
103 return I->ToReg;
106 int MCRegisterInfo::getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const {
107 // On ELF platforms, DWARF EH register numbers are the same as DWARF
108 // other register numbers. On Darwin x86, they differ and so need to be
109 // mapped. The .cfi_* directives accept integer literals as well as
110 // register names and should generate exactly what the assembly code
111 // asked for, so there might be DWARF/EH register numbers that don't have
112 // a corresponding LLVM register number at all. So if we can't map the
113 // EH register number to an LLVM register number, assume it's just a
114 // valid DWARF register number as is.
115 int LRegNum = getLLVMRegNumFromEH(RegNum);
116 if (LRegNum != -1)
117 return getDwarfRegNum(LRegNum, false);
118 return RegNum;
121 int MCRegisterInfo::getSEHRegNum(MCRegister RegNum) const {
122 const DenseMap<MCRegister, int>::const_iterator I = L2SEHRegs.find(RegNum);
123 if (I == L2SEHRegs.end()) return (int)RegNum;
124 return I->second;
127 int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const {
128 if (L2CVRegs.empty())
129 report_fatal_error("target does not implement codeview register mapping");
130 const DenseMap<MCRegister, int>::const_iterator I = L2CVRegs.find(RegNum);
131 if (I == L2CVRegs.end())
132 report_fatal_error("unknown codeview register " + (RegNum < getNumRegs()
133 ? getName(RegNum)
134 : Twine(RegNum)));
135 return I->second;