[Alignment] Migrate Attribute::getWith(Stack)Alignment
[llvm-core.git] / unittests / tools / llvm-exegesis / X86 / SchedClassResolutionTest.cpp
blob879137223e5afd4cf6c537c6baaa3b79ccb31c42
1 //===-- SchedClassResolutionTest.cpp ----------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
9 #include "SchedClassResolution.h"
11 #include <cassert>
12 #include <memory>
14 #include "TestBase.h"
15 #include "llvm/Support/TargetRegistry.h"
16 #include "llvm/Support/TargetSelect.h"
17 #include "gmock/gmock.h"
18 #include "gtest/gtest.h"
20 namespace llvm {
21 namespace exegesis {
22 namespace {
24 using testing::Pair;
25 using testing::UnorderedElementsAre;
27 class SchedClassResolutionTest : public X86TestBase {
28 protected:
29 SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
30 // Compute the ProxResIdx of ports uses in tests.
31 const auto &SM = STI.getSchedModel();
32 for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
33 const std::string Name = SM.getProcResource(I)->Name;
34 if (Name == "HWPort0") {
35 P0Idx = I;
36 } else if (Name == "HWPort1") {
37 P1Idx = I;
38 } else if (Name == "HWPort5") {
39 P5Idx = I;
40 } else if (Name == "HWPort6") {
41 P6Idx = I;
42 } else if (Name == "HWPort05") {
43 P05Idx = I;
44 } else if (Name == "HWPort0156") {
45 P0156Idx = I;
48 EXPECT_NE(P0Idx, 0);
49 EXPECT_NE(P1Idx, 0);
50 EXPECT_NE(P5Idx, 0);
51 EXPECT_NE(P6Idx, 0);
52 EXPECT_NE(P05Idx, 0);
53 EXPECT_NE(P0156Idx, 0);
56 protected:
57 const MCSubtargetInfo &STI;
58 uint16_t P0Idx = 0;
59 uint16_t P1Idx = 0;
60 uint16_t P5Idx = 0;
61 uint16_t P6Idx = 0;
62 uint16_t P05Idx = 0;
63 uint16_t P0156Idx = 0;
66 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
67 const auto Pressure =
68 computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}});
69 EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));
72 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
73 const auto Pressure =
74 computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}});
75 EXPECT_THAT(Pressure,
76 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));
79 TEST_F(SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
80 const auto Pressure = computeIdealizedProcResPressure(
81 STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
82 EXPECT_THAT(Pressure,
83 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
84 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
87 TEST_F(SchedClassResolutionTest,
88 ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {
89 const auto Pressure = computeIdealizedProcResPressure(
90 STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
91 EXPECT_THAT(Pressure,
92 UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
93 Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
96 } // namespace
97 } // namespace exegesis
98 } // namespace llvm