include/llvm/CodeGen/MachineCombinerPattern.h

   1 //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
   2 // combiner  ------*- C++ -*-===//
   3 //
   4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   5 // See https://llvm.org/LICENSE.txt for license information.
   6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines instruction pattern supported by combiner
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
  15 #define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
  16
  17 namespace llvm {
  18
  19 /// These are instruction patterns matched by the machine combiner pass.
  20 enum class MachineCombinerPattern {
  21   // These are commutative variants for reassociating a computation chain. See
  22   // the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
  23   REASSOC_AX_BY,
  24   REASSOC_AX_YB,
  25   REASSOC_XA_BY,
  26   REASSOC_XA_YB,
  27
  28   // These are multiply-add patterns matched by the AArch64 machine combiner.
  29   MULADDW_OP1,
  30   MULADDW_OP2,
  31   MULSUBW_OP1,
  32   MULSUBW_OP2,
  33   MULADDWI_OP1,
  34   MULSUBWI_OP1,
  35   MULADDX_OP1,
  36   MULADDX_OP2,
  37   MULSUBX_OP1,
  38   MULSUBX_OP2,
  39   MULADDXI_OP1,
  40   MULSUBXI_OP1,
  41   // Floating Point
  42   FMULADDS_OP1,
  43   FMULADDS_OP2,
  44   FMULSUBS_OP1,
  45   FMULSUBS_OP2,
  46   FMULADDD_OP1,
  47   FMULADDD_OP2,
  48   FMULSUBD_OP1,
  49   FMULSUBD_OP2,
  50   FNMULSUBS_OP1,
  51   FNMULSUBD_OP1,
  52   FMLAv1i32_indexed_OP1,
  53   FMLAv1i32_indexed_OP2,
  54   FMLAv1i64_indexed_OP1,
  55   FMLAv1i64_indexed_OP2,
  56   FMLAv2f32_OP2,
  57   FMLAv2f32_OP1,
  58   FMLAv2f64_OP1,
  59   FMLAv2f64_OP2,
  60   FMLAv2i32_indexed_OP1,
  61   FMLAv2i32_indexed_OP2,
  62   FMLAv2i64_indexed_OP1,
  63   FMLAv2i64_indexed_OP2,
  64   FMLAv4f32_OP1,
  65   FMLAv4f32_OP2,
  66   FMLAv4i32_indexed_OP1,
  67   FMLAv4i32_indexed_OP2,
  68   FMLSv1i32_indexed_OP2,
  69   FMLSv1i64_indexed_OP2,
  70   FMLSv2f32_OP1,
  71   FMLSv2f32_OP2,
  72   FMLSv2f64_OP1,
  73   FMLSv2f64_OP2,
  74   FMLSv2i32_indexed_OP1,
  75   FMLSv2i32_indexed_OP2,
  76   FMLSv2i64_indexed_OP1,
  77   FMLSv2i64_indexed_OP2,
  78   FMLSv4f32_OP1,
  79   FMLSv4f32_OP2,
  80   FMLSv4i32_indexed_OP1,
  81   FMLSv4i32_indexed_OP2
  82 };
  83
  84 } // end namespace llvm
  85
  86 #endif