include/llvm/CodeGen/TargetSubtargetInfo.h

   1 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file describes the subtarget options of a Target machine.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
  14 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
  15
  16 #include "llvm/ADT/APInt.h"
  17 #include "llvm/ADT/ArrayRef.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/ADT/StringRef.h"
  20 #include "llvm/CodeGen/PBQPRAConstraint.h"
  21 #include "llvm/CodeGen/ScheduleDAGMutation.h"
  22 #include "llvm/CodeGen/SchedulerRegistry.h"
  23 #include "llvm/MC/MCSubtargetInfo.h"
  24 #include "llvm/Support/CodeGen.h"
  25 #include <memory>
  26 #include <vector>
  27
  28
  29 namespace llvm {
  30
  31 class CallLowering;
  32 class InstrItineraryData;
  33 struct InstrStage;
  34 class InstructionSelector;
  35 class LegalizerInfo;
  36 class MachineInstr;
  37 struct MachineSchedPolicy;
  38 struct MCReadAdvanceEntry;
  39 struct MCWriteLatencyEntry;
  40 struct MCWriteProcResEntry;
  41 class RegisterBankInfo;
  42 class SDep;
  43 class SelectionDAGTargetInfo;
  44 struct SubtargetFeatureKV;
  45 struct SubtargetSubTypeKV;
  46 struct SubtargetInfoKV;
  47 class SUnit;
  48 class TargetFrameLowering;
  49 class TargetInstrInfo;
  50 class TargetLowering;
  51 class TargetRegisterClass;
  52 class TargetRegisterInfo;
  53 class TargetSchedModel;
  54 class Triple;
  55
  56 //===----------------------------------------------------------------------===//
  57 ///
  58 /// TargetSubtargetInfo - Generic base class for all target subtargets.  All
  59 /// Target-specific options that control code generation and printing should
  60 /// be exposed through a TargetSubtargetInfo-derived class.
  61 ///
  62 class TargetSubtargetInfo : public MCSubtargetInfo {
  63 protected: // Can only create subclasses...
  64   TargetSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS,
  65                       ArrayRef<SubtargetFeatureKV> PF,
  66                       ArrayRef<SubtargetSubTypeKV> PD,
  67                       const MCWriteProcResEntry *WPR,
  68                       const MCWriteLatencyEntry *WL,
  69                       const MCReadAdvanceEntry *RA, const InstrStage *IS,
  70                       const unsigned *OC, const unsigned *FP);
  71
  72 public:
  73   // AntiDepBreakMode - Type of anti-dependence breaking that should
  74   // be performed before post-RA scheduling.
  75   using AntiDepBreakMode = enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL };
  76   using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
  77
  78   TargetSubtargetInfo() = delete;
  79   TargetSubtargetInfo(const TargetSubtargetInfo &) = delete;
  80   TargetSubtargetInfo &operator=(const TargetSubtargetInfo &) = delete;
  81   ~TargetSubtargetInfo() override;
  82
  83   virtual bool isXRaySupported() const { return false; }
  84
  85   // Interfaces to the major aspects of target machine information:
  86   //
  87   // -- Instruction opcode and operand information
  88   // -- Pipelines and scheduling information
  89   // -- Stack frame information
  90   // -- Selection DAG lowering information
  91   // -- Call lowering information
  92   //
  93   // N.B. These objects may change during compilation. It's not safe to cache
  94   // them between functions.
  95   virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
  96   virtual const TargetFrameLowering *getFrameLowering() const {
  97     return nullptr;
  98   }
  99   virtual const TargetLowering *getTargetLowering() const { return nullptr; }
 100   virtual const SelectionDAGTargetInfo *getSelectionDAGInfo() const {
 101     return nullptr;
 102   }
 103   virtual const CallLowering *getCallLowering() const { return nullptr; }
 104
 105   // FIXME: This lets targets specialize the selector by subtarget (which lets
 106   // us do things like a dedicated avx512 selector).  However, we might want
 107   // to also specialize selectors by MachineFunction, which would let us be
 108   // aware of optsize/optnone and such.
 109   virtual InstructionSelector *getInstructionSelector() const {
 110     return nullptr;
 111   }
 112
 113   virtual unsigned getHwMode() const { return 0; }
 114
 115   /// Target can subclass this hook to select a different DAG scheduler.
 116   virtual RegisterScheduler::FunctionPassCtor
 117       getDAGScheduler(CodeGenOpt::Level) const {
 118     return nullptr;
 119   }
 120
 121   virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
 122
 123   /// getRegisterInfo - If register information is available, return it.  If
 124   /// not, return null.
 125   virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
 126
 127   /// If the information for the register banks is available, return it.
 128   /// Otherwise return nullptr.
 129   virtual const RegisterBankInfo *getRegBankInfo() const { return nullptr; }
 130
 131   /// getInstrItineraryData - Returns instruction itinerary data for the target
 132   /// or specific subtarget.
 133   virtual const InstrItineraryData *getInstrItineraryData() const {
 134     return nullptr;
 135   }
 136
 137   /// Resolve a SchedClass at runtime, where SchedClass identifies an
 138   /// MCSchedClassDesc with the isVariant property. This may return the ID of
 139   /// another variant SchedClass, but repeated invocation must quickly terminate
 140   /// in a nonvariant SchedClass.
 141   virtual unsigned resolveSchedClass(unsigned SchedClass,
 142                                      const MachineInstr *MI,
 143                                      const TargetSchedModel *SchedModel) const {
 144     return 0;
 145   }
 146
 147   /// Returns true if MI is a dependency breaking zero-idiom instruction for the
 148   /// subtarget.
 149   ///
 150   /// This function also sets bits in Mask related to input operands that
 151   /// are not in a data dependency relationship.  There is one bit for each
 152   /// machine operand; implicit operands follow explicit operands in the bit
 153   /// representation used for Mask.  An empty (i.e. a mask with all bits
 154   /// cleared) means: data dependencies are "broken" for all the explicit input
 155   /// machine operands of MI.
 156   virtual bool isZeroIdiom(const MachineInstr *MI, APInt &Mask) const {
 157     return false;
 158   }
 159
 160   /// Returns true if MI is a dependency breaking instruction for the subtarget.
 161   ///
 162   /// Similar in behavior to `isZeroIdiom`. However, it knows how to identify
 163   /// all dependency breaking instructions (i.e. not just zero-idioms).
 164   ///
 165   /// As for `isZeroIdiom`, this method returns a mask of "broken" dependencies.
 166   /// (See method `isZeroIdiom` for a detailed description of Mask).
 167   virtual bool isDependencyBreaking(const MachineInstr *MI, APInt &Mask) const {
 168     return isZeroIdiom(MI, Mask);
 169   }
 170
 171   /// Returns true if MI is a candidate for move elimination.
 172   ///
 173   /// A candidate for move elimination may be optimized out at register renaming
 174   /// stage. Subtargets can specify the set of optimizable moves by
 175   /// instantiating tablegen class `IsOptimizableRegisterMove` (see
 176   /// llvm/Target/TargetInstrPredicate.td).
 177   ///
 178   /// SubtargetEmitter is responsible for processing all the definitions of class
 179   /// IsOptimizableRegisterMove, and auto-generate an override for this method.
 180   virtual bool isOptimizableRegisterMove(const MachineInstr *MI) const {
 181     return false;
 182   }
 183
 184   /// True if the subtarget should run MachineScheduler after aggressive
 185   /// coalescing.
 186   ///
 187   /// This currently replaces the SelectionDAG scheduler with the "source" order
 188   /// scheduler (though see below for an option to turn this off and use the
 189   /// TargetLowering preference). It does not yet disable the postRA scheduler.
 190   virtual bool enableMachineScheduler() const;
 191
 192   /// True if the machine scheduler should disable the TLI preference
 193   /// for preRA scheduling with the source level scheduler.
 194   virtual bool enableMachineSchedDefaultSched() const { return true; }
 195
 196   /// True if the subtarget should run MachinePipeliner
 197   virtual bool enableMachinePipeliner() const { return true; };
 198
 199   /// True if the subtarget should enable joining global copies.
 200   ///
 201   /// By default this is enabled if the machine scheduler is enabled, but
 202   /// can be overridden.
 203   virtual bool enableJoinGlobalCopies() const;
 204
 205   /// True if the subtarget should run a scheduler after register allocation.
 206   ///
 207   /// By default this queries the PostRAScheduling bit in the scheduling model
 208   /// which is the preferred way to influence this.
 209   virtual bool enablePostRAScheduler() const;
 210
 211   /// True if the subtarget should run the atomic expansion pass.
 212   virtual bool enableAtomicExpand() const;
 213
 214   /// True if the subtarget should run the indirectbr expansion pass.
 215   virtual bool enableIndirectBrExpand() const;
 216
 217   /// Override generic scheduling policy within a region.
 218   ///
 219   /// This is a convenient way for targets that don't provide any custom
 220   /// scheduling heuristics (no custom MachineSchedStrategy) to make
 221   /// changes to the generic scheduling policy.
 222   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
 223                                    unsigned NumRegionInstrs) const {}
 224
 225   // Perform target specific adjustments to the latency of a schedule
 226   // dependency.
 227   virtual void adjustSchedDependency(SUnit *def, SUnit *use, SDep &dep) const {}
 228
 229   // For use with PostRAScheduling: get the anti-dependence breaking that should
 230   // be performed before post-RA scheduling.
 231   virtual AntiDepBreakMode getAntiDepBreakMode() const { return ANTIDEP_NONE; }
 232
 233   // For use with PostRAScheduling: in CriticalPathRCs, return any register
 234   // classes that should only be considered for anti-dependence breaking if they
 235   // are on the critical path.
 236   virtual void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
 237     return CriticalPathRCs.clear();
 238   }
 239
 240   // Provide an ordered list of schedule DAG mutations for the post-RA
 241   // scheduler.
 242   virtual void getPostRAMutations(
 243       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
 244   }
 245
 246   // Provide an ordered list of schedule DAG mutations for the machine
 247   // pipeliner.
 248   virtual void getSMSMutations(
 249       std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const {
 250   }
 251
 252   /// Default to DFA for resource management, return false when target will use
 253   /// ProcResource in InstrSchedModel instead.
 254   virtual bool useDFAforSMS() const { return true; }
 255
 256   // For use with PostRAScheduling: get the minimum optimization level needed
 257   // to enable post-RA scheduling.
 258   virtual CodeGenOpt::Level getOptLevelToEnablePostRAScheduler() const {
 259     return CodeGenOpt::Default;
 260   }
 261
 262   /// True if the subtarget should run the local reassignment
 263   /// heuristic of the register allocator.
 264   /// This heuristic may be compile time intensive, \p OptLevel provides
 265   /// a finer grain to tune the register allocator.
 266   virtual bool enableRALocalReassignment(CodeGenOpt::Level OptLevel) const;
 267
 268   /// True if the subtarget should consider the cost of local intervals
 269   /// created by a split candidate when choosing the best split candidate. This
 270   /// heuristic may be compile time intensive.
 271   virtual bool enableAdvancedRASplitCost() const;
 272
 273   /// Enable use of alias analysis during code generation (during MI
 274   /// scheduling, DAGCombine, etc.).
 275   virtual bool useAA() const;
 276
 277   /// Enable the use of the early if conversion pass.
 278   virtual bool enableEarlyIfConversion() const { return false; }
 279
 280   /// Return PBQPConstraint(s) for the target.
 281   ///
 282   /// Override to provide custom PBQP constraints.
 283   virtual std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const {
 284     return nullptr;
 285   }
 286
 287   /// Enable tracking of subregister liveness in register allocator.
 288   /// Please use MachineRegisterInfo::subRegLivenessEnabled() instead where
 289   /// possible.
 290   virtual bool enableSubRegLiveness() const { return false; }
 291
 292   /// This is called after a .mir file was loaded.
 293   virtual void mirFileLoaded(MachineFunction &MF) const;
 294
 295   /// True if the register allocator should use the allocation orders exactly as
 296   /// written in the tablegen descriptions, false if it should allocate
 297   /// the specified physical register later if is it callee-saved.
 298   virtual bool ignoreCSRForAllocationOrder(const MachineFunction &MF,
 299                                            unsigned PhysReg) const {
 300     return false;
 301   }
 302 };
 303
 304 } // end namespace llvm
 305
 306 #endif // LLVM_CODEGEN_TARGETSUBTARGETINFO_H