lib/Target/AArch64/AArch64.td

   1 //=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 //
  10 //===----------------------------------------------------------------------===//
  11
  12 //===----------------------------------------------------------------------===//
  13 // Target-independent interfaces which we are implementing.
  14 //===----------------------------------------------------------------------===//
  15
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // AArch64 Subtarget features.
  20 //
  21
  22 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
  23                                        "Enable ARMv8 FP">;
  24
  25 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  26   "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
  27
  28 def FeatureSM4 : SubtargetFeature<
  29     "sm4", "HasSM4", "true",
  30     "Enable SM3 and SM4 support", [FeatureNEON]>;
  31
  32 def FeatureSHA2 : SubtargetFeature<
  33     "sha2", "HasSHA2", "true",
  34     "Enable SHA1 and SHA256 support", [FeatureNEON]>;
  35
  36 def FeatureSHA3 : SubtargetFeature<
  37     "sha3", "HasSHA3", "true",
  38     "Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
  39
  40 def FeatureAES : SubtargetFeature<
  41     "aes", "HasAES", "true",
  42     "Enable AES support", [FeatureNEON]>;
  43
  44 // Crypto has been split up and any combination is now valid (see the
  45 // crypto defintions above). Also, crypto is now context sensitive:
  46 // it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
  47 // Therefore, we rely on Clang, the user interacing tool, to pass on the
  48 // appropriate crypto options. But here in the backend, crypto has very little
  49 // meaning anymore. We kept the Crypto defintion here for backward
  50 // compatibility, and now imply features SHA2 and AES, which was the
  51 // "traditional" meaning of Crypto.
  52 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  53   "Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
  54
  55 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  56   "Enable ARMv8 CRC-32 checksum instructions">;
  57
  58 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
  59   "Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
  60
  61 def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
  62   "Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
  63
  64 def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
  65   "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
  66
  67 def FeaturePAN : SubtargetFeature<
  68     "pan", "HasPAN", "true",
  69     "Enables ARM v8.1 Privileged Access-Never extension">;
  70
  71 def FeatureLOR : SubtargetFeature<
  72     "lor", "HasLOR", "true",
  73     "Enables ARM v8.1 Limited Ordering Regions extension">;
  74
  75 def FeatureVH : SubtargetFeature<
  76     "vh", "HasVH", "true",
  77     "Enables ARM v8.1 Virtual Host extension">;
  78
  79 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  80   "Enable ARMv8 PMUv3 Performance Monitors extension">;
  81
  82 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  83   "Full FP16", [FeatureFPARMv8]>;
  84
  85 def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
  86   "Enable FP16 FML instructions", [FeatureFullFP16]>;
  87
  88 def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
  89   "Enable Statistical Profiling extension">;
  90
  91 def FeaturePAN_RWV : SubtargetFeature<
  92     "pan-rwv", "HasPAN_RWV", "true",
  93     "Enable v8.2 PAN s1e1R and s1e1W Variants",
  94     [FeaturePAN]>;
  95
  96 // UAO PState
  97 def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
  98     "Enable v8.2 UAO PState">;
  99
 100 def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
 101     "true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
 102
 103 def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
 104   "Enable Scalable Vector Extension (SVE) instructions">;
 105
 106 def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
 107   "Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
 108
 109 def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
 110   "Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
 111
 112 def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
 113   "Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
 114
 115 def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
 116   "Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
 117
 118 def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
 119   "Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
 120
 121 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
 122                                         "Has zero-cycle register moves">;
 123 def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
 124                                         "Has zero-cycle zeroing instructions for generic registers">;
 125
 126 def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
 127                                         "Has zero-cycle zeroing instructions for FP registers">;
 128
 129 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 130                                         "Has zero-cycle zeroing instructions",
 131                                         [FeatureZCZeroingGP, FeatureZCZeroingFP]>;
 132
 133 /// ... but the floating-point version doesn't quite work in rare cases on older
 134 /// CPUs.
 135 def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
 136     "HasZeroCycleZeroingFPWorkaround", "true",
 137     "The zero-cycle floating-point zeroing instruction has a bug">;
 138
 139 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 140                                           "StrictAlign", "true",
 141                                           "Disallow all unaligned memory "
 142                                           "access">;
 143
 144 foreach i = {1-7,9-15,18,20-28} in
 145     def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
 146                                              "Reserve X"#i#", making it unavailable "
 147                                              "as a GPR">;
 148
 149 foreach i = {8-15,18} in
 150     def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
 151          "CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
 152
 153 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 154                                     "Use alias analysis during codegen">;
 155
 156 def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
 157     "true",
 158     "balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
 159
 160 def FeaturePredictableSelectIsExpensive : SubtargetFeature<
 161     "predictable-select-expensive", "PredictableSelectIsExpensive", "true",
 162     "Prefer likely predicted branches over selects">;
 163
 164 def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
 165     "CustomAsCheapAsMove", "true",
 166     "Use custom handling of cheap instructions">;
 167
 168 def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
 169     "ExynosAsCheapAsMove", "true",
 170     "Use Exynos specific handling of cheap instructions",
 171     [FeatureCustomCheapAsMoveHandling]>;
 172
 173 def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
 174     "UsePostRAScheduler", "true", "Schedule again after register allocation">;
 175
 176 def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
 177     "Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
 178
 179 def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
 180     "Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
 181
 182 def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
 183     "true", "STR of Q register with register offset is slow">;
 184
 185 def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
 186     "alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
 187     "true", "Use alternative pattern for sextload convert to f32">;
 188
 189 def FeatureArithmeticBccFusion : SubtargetFeature<
 190     "arith-bcc-fusion", "HasArithmeticBccFusion", "true",
 191     "CPU fuses arithmetic+bcc operations">;
 192
 193 def FeatureArithmeticCbzFusion : SubtargetFeature<
 194     "arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
 195     "CPU fuses arithmetic + cbz/cbnz operations">;
 196
 197 def FeatureFuseAddress : SubtargetFeature<
 198     "fuse-address", "HasFuseAddress", "true",
 199     "CPU fuses address generation and memory operations">;
 200
 201 def FeatureFuseAES : SubtargetFeature<
 202     "fuse-aes", "HasFuseAES", "true",
 203     "CPU fuses AES crypto operations">;
 204
 205 def FeatureFuseArithmeticLogic : SubtargetFeature<
 206     "fuse-arith-logic", "HasFuseArithmeticLogic", "true",
 207     "CPU fuses arithmetic and logic operations">;
 208
 209 def FeatureFuseCCSelect : SubtargetFeature<
 210     "fuse-csel", "HasFuseCCSelect", "true",
 211     "CPU fuses conditional select operations">;
 212
 213 def FeatureFuseCryptoEOR : SubtargetFeature<
 214     "fuse-crypto-eor", "HasFuseCryptoEOR", "true",
 215     "CPU fuses AES/PMULL and EOR operations">;
 216
 217 def FeatureFuseLiterals : SubtargetFeature<
 218     "fuse-literals", "HasFuseLiterals", "true",
 219     "CPU fuses literal generation operations">;
 220
 221 def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
 222     "disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
 223     "Disable latency scheduling heuristic">;
 224
 225 def FeatureForce32BitJumpTables
 226    : SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
 227                       "Force jump table entries to be 32-bits wide except at MinSize">;
 228
 229 def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
 230                                    "Enable support for RCPC extension">;
 231
 232 def FeatureUseRSqrt : SubtargetFeature<
 233     "use-reciprocal-square-root", "UseRSqrt", "true",
 234     "Use the reciprocal square root approximation">;
 235
 236 def FeatureDotProd : SubtargetFeature<
 237     "dotprod", "HasDotProd", "true",
 238     "Enable dot product support">;
 239
 240 def FeaturePA : SubtargetFeature<
 241     "pa", "HasPA", "true",
 242     "Enable v8.3-A Pointer Authentication enchancement">;
 243
 244 def FeatureJS : SubtargetFeature<
 245     "jsconv", "HasJS", "true",
 246     "Enable v8.3-A JavaScript FP conversion enchancement",
 247     [FeatureFPARMv8]>;
 248
 249 def FeatureCCIDX : SubtargetFeature<
 250     "ccidx", "HasCCIDX", "true",
 251     "Enable v8.3-A Extend of the CCSIDR number of sets">;
 252
 253 def FeatureComplxNum : SubtargetFeature<
 254     "complxnum", "HasComplxNum", "true",
 255     "Enable v8.3-A Floating-point complex number support",
 256     [FeatureNEON]>;
 257
 258 def FeatureNV : SubtargetFeature<
 259     "nv", "HasNV", "true",
 260     "Enable v8.4-A Nested Virtualization Enchancement">;
 261
 262 def FeatureRASv8_4 : SubtargetFeature<
 263     "rasv8_4", "HasRASv8_4", "true",
 264     "Enable v8.4-A Reliability, Availability and Serviceability extension",
 265     [FeatureRAS]>;
 266
 267 def FeatureMPAM : SubtargetFeature<
 268     "mpam", "HasMPAM", "true",
 269     "Enable v8.4-A Memory system Partitioning and Monitoring extension">;
 270
 271 def FeatureDIT : SubtargetFeature<
 272     "dit", "HasDIT", "true",
 273     "Enable v8.4-A Data Independent Timing instructions">;
 274
 275 def FeatureTRACEV8_4 : SubtargetFeature<
 276     "tracev8.4", "HasTRACEV8_4", "true",
 277     "Enable v8.4-A Trace extension">;
 278
 279 def FeatureAM : SubtargetFeature<
 280     "am", "HasAM", "true",
 281     "Enable v8.4-A Activity Monitors extension">;
 282
 283 def FeatureSEL2 : SubtargetFeature<
 284     "sel2", "HasSEL2", "true",
 285     "Enable v8.4-A Secure Exception Level 2 extension">;
 286
 287 def FeatureTLB_RMI : SubtargetFeature<
 288     "tlb-rmi", "HasTLB_RMI", "true",
 289     "Enable v8.4-A TLB Range and Maintenance Instructions">;
 290
 291 def FeatureFMI : SubtargetFeature<
 292     "fmi", "HasFMI", "true",
 293     "Enable v8.4-A Flag Manipulation Instructions">;
 294
 295 // 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
 296 def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
 297     "Enable v8.4-A RCPC instructions with Immediate Offsets",
 298     [FeatureRCPC]>;
 299
 300 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 301                                         "NegativeImmediates", "false",
 302                                         "Convert immediates and instructions "
 303                                         "to their negated or complemented "
 304                                         "equivalent when the immediate does "
 305                                         "not fit in the encoding.">;
 306
 307 def FeatureLSLFast : SubtargetFeature<
 308     "lsl-fast", "HasLSLFast", "true",
 309     "CPU has a fastpath logical shift of up to 3 places">;
 310
 311 def FeatureAggressiveFMA :
 312   SubtargetFeature<"aggressive-fma",
 313                    "HasAggressiveFMA",
 314                    "true",
 315                    "Enable Aggressive FMA for floating-point.">;
 316
 317 def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
 318   "Enable alternative NZCV format for floating point comparisons">;
 319
 320 def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
 321   "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
 322   "an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
 323
 324 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
 325   "true", "Enable architectural speculation restriction" >;
 326
 327 def FeatureSB : SubtargetFeature<"sb", "HasSB",
 328   "true", "Enable v8.5 Speculation Barrier" >;
 329
 330 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
 331   "true", "Enable Speculative Store Bypass Safe bit" >;
 332
 333 def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
 334   "Enable v8.5a execution and data prediction invalidation instructions" >;
 335
 336 def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
 337     "true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
 338
 339 def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
 340     "true", "Enable Branch Target Identification" >;
 341
 342 def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
 343     "true", "Enable Random Number generation instructions" >;
 344
 345 def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
 346     "true", "Enable Memory Tagging Extension" >;
 347
 348 def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
 349     "true", "Enable Trace Buffer Extension">;
 350
 351 def FeatureETE : SubtargetFeature<"ete", "HasETE",
 352     "true", "Enable Embedded Trace Extension",
 353     [FeatureTRBE]>;
 354
 355 def FeatureTME : SubtargetFeature<"tme", "HasTME",
 356     "true", "Enable Transactional Memory Extension" >;
 357
 358 def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
 359     "AllowTaggedGlobals",
 360     "true", "Use an instruction sequence for taking the address of a global "
 361     "that allows a memory tag in the upper address bits">;
 362
 363 //===----------------------------------------------------------------------===//
 364 // Architectures.
 365 //
 366
 367 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 368   "Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
 369   FeaturePAN, FeatureLOR, FeatureVH]>;
 370
 371 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 372   "Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
 373   FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
 374
 375 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 376   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePA,
 377   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 378
 379 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 380   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
 381   FeatureNV, FeatureRASv8_4, FeatureMPAM, FeatureDIT,
 382   FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
 383   FeatureFMI, FeatureRCPC_IMMO]>;
 384
 385 def HasV8_5aOps : SubtargetFeature<
 386   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
 387   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
 388    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
 389    FeatureBranchTargetId]
 390 >;
 391
 392 //===----------------------------------------------------------------------===//
 393 // Register File Description
 394 //===----------------------------------------------------------------------===//
 395
 396 include "AArch64RegisterInfo.td"
 397 include "AArch64RegisterBanks.td"
 398 include "AArch64CallingConvention.td"
 399
 400 //===----------------------------------------------------------------------===//
 401 // Instruction Descriptions
 402 //===----------------------------------------------------------------------===//
 403
 404 include "AArch64Schedule.td"
 405 include "AArch64InstrInfo.td"
 406 include "AArch64SchedPredicates.td"
 407 include "AArch64SchedPredExynos.td"
 408
 409 def AArch64InstrInfo : InstrInfo;
 410
 411 //===----------------------------------------------------------------------===//
 412 // Named operands for MRS/MSR/TLBI/...
 413 //===----------------------------------------------------------------------===//
 414
 415 include "AArch64SystemOperands.td"
 416
 417 //===----------------------------------------------------------------------===//
 418 // Access to privileged registers
 419 //===----------------------------------------------------------------------===//
 420
 421 foreach i = 1-3 in
 422 def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
 423   "true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
 424
 425 //===----------------------------------------------------------------------===//
 426 // AArch64 Processors supported.
 427 //
 428
 429 //===----------------------------------------------------------------------===//
 430 // Unsupported features to disable for scheduling models
 431 //===----------------------------------------------------------------------===//
 432
 433 class AArch64Unsupported { list<Predicate> F; }
 434
 435 def SVEUnsupported : AArch64Unsupported {
 436   let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
 437            HasSVE2BitPerm];
 438 }
 439
 440 include "AArch64SchedA53.td"
 441 include "AArch64SchedA57.td"
 442 include "AArch64SchedCyclone.td"
 443 include "AArch64SchedFalkor.td"
 444 include "AArch64SchedKryo.td"
 445 include "AArch64SchedExynosM1.td"
 446 include "AArch64SchedExynosM3.td"
 447 include "AArch64SchedExynosM4.td"
 448 include "AArch64SchedThunderX.td"
 449 include "AArch64SchedThunderX2T99.td"
 450
 451 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 452                                    "Cortex-A35 ARM processors", [
 453                                    FeatureCRC,
 454                                    FeatureCrypto,
 455                                    FeatureFPARMv8,
 456                                    FeatureNEON,
 457                                    FeaturePerfMon
 458                                    ]>;
 459
 460 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 461                                    "Cortex-A53 ARM processors", [
 462                                    FeatureBalanceFPOps,
 463                                    FeatureCRC,
 464                                    FeatureCrypto,
 465                                    FeatureCustomCheapAsMoveHandling,
 466                                    FeatureFPARMv8,
 467                                    FeatureFuseAES,
 468                                    FeatureNEON,
 469                                    FeaturePerfMon,
 470                                    FeaturePostRAScheduler,
 471                                    FeatureUseAA
 472                                    ]>;
 473
 474 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 475                                    "Cortex-A55 ARM processors", [
 476                                    HasV8_2aOps,
 477                                    FeatureCrypto,
 478                                    FeatureFPARMv8,
 479                                    FeatureFuseAES,
 480                                    FeatureNEON,
 481                                    FeatureFullFP16,
 482                                    FeatureDotProd,
 483                                    FeatureRCPC,
 484                                    FeaturePerfMon
 485                                    ]>;
 486
 487 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 488                                    "Cortex-A57 ARM processors", [
 489                                    FeatureBalanceFPOps,
 490                                    FeatureCRC,
 491                                    FeatureCrypto,
 492                                    FeatureCustomCheapAsMoveHandling,
 493                                    FeatureFPARMv8,
 494                                    FeatureFuseAES,
 495                                    FeatureFuseLiterals,
 496                                    FeatureNEON,
 497                                    FeaturePerfMon,
 498                                    FeaturePostRAScheduler,
 499                                    FeaturePredictableSelectIsExpensive
 500                                    ]>;
 501
 502 def ProcA65     : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
 503                                    "Cortex-A65 ARM processors", [
 504                                    HasV8_2aOps,
 505                                    FeatureCrypto,
 506                                    FeatureDotProd,
 507                                    FeatureFPARMv8,
 508                                    FeatureFullFP16,
 509                                    FeatureNEON,
 510                                    FeatureRAS,
 511                                    FeatureRCPC,
 512                                    FeatureSSBS,
 513                                    ]>;
 514
 515 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 516                                    "Cortex-A72 ARM processors", [
 517                                    FeatureCRC,
 518                                    FeatureCrypto,
 519                                    FeatureFPARMv8,
 520                                    FeatureFuseAES,
 521                                    FeatureNEON,
 522                                    FeaturePerfMon
 523                                    ]>;
 524
 525 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 526                                    "Cortex-A73 ARM processors", [
 527                                    FeatureCRC,
 528                                    FeatureCrypto,
 529                                    FeatureFPARMv8,
 530                                    FeatureFuseAES,
 531                                    FeatureNEON,
 532                                    FeaturePerfMon
 533                                    ]>;
 534
 535 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 536                                    "Cortex-A75 ARM processors", [
 537                                    HasV8_2aOps,
 538                                    FeatureCrypto,
 539                                    FeatureFPARMv8,
 540                                    FeatureFuseAES,
 541                                    FeatureNEON,
 542                                    FeatureFullFP16,
 543                                    FeatureDotProd,
 544                                    FeatureRCPC,
 545                                    FeaturePerfMon
 546                                    ]>;
 547
 548 def ProcA76     : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
 549                                    "Cortex-A76 ARM processors", [
 550                                     HasV8_2aOps,
 551                                     FeatureFPARMv8,
 552                                     FeatureNEON,
 553                                     FeatureRCPC,
 554                                     FeatureCrypto,
 555                                     FeatureFullFP16,
 556                                     FeatureDotProd,
 557                                     FeatureSSBS
 558                                     ]>;
 559
 560 // Note that cyclone does not fuse AES instructions, but newer apple chips do
 561 // perform the fusion and cyclone is used by default when targetting apple OSes.
 562 def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
 563                                    "Cyclone", [
 564                                    FeatureAlternateSExtLoadCVTF32Pattern,
 565                                    FeatureArithmeticBccFusion,
 566                                    FeatureArithmeticCbzFusion,
 567                                    FeatureCrypto,
 568                                    FeatureDisableLatencySchedHeuristic,
 569                                    FeatureFPARMv8,
 570                                    FeatureFuseAES,
 571                                    FeatureFuseCryptoEOR,
 572                                    FeatureNEON,
 573                                    FeaturePerfMon,
 574                                    FeatureZCRegMove,
 575                                    FeatureZCZeroing,
 576                                    FeatureZCZeroingFPWorkaround
 577                                    ]>;
 578
 579 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 580                                     "Samsung Exynos-M1 processors",
 581                                     [FeatureSlowPaired128,
 582                                      FeatureCRC,
 583                                      FeatureCrypto,
 584                                      FeatureExynosCheapAsMoveHandling,
 585                                      FeatureForce32BitJumpTables,
 586                                      FeatureFuseAES,
 587                                      FeaturePerfMon,
 588                                      FeaturePostRAScheduler,
 589                                      FeatureSlowMisaligned128Store,
 590                                      FeatureUseRSqrt,
 591                                      FeatureZCZeroingFP]>;
 592
 593 def ProcExynosM2 : SubtargetFeature<"exynosm2", "ARMProcFamily", "ExynosM1",
 594                                     "Samsung Exynos-M2 processors",
 595                                     [FeatureSlowPaired128,
 596                                      FeatureCRC,
 597                                      FeatureCrypto,
 598                                      FeatureExynosCheapAsMoveHandling,
 599                                      FeatureForce32BitJumpTables,
 600                                      FeatureFuseAES,
 601                                      FeaturePerfMon,
 602                                      FeaturePostRAScheduler,
 603                                      FeatureSlowMisaligned128Store,
 604                                      FeatureZCZeroingFP]>;
 605
 606 def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
 607                                     "Samsung Exynos-M3 processors",
 608                                     [FeatureCRC,
 609                                      FeatureCrypto,
 610                                      FeatureExynosCheapAsMoveHandling,
 611                                      FeatureForce32BitJumpTables,
 612                                      FeatureFuseAddress,
 613                                      FeatureFuseAES,
 614                                      FeatureFuseCCSelect,
 615                                      FeatureFuseLiterals,
 616                                      FeatureLSLFast,
 617                                      FeaturePerfMon,
 618                                      FeaturePostRAScheduler,
 619                                      FeaturePredictableSelectIsExpensive,
 620                                      FeatureZCZeroingFP]>;
 621
 622 def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
 623                                     "Samsung Exynos-M4 processors",
 624                                     [HasV8_2aOps,
 625                                      FeatureArithmeticBccFusion,
 626                                      FeatureArithmeticCbzFusion,
 627                                      FeatureCrypto,
 628                                      FeatureDotProd,
 629                                      FeatureExynosCheapAsMoveHandling,
 630                                      FeatureForce32BitJumpTables,
 631                                      FeatureFullFP16,
 632                                      FeatureFuseAddress,
 633                                      FeatureFuseAES,
 634                                      FeatureFuseArithmeticLogic,
 635                                      FeatureFuseCCSelect,
 636                                      FeatureFuseLiterals,
 637                                      FeatureLSLFast,
 638                                      FeaturePerfMon,
 639                                      FeaturePostRAScheduler,
 640                                      FeatureZCZeroing]>;
 641
 642 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 643                                    "Qualcomm Kryo processors", [
 644                                    FeatureCRC,
 645                                    FeatureCrypto,
 646                                    FeatureCustomCheapAsMoveHandling,
 647                                    FeatureFPARMv8,
 648                                    FeatureNEON,
 649                                    FeaturePerfMon,
 650                                    FeaturePostRAScheduler,
 651                                    FeaturePredictableSelectIsExpensive,
 652                                    FeatureZCZeroing,
 653                                    FeatureLSLFast
 654                                    ]>;
 655
 656 def ProcFalkor  : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
 657                                    "Qualcomm Falkor processors", [
 658                                    FeatureCRC,
 659                                    FeatureCrypto,
 660                                    FeatureCustomCheapAsMoveHandling,
 661                                    FeatureFPARMv8,
 662                                    FeatureNEON,
 663                                    FeaturePerfMon,
 664                                    FeaturePostRAScheduler,
 665                                    FeaturePredictableSelectIsExpensive,
 666                                    FeatureRDM,
 667                                    FeatureZCZeroing,
 668                                    FeatureLSLFast,
 669                                    FeatureSlowSTRQro
 670                                    ]>;
 671
 672 def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
 673                                       "NeoverseE1",
 674                                       "Neoverse E1 ARM processors", [
 675                                       HasV8_2aOps,
 676                                       FeatureCrypto,
 677                                       FeatureDotProd,
 678                                       FeatureFPARMv8,
 679                                       FeatureFullFP16,
 680                                       FeatureNEON,
 681                                       FeatureRCPC,
 682                                       FeatureSSBS,
 683                                       ]>;
 684
 685 def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
 686                                       "NeoverseN1",
 687                                       "Neoverse N1 ARM processors", [
 688                                       HasV8_2aOps,
 689                                       FeatureCrypto,
 690                                       FeatureDotProd,
 691                                       FeatureFPARMv8,
 692                                       FeatureFullFP16,
 693                                       FeatureNEON,
 694                                       FeatureRCPC,
 695                                       FeatureSPE,
 696                                       FeatureSSBS,
 697                                       ]>;
 698
 699 def ProcSaphira  : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
 700                                    "Qualcomm Saphira processors", [
 701                                    FeatureCrypto,
 702                                    FeatureCustomCheapAsMoveHandling,
 703                                    FeatureFPARMv8,
 704                                    FeatureNEON,
 705                                    FeatureSPE,
 706                                    FeaturePerfMon,
 707                                    FeaturePostRAScheduler,
 708                                    FeaturePredictableSelectIsExpensive,
 709                                    FeatureZCZeroing,
 710                                    FeatureLSLFast,
 711                                    HasV8_4aOps]>;
 712
 713 def ProcThunderX2T99  : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
 714                                          "ThunderX2T99",
 715                                          "Cavium ThunderX2 processors", [
 716                                           FeatureAggressiveFMA,
 717                                           FeatureCRC,
 718                                           FeatureCrypto,
 719                                           FeatureFPARMv8,
 720                                           FeatureArithmeticBccFusion,
 721                                           FeatureNEON,
 722                                           FeaturePostRAScheduler,
 723                                           FeaturePredictableSelectIsExpensive,
 724                                           FeatureLSE,
 725                                           HasV8_1aOps]>;
 726
 727 def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
 728                                     "Cavium ThunderX processors", [
 729                                     FeatureCRC,
 730                                     FeatureCrypto,
 731                                     FeatureFPARMv8,
 732                                     FeaturePerfMon,
 733                                     FeaturePostRAScheduler,
 734                                     FeaturePredictableSelectIsExpensive,
 735                                     FeatureNEON]>;
 736
 737 def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
 738                                        "ThunderXT88",
 739                                        "Cavium ThunderX processors", [
 740                                        FeatureCRC,
 741                                        FeatureCrypto,
 742                                        FeatureFPARMv8,
 743                                        FeaturePerfMon,
 744                                        FeaturePostRAScheduler,
 745                                        FeaturePredictableSelectIsExpensive,
 746                                        FeatureNEON]>;
 747
 748 def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
 749                                        "ThunderXT81",
 750                                        "Cavium ThunderX processors", [
 751                                        FeatureCRC,
 752                                        FeatureCrypto,
 753                                        FeatureFPARMv8,
 754                                        FeaturePerfMon,
 755                                        FeaturePostRAScheduler,
 756                                        FeaturePredictableSelectIsExpensive,
 757                                        FeatureNEON]>;
 758
 759 def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
 760                                        "ThunderXT83",
 761                                        "Cavium ThunderX processors", [
 762                                        FeatureCRC,
 763                                        FeatureCrypto,
 764                                        FeatureFPARMv8,
 765                                        FeaturePerfMon,
 766                                        FeaturePostRAScheduler,
 767                                        FeaturePredictableSelectIsExpensive,
 768                                        FeatureNEON]>;
 769
 770 def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
 771                                   "HiSilicon TS-V110 processors", [
 772                                   HasV8_2aOps,
 773                                   FeatureCrypto,
 774                                   FeatureCustomCheapAsMoveHandling,
 775                                   FeatureFPARMv8,
 776                                   FeatureFuseAES,
 777                                   FeatureNEON,
 778                                   FeaturePerfMon,
 779                                   FeaturePostRAScheduler,
 780                                   FeatureSPE,
 781                                   FeatureFullFP16,
 782                                   FeatureFP16FML,
 783                                   FeatureDotProd]>;
 784
 785 def : ProcessorModel<"generic", NoSchedModel, [
 786                      FeatureFPARMv8,
 787                      FeatureFuseAES,
 788                      FeatureNEON,
 789                      FeaturePerfMon,
 790                      FeaturePostRAScheduler,
 791 // ETE and TRBE are future architecture extensions. We temporariliy enable them
 792 // by default for users targeting generic AArch64, until it is decided in which
 793 // armv8.x-a architecture revision they will end up. The extensions do not
 794 // affect code generated by the compiler and can be used only by explicitly
 795 // mentioning the new system register names in assembly.
 796                      FeatureETE
 797                      ]>;
 798
 799 def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
 800 def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
 801 def : ProcessorModel<"cortex-a55", CortexA53Model, [ProcA55]>;
 802 def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
 803 def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
 804 def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
 805 def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
 806 def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
 807 def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
 808 def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
 809 def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
 810 def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
 811 def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
 812 def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
 813 def : ProcessorModel<"exynos-m1", ExynosM1Model, [ProcExynosM1]>;
 814 def : ProcessorModel<"exynos-m2", ExynosM1Model, [ProcExynosM2]>;
 815 def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
 816 def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
 817 def : ProcessorModel<"exynos-m5", ExynosM4Model, [ProcExynosM4]>;
 818 def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
 819 def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
 820 def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
 821 // Cavium ThunderX/ThunderX T8X  Processors
 822 def : ProcessorModel<"thunderx", ThunderXT8XModel,  [ProcThunderX]>;
 823 def : ProcessorModel<"thunderxt88", ThunderXT8XModel,  [ProcThunderXT88]>;
 824 def : ProcessorModel<"thunderxt81", ThunderXT8XModel,  [ProcThunderXT81]>;
 825 def : ProcessorModel<"thunderxt83", ThunderXT8XModel,  [ProcThunderXT83]>;
 826 // Cavium ThunderX2T9X  Processors. Formerly Broadcom Vulcan.
 827 def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
 828 // FIXME: HiSilicon TSV110 is currently modeled as a Cortex-A57.
 829 def : ProcessorModel<"tsv110", CortexA57Model, [ProcTSV110]>;
 830
 831 // Alias for the latest Apple processor model supported by LLVM.
 832 def : ProcessorModel<"apple-latest", CycloneModel, [ProcCyclone]>;
 833
 834 //===----------------------------------------------------------------------===//
 835 // Assembly parser
 836 //===----------------------------------------------------------------------===//
 837
 838 def GenericAsmParserVariant : AsmParserVariant {
 839   int Variant = 0;
 840   string Name = "generic";
 841   string BreakCharacters = ".";
 842   string TokenizingCharacters = "[]*!/";
 843 }
 844
 845 def AppleAsmParserVariant : AsmParserVariant {
 846   int Variant = 1;
 847   string Name = "apple-neon";
 848   string BreakCharacters = ".";
 849   string TokenizingCharacters = "[]*!/";
 850 }
 851
 852 //===----------------------------------------------------------------------===//
 853 // Assembly printer
 854 //===----------------------------------------------------------------------===//
 855 // AArch64 Uses the MC printer for asm output, so make sure the TableGen
 856 // AsmWriter bits get associated with the correct class.
 857 def GenericAsmWriter : AsmWriter {
 858   string AsmWriterClassName  = "InstPrinter";
 859   int PassSubtarget = 1;
 860   int Variant = 0;
 861   bit isMCAsmWriter = 1;
 862 }
 863
 864 def AppleAsmWriter : AsmWriter {
 865   let AsmWriterClassName = "AppleInstPrinter";
 866   int PassSubtarget = 1;
 867   int Variant = 1;
 868   int isMCAsmWriter = 1;
 869 }
 870
 871 //===----------------------------------------------------------------------===//
 872 // Target Declaration
 873 //===----------------------------------------------------------------------===//
 874
 875 def AArch64 : Target {
 876   let InstructionSet = AArch64InstrInfo;
 877   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
 878   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
 879   let AllowRegisterRenaming = 1;
 880 }
 881
 882 //===----------------------------------------------------------------------===//
 883 // Pfm Counters
 884 //===----------------------------------------------------------------------===//
 885
 886 include "AArch64PfmCounters.td"