lib/Target/AArch64/AArch64Subtarget.h

   1 //===--- AArch64Subtarget.h - Define Subtarget for the AArch64 -*- C++ -*--===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file declares the AArch64 specific subclass of TargetSubtarget.
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
  14 #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H
  15
  16 #include "AArch64FrameLowering.h"
  17 #include "AArch64ISelLowering.h"
  18 #include "AArch64InstrInfo.h"
  19 #include "AArch64RegisterInfo.h"
  20 #include "AArch64SelectionDAGInfo.h"
  21 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
  22 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
  23 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
  24 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  25 #include "llvm/CodeGen/TargetSubtargetInfo.h"
  26 #include "llvm/IR/DataLayout.h"
  27 #include <string>
  28
  29 #define GET_SUBTARGETINFO_HEADER
  30 #include "AArch64GenSubtargetInfo.inc"
  31
  32 namespace llvm {
  33 class GlobalValue;
  34 class StringRef;
  35 class Triple;
  36
  37 class AArch64Subtarget final : public AArch64GenSubtargetInfo {
  38 public:
  39   enum ARMProcFamilyEnum : uint8_t {
  40     Others,
  41     CortexA35,
  42     CortexA53,
  43     CortexA55,
  44     CortexA57,
  45     CortexA65,
  46     CortexA72,
  47     CortexA73,
  48     CortexA75,
  49     CortexA76,
  50     Cyclone,
  51     ExynosM1,
  52     ExynosM3,
  53     Falkor,
  54     Kryo,
  55     NeoverseE1,
  56     NeoverseN1,
  57     Saphira,
  58     ThunderX2T99,
  59     ThunderX,
  60     ThunderXT81,
  61     ThunderXT83,
  62     ThunderXT88,
  63     TSV110
  64   };
  65
  66 protected:
  67   /// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
  68   ARMProcFamilyEnum ARMProcFamily = Others;
  69
  70   bool HasV8_1aOps = false;
  71   bool HasV8_2aOps = false;
  72   bool HasV8_3aOps = false;
  73   bool HasV8_4aOps = false;
  74   bool HasV8_5aOps = false;
  75
  76   bool HasFPARMv8 = false;
  77   bool HasNEON = false;
  78   bool HasCrypto = false;
  79   bool HasDotProd = false;
  80   bool HasCRC = false;
  81   bool HasLSE = false;
  82   bool HasRAS = false;
  83   bool HasRDM = false;
  84   bool HasPerfMon = false;
  85   bool HasFullFP16 = false;
  86   bool HasFP16FML = false;
  87   bool HasSPE = false;
  88
  89   // ARMv8.1 extensions
  90   bool HasVH = false;
  91   bool HasPAN = false;
  92   bool HasLOR = false;
  93
  94   // ARMv8.2 extensions
  95   bool HasPsUAO = false;
  96   bool HasPAN_RWV = false;
  97   bool HasCCPP = false;
  98
  99   // Armv8.2 Crypto extensions
 100   bool HasSM4 = false;
 101   bool HasSHA3 = false;
 102   bool HasSHA2 = false;
 103   bool HasAES = false;
 104
 105   // ARMv8.3 extensions
 106   bool HasPA = false;
 107   bool HasJS = false;
 108   bool HasCCIDX = false;
 109   bool HasComplxNum = false;
 110
 111   // ARMv8.4 extensions
 112   bool HasNV = false;
 113   bool HasRASv8_4 = false;
 114   bool HasMPAM = false;
 115   bool HasDIT = false;
 116   bool HasTRACEV8_4 = false;
 117   bool HasAM = false;
 118   bool HasSEL2 = false;
 119   bool HasTLB_RMI = false;
 120   bool HasFMI = false;
 121   bool HasRCPC_IMMO = false;
 122
 123   bool HasLSLFast = false;
 124   bool HasSVE = false;
 125   bool HasSVE2 = false;
 126   bool HasRCPC = false;
 127   bool HasAggressiveFMA = false;
 128
 129   // Armv8.5-A Extensions
 130   bool HasAlternativeNZCV = false;
 131   bool HasFRInt3264 = false;
 132   bool HasSpecRestrict = false;
 133   bool HasSSBS = false;
 134   bool HasSB = false;
 135   bool HasPredRes = false;
 136   bool HasCCDP = false;
 137   bool HasBTI = false;
 138   bool HasRandGen = false;
 139   bool HasMTE = false;
 140   bool HasTME = false;
 141
 142   // Arm SVE2 extensions
 143   bool HasSVE2AES = false;
 144   bool HasSVE2SM4 = false;
 145   bool HasSVE2SHA3 = false;
 146   bool HasSVE2BitPerm = false;
 147
 148   // Future architecture extensions.
 149   bool HasETE = false;
 150   bool HasTRBE = false;
 151
 152   // HasZeroCycleRegMove - Has zero-cycle register mov instructions.
 153   bool HasZeroCycleRegMove = false;
 154
 155   // HasZeroCycleZeroing - Has zero-cycle zeroing instructions.
 156   bool HasZeroCycleZeroing = false;
 157   bool HasZeroCycleZeroingGP = false;
 158   bool HasZeroCycleZeroingFP = false;
 159   bool HasZeroCycleZeroingFPWorkaround = false;
 160
 161   // StrictAlign - Disallow unaligned memory accesses.
 162   bool StrictAlign = false;
 163
 164   // NegativeImmediates - transform instructions with negative immediates
 165   bool NegativeImmediates = true;
 166
 167   // Enable 64-bit vectorization in SLP.
 168   unsigned MinVectorRegisterBitWidth = 64;
 169
 170   bool UseAA = false;
 171   bool PredictableSelectIsExpensive = false;
 172   bool BalanceFPOps = false;
 173   bool CustomAsCheapAsMove = false;
 174   bool ExynosAsCheapAsMove = false;
 175   bool UsePostRAScheduler = false;
 176   bool Misaligned128StoreIsSlow = false;
 177   bool Paired128IsSlow = false;
 178   bool STRQroIsSlow = false;
 179   bool UseAlternateSExtLoadCVTF32Pattern = false;
 180   bool HasArithmeticBccFusion = false;
 181   bool HasArithmeticCbzFusion = false;
 182   bool HasFuseAddress = false;
 183   bool HasFuseAES = false;
 184   bool HasFuseArithmeticLogic = false;
 185   bool HasFuseCCSelect = false;
 186   bool HasFuseCryptoEOR = false;
 187   bool HasFuseLiterals = false;
 188   bool DisableLatencySchedHeuristic = false;
 189   bool UseRSqrt = false;
 190   bool Force32BitJumpTables = false;
 191   bool UseEL1ForTP = false;
 192   bool UseEL2ForTP = false;
 193   bool UseEL3ForTP = false;
 194   bool AllowTaggedGlobals = false;
 195   uint8_t MaxInterleaveFactor = 2;
 196   uint8_t VectorInsertExtractBaseCost = 3;
 197   uint16_t CacheLineSize = 0;
 198   uint16_t PrefetchDistance = 0;
 199   uint16_t MinPrefetchStride = 1;
 200   unsigned MaxPrefetchIterationsAhead = UINT_MAX;
 201   unsigned PrefFunctionLogAlignment = 0;
 202   unsigned PrefLoopLogAlignment = 0;
 203   unsigned MaxJumpTableSize = 0;
 204   unsigned WideningBaseCost = 0;
 205
 206   // ReserveXRegister[i] - X#i is not available as a general purpose register.
 207   BitVector ReserveXRegister;
 208
 209   // CustomCallUsedXRegister[i] - X#i call saved.
 210   BitVector CustomCallSavedXRegs;
 211
 212   bool IsLittle;
 213
 214   /// TargetTriple - What processor and OS we're targeting.
 215   Triple TargetTriple;
 216
 217   AArch64FrameLowering FrameLowering;
 218   AArch64InstrInfo InstrInfo;
 219   AArch64SelectionDAGInfo TSInfo;
 220   AArch64TargetLowering TLInfo;
 221
 222   /// GlobalISel related APIs.
 223   std::unique_ptr<CallLowering> CallLoweringInfo;
 224   std::unique_ptr<InstructionSelector> InstSelector;
 225   std::unique_ptr<LegalizerInfo> Legalizer;
 226   std::unique_ptr<RegisterBankInfo> RegBankInfo;
 227
 228 private:
 229   /// initializeSubtargetDependencies - Initializes using CPUString and the
 230   /// passed in feature string so that we can use initializer lists for
 231   /// subtarget initialization.
 232   AArch64Subtarget &initializeSubtargetDependencies(StringRef FS,
 233                                                     StringRef CPUString);
 234
 235   /// Initialize properties based on the selected processor family.
 236   void initializeProperties();
 237
 238 public:
 239   /// This constructor initializes the data members to match that
 240   /// of the specified triple.
 241   AArch64Subtarget(const Triple &TT, const std::string &CPU,
 242                    const std::string &FS, const TargetMachine &TM,
 243                    bool LittleEndian);
 244
 245   const AArch64SelectionDAGInfo *getSelectionDAGInfo() const override {
 246     return &TSInfo;
 247   }
 248   const AArch64FrameLowering *getFrameLowering() const override {
 249     return &FrameLowering;
 250   }
 251   const AArch64TargetLowering *getTargetLowering() const override {
 252     return &TLInfo;
 253   }
 254   const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
 255   const AArch64RegisterInfo *getRegisterInfo() const override {
 256     return &getInstrInfo()->getRegisterInfo();
 257   }
 258   const CallLowering *getCallLowering() const override;
 259   InstructionSelector *getInstructionSelector() const override;
 260   const LegalizerInfo *getLegalizerInfo() const override;
 261   const RegisterBankInfo *getRegBankInfo() const override;
 262   const Triple &getTargetTriple() const { return TargetTriple; }
 263   bool enableMachineScheduler() const override { return true; }
 264   bool enablePostRAScheduler() const override {
 265     return UsePostRAScheduler;
 266   }
 267
 268   /// Returns ARM processor family.
 269   /// Avoid this function! CPU specifics should be kept local to this class
 270   /// and preferably modeled with SubtargetFeatures or properties in
 271   /// initializeProperties().
 272   ARMProcFamilyEnum getProcFamily() const {
 273     return ARMProcFamily;
 274   }
 275
 276   bool hasV8_1aOps() const { return HasV8_1aOps; }
 277   bool hasV8_2aOps() const { return HasV8_2aOps; }
 278   bool hasV8_3aOps() const { return HasV8_3aOps; }
 279   bool hasV8_4aOps() const { return HasV8_4aOps; }
 280   bool hasV8_5aOps() const { return HasV8_5aOps; }
 281
 282   bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
 283
 284   bool hasZeroCycleZeroingGP() const { return HasZeroCycleZeroingGP; }
 285
 286   bool hasZeroCycleZeroingFP() const { return HasZeroCycleZeroingFP; }
 287
 288   bool hasZeroCycleZeroingFPWorkaround() const {
 289     return HasZeroCycleZeroingFPWorkaround;
 290   }
 291
 292   bool requiresStrictAlign() const { return StrictAlign; }
 293
 294   bool isXRaySupported() const override { return true; }
 295
 296   unsigned getMinVectorRegisterBitWidth() const {
 297     return MinVectorRegisterBitWidth;
 298   }
 299
 300   bool isXRegisterReserved(size_t i) const { return ReserveXRegister[i]; }
 301   unsigned getNumXRegisterReserved() const { return ReserveXRegister.count(); }
 302   bool isXRegCustomCalleeSaved(size_t i) const {
 303     return CustomCallSavedXRegs[i];
 304   }
 305   bool hasCustomCallingConv() const { return CustomCallSavedXRegs.any(); }
 306   bool hasFPARMv8() const { return HasFPARMv8; }
 307   bool hasNEON() const { return HasNEON; }
 308   bool hasCrypto() const { return HasCrypto; }
 309   bool hasDotProd() const { return HasDotProd; }
 310   bool hasCRC() const { return HasCRC; }
 311   bool hasLSE() const { return HasLSE; }
 312   bool hasRAS() const { return HasRAS; }
 313   bool hasRDM() const { return HasRDM; }
 314   bool hasSM4() const { return HasSM4; }
 315   bool hasSHA3() const { return HasSHA3; }
 316   bool hasSHA2() const { return HasSHA2; }
 317   bool hasAES() const { return HasAES; }
 318   bool balanceFPOps() const { return BalanceFPOps; }
 319   bool predictableSelectIsExpensive() const {
 320     return PredictableSelectIsExpensive;
 321   }
 322   bool hasCustomCheapAsMoveHandling() const { return CustomAsCheapAsMove; }
 323   bool hasExynosCheapAsMoveHandling() const { return ExynosAsCheapAsMove; }
 324   bool isMisaligned128StoreSlow() const { return Misaligned128StoreIsSlow; }
 325   bool isPaired128Slow() const { return Paired128IsSlow; }
 326   bool isSTRQroSlow() const { return STRQroIsSlow; }
 327   bool useAlternateSExtLoadCVTF32Pattern() const {
 328     return UseAlternateSExtLoadCVTF32Pattern;
 329   }
 330   bool hasArithmeticBccFusion() const { return HasArithmeticBccFusion; }
 331   bool hasArithmeticCbzFusion() const { return HasArithmeticCbzFusion; }
 332   bool hasFuseAddress() const { return HasFuseAddress; }
 333   bool hasFuseAES() const { return HasFuseAES; }
 334   bool hasFuseArithmeticLogic() const { return HasFuseArithmeticLogic; }
 335   bool hasFuseCCSelect() const { return HasFuseCCSelect; }
 336   bool hasFuseCryptoEOR() const { return HasFuseCryptoEOR; }
 337   bool hasFuseLiterals() const { return HasFuseLiterals; }
 338
 339   /// Return true if the CPU supports any kind of instruction fusion.
 340   bool hasFusion() const {
 341     return hasArithmeticBccFusion() || hasArithmeticCbzFusion() ||
 342            hasFuseAES() || hasFuseArithmeticLogic() ||
 343            hasFuseCCSelect() || hasFuseLiterals();
 344   }
 345
 346   bool useEL1ForTP() const { return UseEL1ForTP; }
 347   bool useEL2ForTP() const { return UseEL2ForTP; }
 348   bool useEL3ForTP() const { return UseEL3ForTP; }
 349
 350   bool useRSqrt() const { return UseRSqrt; }
 351   bool force32BitJumpTables() const { return Force32BitJumpTables; }
 352   unsigned getMaxInterleaveFactor() const { return MaxInterleaveFactor; }
 353   unsigned getVectorInsertExtractBaseCost() const {
 354     return VectorInsertExtractBaseCost;
 355   }
 356   unsigned getCacheLineSize() const { return CacheLineSize; }
 357   unsigned getPrefetchDistance() const { return PrefetchDistance; }
 358   unsigned getMinPrefetchStride() const { return MinPrefetchStride; }
 359   unsigned getMaxPrefetchIterationsAhead() const {
 360     return MaxPrefetchIterationsAhead;
 361   }
 362   unsigned getPrefFunctionLogAlignment() const {
 363     return PrefFunctionLogAlignment;
 364   }
 365   unsigned getPrefLoopLogAlignment() const { return PrefLoopLogAlignment; }
 366
 367   unsigned getMaximumJumpTableSize() const { return MaxJumpTableSize; }
 368
 369   unsigned getWideningBaseCost() const { return WideningBaseCost; }
 370
 371   /// CPU has TBI (top byte of addresses is ignored during HW address
 372   /// translation) and OS enables it.
 373   bool supportsAddressTopByteIgnored() const;
 374
 375   bool hasPerfMon() const { return HasPerfMon; }
 376   bool hasFullFP16() const { return HasFullFP16; }
 377   bool hasFP16FML() const { return HasFP16FML; }
 378   bool hasSPE() const { return HasSPE; }
 379   bool hasLSLFast() const { return HasLSLFast; }
 380   bool hasSVE() const { return HasSVE; }
 381   bool hasSVE2() const { return HasSVE2; }
 382   bool hasRCPC() const { return HasRCPC; }
 383   bool hasAggressiveFMA() const { return HasAggressiveFMA; }
 384   bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
 385   bool hasFRInt3264() const { return HasFRInt3264; }
 386   bool hasSpecRestrict() const { return HasSpecRestrict; }
 387   bool hasSSBS() const { return HasSSBS; }
 388   bool hasSB() const { return HasSB; }
 389   bool hasPredRes() const { return HasPredRes; }
 390   bool hasCCDP() const { return HasCCDP; }
 391   bool hasBTI() const { return HasBTI; }
 392   bool hasRandGen() const { return HasRandGen; }
 393   bool hasMTE() const { return HasMTE; }
 394   bool hasTME() const { return HasTME; }
 395   // Arm SVE2 extensions
 396   bool hasSVE2AES() const { return HasSVE2AES; }
 397   bool hasSVE2SM4() const { return HasSVE2SM4; }
 398   bool hasSVE2SHA3() const { return HasSVE2SHA3; }
 399   bool hasSVE2BitPerm() const { return HasSVE2BitPerm; }
 400
 401   bool isLittleEndian() const { return IsLittle; }
 402
 403   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
 404   bool isTargetIOS() const { return TargetTriple.isiOS(); }
 405   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
 406   bool isTargetWindows() const { return TargetTriple.isOSWindows(); }
 407   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
 408   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
 409
 410   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
 411   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
 412   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
 413
 414   bool useAA() const override { return UseAA; }
 415
 416   bool hasVH() const { return HasVH; }
 417   bool hasPAN() const { return HasPAN; }
 418   bool hasLOR() const { return HasLOR; }
 419
 420   bool hasPsUAO() const { return HasPsUAO; }
 421   bool hasPAN_RWV() const { return HasPAN_RWV; }
 422   bool hasCCPP() const { return HasCCPP; }
 423
 424   bool hasPA() const { return HasPA; }
 425   bool hasJS() const { return HasJS; }
 426   bool hasCCIDX() const { return HasCCIDX; }
 427   bool hasComplxNum() const { return HasComplxNum; }
 428
 429   bool hasNV() const { return HasNV; }
 430   bool hasRASv8_4() const { return HasRASv8_4; }
 431   bool hasMPAM() const { return HasMPAM; }
 432   bool hasDIT() const { return HasDIT; }
 433   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
 434   bool hasAM() const { return HasAM; }
 435   bool hasSEL2() const { return HasSEL2; }
 436   bool hasTLB_RMI() const { return HasTLB_RMI; }
 437   bool hasFMI() const { return HasFMI; }
 438   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
 439
 440   bool useSmallAddressing() const {
 441     switch (TLInfo.getTargetMachine().getCodeModel()) {
 442       case CodeModel::Kernel:
 443         // Kernel is currently allowed only for Fuchsia targets,
 444         // where it is the same as Small for almost all purposes.
 445       case CodeModel::Small:
 446         return true;
 447       default:
 448         return false;
 449     }
 450   }
 451
 452   /// ParseSubtargetFeatures - Parses features string setting specified
 453   /// subtarget options.  Definition of function is auto generated by tblgen.
 454   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 455
 456   /// ClassifyGlobalReference - Find the target operand flags that describe
 457   /// how a global value should be referenced for the current subtarget.
 458   unsigned ClassifyGlobalReference(const GlobalValue *GV,
 459                                    const TargetMachine &TM) const;
 460
 461   unsigned classifyGlobalFunctionReference(const GlobalValue *GV,
 462                                            const TargetMachine &TM) const;
 463
 464   void overrideSchedPolicy(MachineSchedPolicy &Policy,
 465                            unsigned NumRegionInstrs) const override;
 466
 467   bool enableEarlyIfConversion() const override;
 468
 469   std::unique_ptr<PBQPRAConstraint> getCustomPBQPConstraints() const override;
 470
 471   bool isCallingConvWin64(CallingConv::ID CC) const {
 472     switch (CC) {
 473     case CallingConv::C:
 474     case CallingConv::Fast:
 475     case CallingConv::Swift:
 476       return isTargetWindows();
 477     case CallingConv::Win64:
 478       return true;
 479     default:
 480       return false;
 481     }
 482   }
 483
 484   void mirFileLoaded(MachineFunction &MF) const override;
 485 };
 486 } // End llvm namespace
 487
 488 #endif