lib/Target/AMDGPU/AMDGPUISelLowering.h

   1 //===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Interface definition of the TargetLowering class that is common
  11 /// to all AMD GPUs.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
  16 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUISELLOWERING_H
  17
  18 #include "AMDGPU.h"
  19 #include "llvm/CodeGen/CallingConvLower.h"
  20 #include "llvm/CodeGen/TargetLowering.h"
  21
  22 namespace llvm {
  23
  24 class AMDGPUMachineFunction;
  25 class AMDGPUSubtarget;
  26 struct ArgDescriptor;
  27
  28 class AMDGPUTargetLowering : public TargetLowering {
  29 private:
  30   const AMDGPUSubtarget *Subtarget;
  31
  32   /// \returns AMDGPUISD::FFBH_U32 node if the incoming \p Op may have been
  33   /// legalized from a smaller type VT. Need to match pre-legalized type because
  34   /// the generic legalization inserts the add/sub between the select and
  35   /// compare.
  36   SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
  37
  38 public:
  39   static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
  40   static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
  41
  42 protected:
  43   SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
  44   SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
  45   /// Split a vector store into multiple scalar stores.
  46   /// \returns The resulting chain.
  47
  48   SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
  49   SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
  50   SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
  51   SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
  52   SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
  53
  54   SDValue LowerFROUND32_16(SDValue Op, SelectionDAG &DAG) const;
  55   SDValue LowerFROUND64(SDValue Op, SelectionDAG &DAG) const;
  56   SDValue LowerFROUND(SDValue Op, SelectionDAG &DAG) const;
  57   SDValue LowerFFLOOR(SDValue Op, SelectionDAG &DAG) const;
  58   SDValue LowerFLOG(SDValue Op, SelectionDAG &DAG,
  59                     double Log2BaseInverted) const;
  60   SDValue lowerFEXP(SDValue Op, SelectionDAG &DAG) const;
  61
  62   SDValue LowerCTLZ_CTTZ(SDValue Op, SelectionDAG &DAG) const;
  63
  64   SDValue LowerINT_TO_FP32(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  65   SDValue LowerINT_TO_FP64(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  66   SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
  67   SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
  68
  69   SDValue LowerFP64_TO_INT(SDValue Op, SelectionDAG &DAG, bool Signed) const;
  70   SDValue LowerFP_TO_FP16(SDValue Op, SelectionDAG &DAG) const;
  71   SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
  72   SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
  73
  74   SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
  75
  76 protected:
  77   bool shouldCombineMemoryType(EVT VT) const;
  78   SDValue performLoadCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  79   SDValue performStoreCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  80   SDValue performAssertSZExtCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  81   SDValue performIntrinsicWOChainCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  82
  83   SDValue splitBinaryBitConstantOpImpl(DAGCombinerInfo &DCI, const SDLoc &SL,
  84                                        unsigned Opc, SDValue LHS,
  85                                        uint32_t ValLo, uint32_t ValHi) const;
  86   SDValue performShlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  87   SDValue performSraCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  88   SDValue performSrlCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  89   SDValue performTruncateCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  90   SDValue performMulCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  91   SDValue performMulhsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  92   SDValue performMulhuCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  93   SDValue performMulLoHi24Combine(SDNode *N, DAGCombinerInfo &DCI) const;
  94   SDValue performCtlz_CttzCombine(const SDLoc &SL, SDValue Cond, SDValue LHS,
  95                              SDValue RHS, DAGCombinerInfo &DCI) const;
  96   SDValue performSelectCombine(SDNode *N, DAGCombinerInfo &DCI) const;
  97
  98   bool isConstantCostlierToNegate(SDValue N) const;
  99   SDValue performFNegCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 100   SDValue performFAbsCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 101   SDValue performRcpCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 102
 103   static EVT getEquivalentMemType(LLVMContext &Context, EVT VT);
 104
 105   virtual SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
 106                                      SelectionDAG &DAG) const;
 107
 108   /// Return 64-bit value Op as two 32-bit integers.
 109   std::pair<SDValue, SDValue> split64BitValue(SDValue Op,
 110                                               SelectionDAG &DAG) const;
 111   SDValue getLoHalf64(SDValue Op, SelectionDAG &DAG) const;
 112   SDValue getHiHalf64(SDValue Op, SelectionDAG &DAG) const;
 113
 114   /// Split a vector type into two parts. The first part is a power of two
 115   /// vector. The second part is whatever is left over, and is a scalar if it
 116   /// would otherwise be a 1-vector.
 117   std::pair<EVT, EVT> getSplitDestVTs(const EVT &VT, SelectionDAG &DAG) const;
 118
 119   /// Split a vector value into two parts of types LoVT and HiVT. HiVT could be
 120   /// scalar.
 121   std::pair<SDValue, SDValue> splitVector(const SDValue &N, const SDLoc &DL,
 122                                           const EVT &LoVT, const EVT &HighVT,
 123                                           SelectionDAG &DAG) const;
 124
 125   /// Split a vector load into 2 loads of half the vector.
 126   SDValue SplitVectorLoad(SDValue Op, SelectionDAG &DAG) const;
 127
 128   /// Widen a vector load from vec3 to vec4.
 129   SDValue WidenVectorLoad(SDValue Op, SelectionDAG &DAG) const;
 130
 131   /// Split a vector store into 2 stores of half the vector.
 132   SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
 133
 134   SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 135   SDValue LowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
 136   SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
 137   SDValue LowerDIVREM24(SDValue Op, SelectionDAG &DAG, bool sign) const;
 138   void LowerUDIVREM64(SDValue Op, SelectionDAG &DAG,
 139                                     SmallVectorImpl<SDValue> &Results) const;
 140
 141   void analyzeFormalArgumentsCompute(
 142     CCState &State,
 143     const SmallVectorImpl<ISD::InputArg> &Ins) const;
 144
 145 public:
 146   AMDGPUTargetLowering(const TargetMachine &TM, const AMDGPUSubtarget &STI);
 147
 148   bool mayIgnoreSignedZero(SDValue Op) const {
 149     if (getTargetMachine().Options.NoSignedZerosFPMath)
 150       return true;
 151
 152     const auto Flags = Op.getNode()->getFlags();
 153     if (Flags.isDefined())
 154       return Flags.hasNoSignedZeros();
 155
 156     return false;
 157   }
 158
 159   static inline SDValue stripBitcast(SDValue Val) {
 160     return Val.getOpcode() == ISD::BITCAST ? Val.getOperand(0) : Val;
 161   }
 162
 163   static bool allUsesHaveSourceMods(const SDNode *N,
 164                                     unsigned CostThreshold = 4);
 165   bool isFAbsFree(EVT VT) const override;
 166   bool isFNegFree(EVT VT) const override;
 167   bool isTruncateFree(EVT Src, EVT Dest) const override;
 168   bool isTruncateFree(Type *Src, Type *Dest) const override;
 169
 170   bool isZExtFree(Type *Src, Type *Dest) const override;
 171   bool isZExtFree(EVT Src, EVT Dest) const override;
 172   bool isZExtFree(SDValue Val, EVT VT2) const override;
 173
 174   bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
 175
 176   MVT getVectorIdxTy(const DataLayout &) const override;
 177   bool isSelectSupported(SelectSupportKind) const override;
 178
 179   bool isFPImmLegal(const APFloat &Imm, EVT VT,
 180                     bool ForCodeSize) const override;
 181   bool ShouldShrinkFPConstant(EVT VT) const override;
 182   bool shouldReduceLoadWidth(SDNode *Load,
 183                              ISD::LoadExtType ExtType,
 184                              EVT ExtVT) const override;
 185
 186   bool isLoadBitCastBeneficial(EVT, EVT, const SelectionDAG &DAG,
 187                                const MachineMemOperand &MMO) const final;
 188
 189   bool storeOfVectorConstantIsCheap(EVT MemVT,
 190                                     unsigned NumElem,
 191                                     unsigned AS) const override;
 192   bool aggressivelyPreferBuildVectorSources(EVT VecVT) const override;
 193   bool isCheapToSpeculateCttz() const override;
 194   bool isCheapToSpeculateCtlz() const override;
 195
 196   bool isSDNodeAlwaysUniform(const SDNode *N) const override;
 197   static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg);
 198   static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg);
 199
 200   SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 201                       const SmallVectorImpl<ISD::OutputArg> &Outs,
 202                       const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
 203                       SelectionDAG &DAG) const override;
 204
 205   SDValue addTokenForArgument(SDValue Chain,
 206                               SelectionDAG &DAG,
 207                               MachineFrameInfo &MFI,
 208                               int ClobberedFI) const;
 209
 210   SDValue lowerUnhandledCall(CallLoweringInfo &CLI,
 211                              SmallVectorImpl<SDValue> &InVals,
 212                              StringRef Reason) const;
 213   SDValue LowerCall(CallLoweringInfo &CLI,
 214                     SmallVectorImpl<SDValue> &InVals) const override;
 215
 216   SDValue LowerDYNAMIC_STACKALLOC(SDValue Op,
 217                                   SelectionDAG &DAG) const;
 218
 219   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 220   SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 221   void ReplaceNodeResults(SDNode * N,
 222                           SmallVectorImpl<SDValue> &Results,
 223                           SelectionDAG &DAG) const override;
 224
 225   SDValue combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS,
 226                                SDValue RHS, SDValue True, SDValue False,
 227                                SDValue CC, DAGCombinerInfo &DCI) const;
 228
 229   const char* getTargetNodeName(unsigned Opcode) const override;
 230
 231   // FIXME: Turn off MergeConsecutiveStores() before Instruction Selection for
 232   // AMDGPU.  Commit r319036,
 233   // (https://github.com/llvm/llvm-project/commit/db77e57ea86d941a4262ef60261692f4cb6893e6)
 234   // turned on MergeConsecutiveStores() before Instruction Selection for all
 235   // targets.  Enough AMDGPU compiles go into an infinite loop (
 236   // MergeConsecutiveStores() merges two stores; LegalizeStoreOps() un-merges;
 237   // MergeConsecutiveStores() re-merges, etc. ) to warrant turning it off for
 238   // now.
 239   bool mergeStoresAfterLegalization(EVT) const override { return false; }
 240
 241   bool isFsqrtCheap(SDValue Operand, SelectionDAG &DAG) const override {
 242     return true;
 243   }
 244   SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
 245                            int &RefinementSteps, bool &UseOneConstNR,
 246                            bool Reciprocal) const override;
 247   SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
 248                            int &RefinementSteps) const override;
 249
 250   virtual SDNode *PostISelFolding(MachineSDNode *N,
 251                                   SelectionDAG &DAG) const = 0;
 252
 253   /// Determine which of the bits specified in \p Mask are known to be
 254   /// either zero or one and return them in the \p KnownZero and \p KnownOne
 255   /// bitsets.
 256   void computeKnownBitsForTargetNode(const SDValue Op,
 257                                      KnownBits &Known,
 258                                      const APInt &DemandedElts,
 259                                      const SelectionDAG &DAG,
 260                                      unsigned Depth = 0) const override;
 261
 262   unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts,
 263                                            const SelectionDAG &DAG,
 264                                            unsigned Depth = 0) const override;
 265
 266   bool isKnownNeverNaNForTargetNode(SDValue Op,
 267                                     const SelectionDAG &DAG,
 268                                     bool SNaN = false,
 269                                     unsigned Depth = 0) const override;
 270
 271   /// Helper function that adds Reg to the LiveIn list of the DAG's
 272   /// MachineFunction.
 273   ///
 274   /// \returns a RegisterSDNode representing Reg if \p RawReg is true, otherwise
 275   /// a copy from the register.
 276   SDValue CreateLiveInRegister(SelectionDAG &DAG,
 277                                const TargetRegisterClass *RC,
 278                                unsigned Reg, EVT VT,
 279                                const SDLoc &SL,
 280                                bool RawReg = false) const;
 281   SDValue CreateLiveInRegister(SelectionDAG &DAG,
 282                                const TargetRegisterClass *RC,
 283                                unsigned Reg, EVT VT) const {
 284     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()));
 285   }
 286
 287   // Returns the raw live in register rather than a copy from it.
 288   SDValue CreateLiveInRegisterRaw(SelectionDAG &DAG,
 289                                   const TargetRegisterClass *RC,
 290                                   unsigned Reg, EVT VT) const {
 291     return CreateLiveInRegister(DAG, RC, Reg, VT, SDLoc(DAG.getEntryNode()), true);
 292   }
 293
 294   /// Similar to CreateLiveInRegister, except value maybe loaded from a stack
 295   /// slot rather than passed in a register.
 296   SDValue loadStackInputValue(SelectionDAG &DAG,
 297                               EVT VT,
 298                               const SDLoc &SL,
 299                               int64_t Offset) const;
 300
 301   SDValue storeStackInputValue(SelectionDAG &DAG,
 302                                const SDLoc &SL,
 303                                SDValue Chain,
 304                                SDValue ArgVal,
 305                                int64_t Offset) const;
 306
 307   SDValue loadInputValue(SelectionDAG &DAG,
 308                          const TargetRegisterClass *RC,
 309                          EVT VT, const SDLoc &SL,
 310                          const ArgDescriptor &Arg) const;
 311
 312   enum ImplicitParameter {
 313     FIRST_IMPLICIT,
 314     GRID_DIM = FIRST_IMPLICIT,
 315     GRID_OFFSET,
 316   };
 317
 318   /// Helper function that returns the byte offset of the given
 319   /// type of implicit parameter.
 320   uint32_t getImplicitParameterOffset(const MachineFunction &MF,
 321                                       const ImplicitParameter Param) const;
 322
 323   MVT getFenceOperandTy(const DataLayout &DL) const override {
 324     return MVT::i32;
 325   }
 326
 327   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 328
 329   bool SelectFlatOffset(bool IsSigned, SelectionDAG &DAG, SDNode *N,
 330                         SDValue Addr, SDValue &VAddr, SDValue &Offset,
 331                         SDValue &SLC) const;
 332 };
 333
 334 namespace AMDGPUISD {
 335
 336 enum NodeType : unsigned {
 337   // AMDIL ISD Opcodes
 338   FIRST_NUMBER = ISD::BUILTIN_OP_END,
 339   UMUL,        // 32bit unsigned multiplication
 340   BRANCH_COND,
 341   // End AMDIL ISD Opcodes
 342
 343   // Function call.
 344   CALL,
 345   TC_RETURN,
 346   TRAP,
 347
 348   // Masked control flow nodes.
 349   IF,
 350   ELSE,
 351   LOOP,
 352
 353   // A uniform kernel return that terminates the wavefront.
 354   ENDPGM,
 355
 356   // Return to a shader part's epilog code.
 357   RETURN_TO_EPILOG,
 358
 359   // Return with values from a non-entry function.
 360   RET_FLAG,
 361
 362   DWORDADDR,
 363   FRACT,
 364
 365   /// CLAMP value between 0.0 and 1.0. NaN clamped to 0, following clamp output
 366   /// modifier behavior with dx10_enable.
 367   CLAMP,
 368
 369   // This is SETCC with the full mask result which is used for a compare with a
 370   // result bit per item in the wavefront.
 371   SETCC,
 372   SETREG,
 373
 374   DENORM_MODE,
 375
 376   // FP ops with input and output chain.
 377   FMA_W_CHAIN,
 378   FMUL_W_CHAIN,
 379
 380   // SIN_HW, COS_HW - f32 for SI, 1 ULP max error, valid from -100 pi to 100 pi.
 381   // Denormals handled on some parts.
 382   COS_HW,
 383   SIN_HW,
 384   FMAX_LEGACY,
 385   FMIN_LEGACY,
 386
 387   FMAX3,
 388   SMAX3,
 389   UMAX3,
 390   FMIN3,
 391   SMIN3,
 392   UMIN3,
 393   FMED3,
 394   SMED3,
 395   UMED3,
 396   FDOT2,
 397   URECIP,
 398   DIV_SCALE,
 399   DIV_FMAS,
 400   DIV_FIXUP,
 401   // For emitting ISD::FMAD when f32 denormals are enabled because mac/mad is
 402   // treated as an illegal operation.
 403   FMAD_FTZ,
 404   TRIG_PREOP, // 1 ULP max error for f64
 405
 406   // RCP, RSQ - For f32, 1 ULP max error, no denormal handling.
 407   //            For f64, max error 2^29 ULP, handles denormals.
 408   RCP,
 409   RSQ,
 410   RCP_LEGACY,
 411   RSQ_LEGACY,
 412   RCP_IFLAG,
 413   FMUL_LEGACY,
 414   RSQ_CLAMP,
 415   LDEXP,
 416   FP_CLASS,
 417   DOT4,
 418   CARRY,
 419   BORROW,
 420   BFE_U32, // Extract range of bits with zero extension to 32-bits.
 421   BFE_I32, // Extract range of bits with sign extension to 32-bits.
 422   BFI, // (src0 & src1) | (~src0 & src2)
 423   BFM, // Insert a range of bits into a 32-bit word.
 424   FFBH_U32, // ctlz with -1 if input is zero.
 425   FFBH_I32,
 426   FFBL_B32, // cttz with -1 if input is zero.
 427   MUL_U24,
 428   MUL_I24,
 429   MULHI_U24,
 430   MULHI_I24,
 431   MAD_U24,
 432   MAD_I24,
 433   MAD_U64_U32,
 434   MAD_I64_I32,
 435   MUL_LOHI_I24,
 436   MUL_LOHI_U24,
 437   PERM,
 438   TEXTURE_FETCH,
 439   EXPORT, // exp on SI+
 440   EXPORT_DONE, // exp on SI+ with done bit set
 441   R600_EXPORT,
 442   CONST_ADDRESS,
 443   REGISTER_LOAD,
 444   REGISTER_STORE,
 445   SAMPLE,
 446   SAMPLEB,
 447   SAMPLED,
 448   SAMPLEL,
 449
 450   // These cvt_f32_ubyte* nodes need to remain consecutive and in order.
 451   CVT_F32_UBYTE0,
 452   CVT_F32_UBYTE1,
 453   CVT_F32_UBYTE2,
 454   CVT_F32_UBYTE3,
 455
 456   // Convert two float 32 numbers into a single register holding two packed f16
 457   // with round to zero.
 458   CVT_PKRTZ_F16_F32,
 459   CVT_PKNORM_I16_F32,
 460   CVT_PKNORM_U16_F32,
 461   CVT_PK_I16_I32,
 462   CVT_PK_U16_U32,
 463
 464   // Same as the standard node, except the high bits of the resulting integer
 465   // are known 0.
 466   FP_TO_FP16,
 467
 468   // Wrapper around fp16 results that are known to zero the high bits.
 469   FP16_ZEXT,
 470
 471   /// This node is for VLIW targets and it is used to represent a vector
 472   /// that is stored in consecutive registers with the same channel.
 473   /// For example:
 474   ///   |X  |Y|Z|W|
 475   /// T0|v.x| | | |
 476   /// T1|v.y| | | |
 477   /// T2|v.z| | | |
 478   /// T3|v.w| | | |
 479   BUILD_VERTICAL_VECTOR,
 480   /// Pointer to the start of the shader's constant data.
 481   CONST_DATA_PTR,
 482   INIT_EXEC,
 483   INIT_EXEC_FROM_INPUT,
 484   INTERP_MOV,
 485   INTERP_P1,
 486   INTERP_P2,
 487   INTERP_P1LL_F16,
 488   INTERP_P1LV_F16,
 489   INTERP_P2_F16,
 490   PC_ADD_REL_OFFSET,
 491   LDS,
 492   KILL,
 493   DUMMY_CHAIN,
 494   FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
 495   LOAD_D16_HI,
 496   LOAD_D16_LO,
 497   LOAD_D16_HI_I8,
 498   LOAD_D16_HI_U8,
 499   LOAD_D16_LO_I8,
 500   LOAD_D16_LO_U8,
 501
 502   STORE_MSKOR,
 503   LOAD_CONSTANT,
 504   TBUFFER_STORE_FORMAT,
 505   TBUFFER_STORE_FORMAT_D16,
 506   TBUFFER_LOAD_FORMAT,
 507   TBUFFER_LOAD_FORMAT_D16,
 508   DS_ORDERED_COUNT,
 509   ATOMIC_CMP_SWAP,
 510   ATOMIC_INC,
 511   ATOMIC_DEC,
 512   ATOMIC_LOAD_FMIN,
 513   ATOMIC_LOAD_FMAX,
 514   BUFFER_LOAD,
 515   BUFFER_LOAD_UBYTE,
 516   BUFFER_LOAD_USHORT,
 517   BUFFER_LOAD_BYTE,
 518   BUFFER_LOAD_SHORT,
 519   BUFFER_LOAD_FORMAT,
 520   BUFFER_LOAD_FORMAT_D16,
 521   SBUFFER_LOAD,
 522   BUFFER_STORE,
 523   BUFFER_STORE_BYTE,
 524   BUFFER_STORE_SHORT,
 525   BUFFER_STORE_FORMAT,
 526   BUFFER_STORE_FORMAT_D16,
 527   BUFFER_ATOMIC_SWAP,
 528   BUFFER_ATOMIC_ADD,
 529   BUFFER_ATOMIC_SUB,
 530   BUFFER_ATOMIC_SMIN,
 531   BUFFER_ATOMIC_UMIN,
 532   BUFFER_ATOMIC_SMAX,
 533   BUFFER_ATOMIC_UMAX,
 534   BUFFER_ATOMIC_AND,
 535   BUFFER_ATOMIC_OR,
 536   BUFFER_ATOMIC_XOR,
 537   BUFFER_ATOMIC_INC,
 538   BUFFER_ATOMIC_DEC,
 539   BUFFER_ATOMIC_CMPSWAP,
 540   BUFFER_ATOMIC_FADD,
 541   BUFFER_ATOMIC_PK_FADD,
 542   ATOMIC_FADD,
 543   ATOMIC_PK_FADD,
 544
 545   LAST_AMDGPU_ISD_NUMBER
 546 };
 547
 548
 549 } // End namespace AMDGPUISD
 550
 551 } // End namespace llvm
 552
 553 #endif