lib/Target/AMDGPU/AMDGPURegisterBankInfo.h

   1 //===- AMDGPURegisterBankInfo -----------------------------------*- C++ -*-==//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 /// \file
   9 /// This file declares the targeting of the RegisterBankInfo class for AMDGPU.
  10 /// \todo This should be generated by TableGen.
  11 //===----------------------------------------------------------------------===//
  12
  13 #ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  14 #define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERBANKINFO_H
  15
  16 #include "llvm/CodeGen/Register.h"
  17 #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
  18
  19 #define GET_REGBANK_DECLARATIONS
  20 #include "AMDGPUGenRegisterBank.inc"
  21 #undef GET_REGBANK_DECLARATIONS
  22
  23 namespace llvm {
  24
  25 class LLT;
  26 class MachineIRBuilder;
  27 class SIRegisterInfo;
  28 class TargetRegisterInfo;
  29
  30 /// This class provides the information for the target register banks.
  31 class AMDGPUGenRegisterBankInfo : public RegisterBankInfo {
  32
  33 protected:
  34
  35 #define GET_TARGET_REGBANK_CLASS
  36 #include "AMDGPUGenRegisterBank.inc"
  37 };
  38 class AMDGPURegisterBankInfo : public AMDGPUGenRegisterBankInfo {
  39   const SIRegisterInfo *TRI;
  40
  41   void executeInWaterfallLoop(MachineInstr &MI,
  42                               MachineRegisterInfo &MRI,
  43                               ArrayRef<unsigned> OpIndices) const;
  44
  45   void constrainOpWithReadfirstlane(MachineInstr &MI, MachineRegisterInfo &MRI,
  46                                     unsigned OpIdx) const;
  47   bool applyMappingWideLoad(MachineInstr &MI,
  48                             const AMDGPURegisterBankInfo::OperandsMapper &OpdMapper,
  49                             MachineRegisterInfo &MRI) const;
  50
  51   /// See RegisterBankInfo::applyMapping.
  52   void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
  53
  54   const RegisterBankInfo::InstructionMapping &
  55   getInstrMappingForLoad(const MachineInstr &MI) const;
  56
  57   unsigned getRegBankID(Register Reg, const MachineRegisterInfo &MRI,
  58                         const TargetRegisterInfo &TRI,
  59                         unsigned Default = AMDGPU::VGPRRegBankID) const;
  60
  61   /// Split 64-bit value \p Reg into two 32-bit halves and populate them into \p
  62   /// Regs. This appropriately sets the regbank of the new registers.
  63   void split64BitValueForMapping(MachineIRBuilder &B,
  64                                  SmallVector<Register, 2> &Regs,
  65                                  LLT HalfTy,
  66                                  Register Reg) const;
  67
  68   template <unsigned NumOps>
  69   struct OpRegBankEntry {
  70     int8_t RegBanks[NumOps];
  71     int16_t Cost;
  72   };
  73
  74   template <unsigned NumOps>
  75   InstructionMappings
  76   addMappingFromTable(const MachineInstr &MI, const MachineRegisterInfo &MRI,
  77                       const std::array<unsigned, NumOps> RegSrcOpIdx,
  78                       ArrayRef<OpRegBankEntry<NumOps>> Table) const;
  79
  80   RegisterBankInfo::InstructionMappings
  81   getInstrAlternativeMappingsIntrinsic(
  82       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
  83
  84   RegisterBankInfo::InstructionMappings
  85   getInstrAlternativeMappingsIntrinsicWSideEffects(
  86       const MachineInstr &MI, const MachineRegisterInfo &MRI) const;
  87
  88   bool isSALUMapping(const MachineInstr &MI) const;
  89   const InstructionMapping &getDefaultMappingSOP(const MachineInstr &MI) const;
  90   const InstructionMapping &getDefaultMappingVOP(const MachineInstr &MI) const;
  91   const InstructionMapping &getDefaultMappingAllVGPR(
  92     const MachineInstr &MI) const;
  93 public:
  94   AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI);
  95
  96   unsigned copyCost(const RegisterBank &A, const RegisterBank &B,
  97                     unsigned Size) const override;
  98
  99   unsigned getBreakDownCost(const ValueMapping &ValMapping,
 100                             const RegisterBank *CurBank = nullptr) const override;
 101
 102   const RegisterBank &
 103   getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
 104
 105   InstructionMappings
 106   getInstrAlternativeMappings(const MachineInstr &MI) const override;
 107
 108   const InstructionMapping &
 109   getInstrMapping(const MachineInstr &MI) const override;
 110 };
 111 } // End llvm namespace.
 112 #endif