lib/Target/ARM/ARM.h

   1 //===-- ARM.h - Top-level interface for ARM representation ------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file contains the entry points for global functions defined in the LLVM
  10 // ARM back-end.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_ARM_H
  15 #define LLVM_LIB_TARGET_ARM_ARM_H
  16
  17 #include "llvm/IR/LegacyPassManager.h"
  18 #include "llvm/Support/CodeGen.h"
  19 #include <functional>
  20 #include <vector>
  21
  22 namespace llvm {
  23
  24 class ARMAsmPrinter;
  25 class ARMBaseTargetMachine;
  26 class ARMRegisterBankInfo;
  27 class ARMSubtarget;
  28 struct BasicBlockInfo;
  29 class Function;
  30 class FunctionPass;
  31 class InstructionSelector;
  32 class MachineBasicBlock;
  33 class MachineFunction;
  34 class MachineInstr;
  35 class MCInst;
  36 class PassRegistry;
  37
  38 Pass *createMVETailPredicationPass();
  39 FunctionPass *createARMLowOverheadLoopsPass();
  40 Pass *createARMParallelDSPPass();
  41 FunctionPass *createARMISelDag(ARMBaseTargetMachine &TM,
  42                                CodeGenOpt::Level OptLevel);
  43 FunctionPass *createA15SDOptimizerPass();
  44 FunctionPass *createARMLoadStoreOptimizationPass(bool PreAlloc = false);
  45 FunctionPass *createARMExpandPseudoPass();
  46 FunctionPass *createARMCodeGenPreparePass();
  47 FunctionPass *createARMConstantIslandPass();
  48 FunctionPass *createMLxExpansionPass();
  49 FunctionPass *createThumb2ITBlockPass();
  50 FunctionPass *createMVEVPTBlockPass();
  51 FunctionPass *createARMOptimizeBarriersPass();
  52 FunctionPass *createThumb2SizeReductionPass(
  53     std::function<bool(const Function &)> Ftor = nullptr);
  54 InstructionSelector *
  55 createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
  56                              const ARMRegisterBankInfo &RBI);
  57
  58 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
  59                                   ARMAsmPrinter &AP);
  60
  61 void initializeARMParallelDSPPass(PassRegistry &);
  62 void initializeARMLoadStoreOptPass(PassRegistry &);
  63 void initializeARMPreAllocLoadStoreOptPass(PassRegistry &);
  64 void initializeARMCodeGenPreparePass(PassRegistry &);
  65 void initializeARMConstantIslandsPass(PassRegistry &);
  66 void initializeARMExpandPseudoPass(PassRegistry &);
  67 void initializeThumb2SizeReducePass(PassRegistry &);
  68 void initializeThumb2ITBlockPass(PassRegistry &);
  69 void initializeMVEVPTBlockPass(PassRegistry &);
  70 void initializeARMLowOverheadLoopsPass(PassRegistry &);
  71 void initializeMVETailPredicationPass(PassRegistry &);
  72
  73 } // end namespace llvm
  74
  75 #endif // LLVM_LIB_TARGET_ARM_ARM_H