lib/Target/ARM/ARMParallelDSP.cpp

   1 //===- ARMParallelDSP.cpp - Parallel DSP Pass -----------------------------===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 /// \file
  10 /// Armv6 introduced instructions to perform 32-bit SIMD operations. The
  11 /// purpose of this pass is do some IR pattern matching to create ACLE
  12 /// DSP intrinsics, which map on these 32-bit SIMD operations.
  13 /// This pass runs only when unaligned accesses is supported/enabled.
  14 //
  15 //===----------------------------------------------------------------------===//
  16
  17 #include "llvm/ADT/Statistic.h"
  18 #include "llvm/ADT/SmallPtrSet.h"
  19 #include "llvm/Analysis/AliasAnalysis.h"
  20 #include "llvm/Analysis/LoopAccessAnalysis.h"
  21 #include "llvm/IR/Instructions.h"
  22 #include "llvm/IR/NoFolder.h"
  23 #include "llvm/Transforms/Scalar.h"
  24 #include "llvm/Transforms/Utils/BasicBlockUtils.h"
  25 #include "llvm/Pass.h"
  26 #include "llvm/PassRegistry.h"
  27 #include "llvm/PassSupport.h"
  28 #include "llvm/Support/Debug.h"
  29 #include "llvm/IR/PatternMatch.h"
  30 #include "llvm/CodeGen/TargetPassConfig.h"
  31 #include "ARM.h"
  32 #include "ARMSubtarget.h"
  33
  34 using namespace llvm;
  35 using namespace PatternMatch;
  36
  37 #define DEBUG_TYPE "arm-parallel-dsp"
  38
  39 STATISTIC(NumSMLAD , "Number of smlad instructions generated");
  40
  41 static cl::opt<bool>
  42 DisableParallelDSP("disable-arm-parallel-dsp", cl::Hidden, cl::init(false),
  43                    cl::desc("Disable the ARM Parallel DSP pass"));
  44
  45 namespace {
  46   struct MulCandidate;
  47   class Reduction;
  48
  49   using MulCandList = SmallVector<std::unique_ptr<MulCandidate>, 8>;
  50   using MemInstList = SmallVectorImpl<LoadInst*>;
  51   using MulPairList = SmallVector<std::pair<MulCandidate*, MulCandidate*>, 8>;
  52
  53   // 'MulCandidate' holds the multiplication instructions that are candidates
  54   // for parallel execution.
  55   struct MulCandidate {
  56     Instruction   *Root;
  57     Value*        LHS;
  58     Value*        RHS;
  59     bool          Exchange = false;
  60     bool          ReadOnly = true;
  61     bool          Paired = false;
  62     SmallVector<LoadInst*, 2> VecLd;    // Container for loads to widen.
  63
  64     MulCandidate(Instruction *I, Value *lhs, Value *rhs) :
  65       Root(I), LHS(lhs), RHS(rhs) { }
  66
  67     bool HasTwoLoadInputs() const {
  68       return isa<LoadInst>(LHS) && isa<LoadInst>(RHS);
  69     }
  70
  71     LoadInst *getBaseLoad() const {
  72       return VecLd.front();
  73     }
  74   };
  75
  76   /// Represent a sequence of multiply-accumulate operations with the aim to
  77   /// perform the multiplications in parallel.
  78   class Reduction {
  79     Instruction     *Root = nullptr;
  80     Value           *Acc = nullptr;
  81     MulCandList     Muls;
  82     MulPairList        MulPairs;
  83     SetVector<Instruction*> Adds;
  84
  85   public:
  86     Reduction() = delete;
  87
  88     Reduction (Instruction *Add) : Root(Add) { }
  89
  90     /// Record an Add instruction that is a part of the this reduction.
  91     void InsertAdd(Instruction *I) { Adds.insert(I); }
  92
  93     /// Create MulCandidates, each rooted at a Mul instruction, that is a part
  94     /// of this reduction.
  95     void InsertMuls() {
  96       auto GetMulOperand = [](Value *V) -> Instruction* {
  97         if (auto *SExt = dyn_cast<SExtInst>(V)) {
  98           if (auto *I = dyn_cast<Instruction>(SExt->getOperand(0)))
  99             if (I->getOpcode() == Instruction::Mul)
 100               return I;
 101         } else if (auto *I = dyn_cast<Instruction>(V)) {
 102           if (I->getOpcode() == Instruction::Mul)
 103             return I;
 104         }
 105         return nullptr;
 106       };
 107
 108       auto InsertMul = [this](Instruction *I) {
 109         Value *LHS = cast<Instruction>(I->getOperand(0))->getOperand(0);
 110         Value *RHS = cast<Instruction>(I->getOperand(1))->getOperand(0);
 111         Muls.push_back(std::make_unique<MulCandidate>(I, LHS, RHS));
 112       };
 113
 114       for (auto *Add : Adds) {
 115         if (Add == Acc)
 116           continue;
 117         if (auto *Mul = GetMulOperand(Add->getOperand(0)))
 118           InsertMul(Mul);
 119         if (auto *Mul = GetMulOperand(Add->getOperand(1)))
 120           InsertMul(Mul);
 121       }
 122     }
 123
 124     /// Add the incoming accumulator value, returns true if a value had not
 125     /// already been added. Returning false signals to the user that this
 126     /// reduction already has a value to initialise the accumulator.
 127     bool InsertAcc(Value *V) {
 128       if (Acc)
 129         return false;
 130       Acc = V;
 131       return true;
 132     }
 133
 134     /// Set two MulCandidates, rooted at muls, that can be executed as a single
 135     /// parallel operation.
 136     void AddMulPair(MulCandidate *Mul0, MulCandidate *Mul1,
 137                     bool Exchange = false) {
 138       LLVM_DEBUG(dbgs() << "Pairing:\n"
 139                  << *Mul0->Root << "\n"
 140                  << *Mul1->Root << "\n");
 141       Mul0->Paired = true;
 142       Mul1->Paired = true;
 143       if (Exchange)
 144         Mul1->Exchange = true;
 145       MulPairs.push_back(std::make_pair(Mul0, Mul1));
 146     }
 147
 148     /// Return true if enough mul operations are found that can be executed in
 149     /// parallel.
 150     bool CreateParallelPairs();
 151
 152     /// Return the add instruction which is the root of the reduction.
 153     Instruction *getRoot() { return Root; }
 154
 155     bool is64Bit() const { return Root->getType()->isIntegerTy(64); }
 156
 157     /// Return the incoming value to be accumulated. This maybe null.
 158     Value *getAccumulator() { return Acc; }
 159
 160     /// Return the set of adds that comprise the reduction.
 161     SetVector<Instruction*> &getAdds() { return Adds; }
 162
 163     /// Return the MulCandidate, rooted at mul instruction, that comprise the
 164     /// the reduction.
 165     MulCandList &getMuls() { return Muls; }
 166
 167     /// Return the MulCandidate, rooted at mul instructions, that have been
 168     /// paired for parallel execution.
 169     MulPairList &getMulPairs() { return MulPairs; }
 170
 171     /// To finalise, replace the uses of the root with the intrinsic call.
 172     void UpdateRoot(Instruction *SMLAD) {
 173       Root->replaceAllUsesWith(SMLAD);
 174     }
 175
 176     void dump() {
 177       LLVM_DEBUG(dbgs() << "Reduction:\n";
 178         for (auto *Add : Adds)
 179           LLVM_DEBUG(dbgs() << *Add << "\n");
 180         for (auto &Mul : Muls)
 181           LLVM_DEBUG(dbgs() << *Mul->Root << "\n"
 182                      << "  " << *Mul->LHS << "\n"
 183                      << "  " << *Mul->RHS << "\n");
 184         LLVM_DEBUG(if (Acc) dbgs() << "Acc in: " << *Acc << "\n")
 185       );
 186     }
 187   };
 188
 189   class WidenedLoad {
 190     LoadInst *NewLd = nullptr;
 191     SmallVector<LoadInst*, 4> Loads;
 192
 193   public:
 194     WidenedLoad(SmallVectorImpl<LoadInst*> &Lds, LoadInst *Wide)
 195       : NewLd(Wide) {
 196       for (auto *I : Lds)
 197         Loads.push_back(I);
 198     }
 199     LoadInst *getLoad() {
 200       return NewLd;
 201     }
 202   };
 203
 204   class ARMParallelDSP : public FunctionPass {
 205     ScalarEvolution   *SE;
 206     AliasAnalysis     *AA;
 207     TargetLibraryInfo *TLI;
 208     DominatorTree     *DT;
 209     const DataLayout  *DL;
 210     Module            *M;
 211     std::map<LoadInst*, LoadInst*> LoadPairs;
 212     SmallPtrSet<LoadInst*, 4> OffsetLoads;
 213     std::map<LoadInst*, std::unique_ptr<WidenedLoad>> WideLoads;
 214
 215     template<unsigned>
 216     bool IsNarrowSequence(Value *V);
 217     bool Search(Value *V, BasicBlock *BB, Reduction &R);
 218     bool RecordMemoryOps(BasicBlock *BB);
 219     void InsertParallelMACs(Reduction &Reduction);
 220     bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
 221     LoadInst* CreateWideLoad(MemInstList &Loads, IntegerType *LoadTy);
 222     bool CreateParallelPairs(Reduction &R);
 223
 224     /// Try to match and generate: SMLAD, SMLADX - Signed Multiply Accumulate
 225     /// Dual performs two signed 16x16-bit multiplications. It adds the
 226     /// products to a 32-bit accumulate operand. Optionally, the instruction can
 227     /// exchange the halfwords of the second operand before performing the
 228     /// arithmetic.
 229     bool MatchSMLAD(Function &F);
 230
 231   public:
 232     static char ID;
 233
 234     ARMParallelDSP() : FunctionPass(ID) { }
 235
 236     void getAnalysisUsage(AnalysisUsage &AU) const override {
 237       FunctionPass::getAnalysisUsage(AU);
 238       AU.addRequired<AssumptionCacheTracker>();
 239       AU.addRequired<ScalarEvolutionWrapperPass>();
 240       AU.addRequired<AAResultsWrapperPass>();
 241       AU.addRequired<TargetLibraryInfoWrapperPass>();
 242       AU.addRequired<DominatorTreeWrapperPass>();
 243       AU.addRequired<TargetPassConfig>();
 244       AU.addPreserved<ScalarEvolutionWrapperPass>();
 245       AU.addPreserved<GlobalsAAWrapperPass>();
 246       AU.setPreservesCFG();
 247     }
 248
 249     bool runOnFunction(Function &F) override {
 250       if (DisableParallelDSP)
 251         return false;
 252       if (skipFunction(F))
 253         return false;
 254
 255       SE = &getAnalysis<ScalarEvolutionWrapperPass>().getSE();
 256       AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
 257       TLI = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI();
 258       DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
 259       auto &TPC = getAnalysis<TargetPassConfig>();
 260
 261       M = F.getParent();
 262       DL = &M->getDataLayout();
 263
 264       auto &TM = TPC.getTM<TargetMachine>();
 265       auto *ST = &TM.getSubtarget<ARMSubtarget>(F);
 266
 267       if (!ST->allowsUnalignedMem()) {
 268         LLVM_DEBUG(dbgs() << "Unaligned memory access not supported: not "
 269                              "running pass ARMParallelDSP\n");
 270         return false;
 271       }
 272
 273       if (!ST->hasDSP()) {
 274         LLVM_DEBUG(dbgs() << "DSP extension not enabled: not running pass "
 275                              "ARMParallelDSP\n");
 276         return false;
 277       }
 278
 279       if (!ST->isLittle()) {
 280         LLVM_DEBUG(dbgs() << "Only supporting little endian: not running pass "
 281                           << "ARMParallelDSP\n");
 282         return false;
 283       }
 284
 285       LLVM_DEBUG(dbgs() << "\n== Parallel DSP pass ==\n");
 286       LLVM_DEBUG(dbgs() << " - " << F.getName() << "\n\n");
 287
 288       bool Changes = MatchSMLAD(F);
 289       return Changes;
 290     }
 291   };
 292 }
 293
 294 template<typename MemInst>
 295 static bool AreSequentialAccesses(MemInst *MemOp0, MemInst *MemOp1,
 296                                   const DataLayout &DL, ScalarEvolution &SE) {
 297   if (isConsecutiveAccess(MemOp0, MemOp1, DL, SE))
 298     return true;
 299   return false;
 300 }
 301
 302 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1,
 303                                         MemInstList &VecMem) {
 304   if (!Ld0 || !Ld1)
 305     return false;
 306
 307   if (!LoadPairs.count(Ld0) || LoadPairs[Ld0] != Ld1)
 308     return false;
 309
 310   LLVM_DEBUG(dbgs() << "Loads are sequential and valid:\n";
 311     dbgs() << "Ld0:"; Ld0->dump();
 312     dbgs() << "Ld1:"; Ld1->dump();
 313   );
 314
 315   VecMem.clear();
 316   VecMem.push_back(Ld0);
 317   VecMem.push_back(Ld1);
 318   return true;
 319 }
 320
 321 // MaxBitwidth: the maximum supported bitwidth of the elements in the DSP
 322 // instructions, which is set to 16. So here we should collect all i8 and i16
 323 // narrow operations.
 324 // TODO: we currently only collect i16, and will support i8 later, so that's
 325 // why we check that types are equal to MaxBitWidth, and not <= MaxBitWidth.
 326 template<unsigned MaxBitWidth>
 327 bool ARMParallelDSP::IsNarrowSequence(Value *V) {
 328   if (auto *SExt = dyn_cast<SExtInst>(V)) {
 329     if (SExt->getSrcTy()->getIntegerBitWidth() != MaxBitWidth)
 330       return false;
 331
 332     if (auto *Ld = dyn_cast<LoadInst>(SExt->getOperand(0))) {
 333       // Check that this load could be paired.
 334       return LoadPairs.count(Ld) || OffsetLoads.count(Ld);
 335     }
 336   }
 337   return false;
 338 }
 339
 340 /// Iterate through the block and record base, offset pairs of loads which can
 341 /// be widened into a single load.
 342 bool ARMParallelDSP::RecordMemoryOps(BasicBlock *BB) {
 343   SmallVector<LoadInst*, 8> Loads;
 344   SmallVector<Instruction*, 8> Writes;
 345   LoadPairs.clear();
 346   WideLoads.clear();
 347
 348   // Collect loads and instruction that may write to memory. For now we only
 349   // record loads which are simple, sign-extended and have a single user.
 350   // TODO: Allow zero-extended loads.
 351   for (auto &I : *BB) {
 352     if (I.mayWriteToMemory())
 353       Writes.push_back(&I);
 354     auto *Ld = dyn_cast<LoadInst>(&I);
 355     if (!Ld || !Ld->isSimple() ||
 356         !Ld->hasOneUse() || !isa<SExtInst>(Ld->user_back()))
 357       continue;
 358     Loads.push_back(Ld);
 359   }
 360
 361   using InstSet = std::set<Instruction*>;
 362   using DepMap = std::map<Instruction*, InstSet>;
 363   DepMap RAWDeps;
 364
 365   // Record any writes that may alias a load.
 366   const auto Size = LocationSize::unknown();
 367   for (auto Read : Loads) {
 368     for (auto Write : Writes) {
 369       MemoryLocation ReadLoc =
 370         MemoryLocation(Read->getPointerOperand(), Size);
 371
 372       if (!isModOrRefSet(intersectModRef(AA->getModRefInfo(Write, ReadLoc),
 373           ModRefInfo::ModRef)))
 374         continue;
 375       if (DT->dominates(Write, Read))
 376         RAWDeps[Read].insert(Write);
 377     }
 378   }
 379
 380   // Check whether there's not a write between the two loads which would
 381   // prevent them from being safely merged.
 382   auto SafeToPair = [&](LoadInst *Base, LoadInst *Offset) {
 383     LoadInst *Dominator = DT->dominates(Base, Offset) ? Base : Offset;
 384     LoadInst *Dominated = DT->dominates(Base, Offset) ? Offset : Base;
 385
 386     if (RAWDeps.count(Dominated)) {
 387       InstSet &WritesBefore = RAWDeps[Dominated];
 388
 389       for (auto Before : WritesBefore) {
 390         // We can't move the second load backward, past a write, to merge
 391         // with the first load.
 392         if (DT->dominates(Dominator, Before))
 393           return false;
 394       }
 395     }
 396     return true;
 397   };
 398
 399   // Record base, offset load pairs.
 400   for (auto *Base : Loads) {
 401     for (auto *Offset : Loads) {
 402       if (Base == Offset)
 403         continue;
 404
 405       if (AreSequentialAccesses<LoadInst>(Base, Offset, *DL, *SE) &&
 406           SafeToPair(Base, Offset)) {
 407         LoadPairs[Base] = Offset;
 408         OffsetLoads.insert(Offset);
 409         break;
 410       }
 411     }
 412   }
 413
 414   LLVM_DEBUG(if (!LoadPairs.empty()) {
 415                dbgs() << "Consecutive load pairs:\n";
 416                for (auto &MapIt : LoadPairs) {
 417                  LLVM_DEBUG(dbgs() << *MapIt.first << ", "
 418                             << *MapIt.second << "\n");
 419                }
 420              });
 421   return LoadPairs.size() > 1;
 422 }
 423
 424 // Search recursively back through the operands to find a tree of values that
 425 // form a multiply-accumulate chain. The search records the Add and Mul
 426 // instructions that form the reduction and allows us to find a single value
 427 // to be used as the initial input to the accumlator.
 428 bool ARMParallelDSP::Search(Value *V, BasicBlock *BB, Reduction &R) {
 429   // If we find a non-instruction, try to use it as the initial accumulator
 430   // value. This may have already been found during the search in which case
 431   // this function will return false, signaling a search fail.
 432   auto *I = dyn_cast<Instruction>(V);
 433   if (!I)
 434     return R.InsertAcc(V);
 435
 436   if (I->getParent() != BB)
 437     return false;
 438
 439   switch (I->getOpcode()) {
 440   default:
 441     break;
 442   case Instruction::PHI:
 443     // Could be the accumulator value.
 444     return R.InsertAcc(V);
 445   case Instruction::Add: {
 446     // Adds should be adding together two muls, or another add and a mul to
 447     // be within the mac chain. One of the operands may also be the
 448     // accumulator value at which point we should stop searching.
 449     R.InsertAdd(I);
 450     Value *LHS = I->getOperand(0);
 451     Value *RHS = I->getOperand(1);
 452     bool ValidLHS = Search(LHS, BB, R);
 453     bool ValidRHS = Search(RHS, BB, R);
 454
 455     if (ValidLHS && ValidRHS)
 456       return true;
 457
 458     return R.InsertAcc(I);
 459   }
 460   case Instruction::Mul: {
 461     Value *MulOp0 = I->getOperand(0);
 462     Value *MulOp1 = I->getOperand(1);
 463     return IsNarrowSequence<16>(MulOp0) && IsNarrowSequence<16>(MulOp1);
 464   }
 465   case Instruction::SExt:
 466     return Search(I->getOperand(0), BB, R);
 467   }
 468   return false;
 469 }
 470
 471 // The pass needs to identify integer add/sub reductions of 16-bit vector
 472 // multiplications.
 473 // To use SMLAD:
 474 // 1) we first need to find integer add then look for this pattern:
 475 //
 476 // acc0 = ...
 477 // ld0 = load i16
 478 // sext0 = sext i16 %ld0 to i32
 479 // ld1 = load i16
 480 // sext1 = sext i16 %ld1 to i32
 481 // mul0 = mul %sext0, %sext1
 482 // ld2 = load i16
 483 // sext2 = sext i16 %ld2 to i32
 484 // ld3 = load i16
 485 // sext3 = sext i16 %ld3 to i32
 486 // mul1 = mul i32 %sext2, %sext3
 487 // add0 = add i32 %mul0, %acc0
 488 // acc1 = add i32 %add0, %mul1
 489 //
 490 // Which can be selected to:
 491 //
 492 // ldr r0
 493 // ldr r1
 494 // smlad r2, r0, r1, r2
 495 //
 496 // If constants are used instead of loads, these will need to be hoisted
 497 // out and into a register.
 498 //
 499 // If loop invariants are used instead of loads, these need to be packed
 500 // before the loop begins.
 501 //
 502 bool ARMParallelDSP::MatchSMLAD(Function &F) {
 503   bool Changed = false;
 504
 505   for (auto &BB : F) {
 506     SmallPtrSet<Instruction*, 4> AllAdds;
 507     if (!RecordMemoryOps(&BB))
 508       continue;
 509
 510     for (Instruction &I : reverse(BB)) {
 511       if (I.getOpcode() != Instruction::Add)
 512         continue;
 513
 514       if (AllAdds.count(&I))
 515         continue;
 516
 517       const auto *Ty = I.getType();
 518       if (!Ty->isIntegerTy(32) && !Ty->isIntegerTy(64))
 519         continue;
 520
 521       Reduction R(&I);
 522       if (!Search(&I, &BB, R))
 523         continue;
 524
 525       R.InsertMuls();
 526       LLVM_DEBUG(dbgs() << "After search, Reduction:\n"; R.dump());
 527
 528       if (!CreateParallelPairs(R))
 529         continue;
 530
 531       InsertParallelMACs(R);
 532       Changed = true;
 533       AllAdds.insert(R.getAdds().begin(), R.getAdds().end());
 534     }
 535   }
 536
 537   return Changed;
 538 }
 539
 540 bool ARMParallelDSP::CreateParallelPairs(Reduction &R) {
 541
 542   // Not enough mul operations to make a pair.
 543   if (R.getMuls().size() < 2)
 544     return false;
 545
 546   // Check that the muls operate directly upon sign extended loads.
 547   for (auto &MulCand : R.getMuls()) {
 548     if (!MulCand->HasTwoLoadInputs())
 549       return false;
 550   }
 551
 552   auto CanPair = [&](Reduction &R, MulCandidate *PMul0, MulCandidate *PMul1) {
 553     // The first elements of each vector should be loads with sexts. If we
 554     // find that its two pairs of consecutive loads, then these can be
 555     // transformed into two wider loads and the users can be replaced with
 556     // DSP intrinsics.
 557     auto Ld0 = static_cast<LoadInst*>(PMul0->LHS);
 558     auto Ld1 = static_cast<LoadInst*>(PMul1->LHS);
 559     auto Ld2 = static_cast<LoadInst*>(PMul0->RHS);
 560     auto Ld3 = static_cast<LoadInst*>(PMul1->RHS);
 561
 562     if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd)) {
 563       if (AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) {
 564         LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n");
 565         R.AddMulPair(PMul0, PMul1);
 566         return true;
 567       } else if (AreSequentialLoads(Ld3, Ld2, PMul1->VecLd)) {
 568         LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n");
 569         LLVM_DEBUG(dbgs() << "    exchanging Ld2 and Ld3\n");
 570         R.AddMulPair(PMul0, PMul1, true);
 571         return true;
 572       }
 573     } else if (AreSequentialLoads(Ld1, Ld0, PMul0->VecLd) &&
 574                AreSequentialLoads(Ld2, Ld3, PMul1->VecLd)) {
 575       LLVM_DEBUG(dbgs() << "OK: found two pairs of parallel loads!\n");
 576       LLVM_DEBUG(dbgs() << "    exchanging Ld0 and Ld1\n");
 577       LLVM_DEBUG(dbgs() << "    and swapping muls\n");
 578       // Only the second operand can be exchanged, so swap the muls.
 579       R.AddMulPair(PMul1, PMul0, true);
 580       return true;
 581     }
 582     return false;
 583   };
 584
 585   MulCandList &Muls = R.getMuls();
 586   const unsigned Elems = Muls.size();
 587   for (unsigned i = 0; i < Elems; ++i) {
 588     MulCandidate *PMul0 = static_cast<MulCandidate*>(Muls[i].get());
 589     if (PMul0->Paired)
 590       continue;
 591
 592     for (unsigned j = 0; j < Elems; ++j) {
 593       if (i == j)
 594         continue;
 595
 596       MulCandidate *PMul1 = static_cast<MulCandidate*>(Muls[j].get());
 597       if (PMul1->Paired)
 598         continue;
 599
 600       const Instruction *Mul0 = PMul0->Root;
 601       const Instruction *Mul1 = PMul1->Root;
 602       if (Mul0 == Mul1)
 603         continue;
 604
 605       assert(PMul0 != PMul1 && "expected different chains");
 606
 607       if (CanPair(R, PMul0, PMul1))
 608         break;
 609     }
 610   }
 611   return !R.getMulPairs().empty();
 612 }
 613
 614
 615 void ARMParallelDSP::InsertParallelMACs(Reduction &R) {
 616
 617   auto CreateSMLAD = [&](LoadInst* WideLd0, LoadInst *WideLd1,
 618                          Value *Acc, bool Exchange,
 619                          Instruction *InsertAfter) {
 620     // Replace the reduction chain with an intrinsic call
 621
 622     Value* Args[] = { WideLd0, WideLd1, Acc };
 623     Function *SMLAD = nullptr;
 624     if (Exchange)
 625       SMLAD = Acc->getType()->isIntegerTy(32) ?
 626         Intrinsic::getDeclaration(M, Intrinsic::arm_smladx) :
 627         Intrinsic::getDeclaration(M, Intrinsic::arm_smlaldx);
 628     else
 629       SMLAD = Acc->getType()->isIntegerTy(32) ?
 630         Intrinsic::getDeclaration(M, Intrinsic::arm_smlad) :
 631         Intrinsic::getDeclaration(M, Intrinsic::arm_smlald);
 632
 633     IRBuilder<NoFolder> Builder(InsertAfter->getParent(),
 634                                 ++BasicBlock::iterator(InsertAfter));
 635     Instruction *Call = Builder.CreateCall(SMLAD, Args);
 636     NumSMLAD++;
 637     return Call;
 638   };
 639
 640   Instruction *InsertAfter = R.getRoot();
 641   Value *Acc = R.getAccumulator();
 642
 643   // For any muls that were discovered but not paired, accumulate their values
 644   // as before.
 645   IRBuilder<NoFolder> Builder(InsertAfter->getParent(),
 646                               ++BasicBlock::iterator(InsertAfter));
 647   MulCandList &MulCands = R.getMuls();
 648   for (auto &MulCand : MulCands) {
 649     if (MulCand->Paired)
 650       continue;
 651
 652     Value *Mul = MulCand->Root;
 653     LLVM_DEBUG(dbgs() << "Accumulating unpaired mul: " << *Mul << "\n");
 654
 655     if (R.getRoot()->getType() != Mul->getType()) {
 656       assert(R.is64Bit() && "expected 64-bit result");
 657       Mul = Builder.CreateSExt(Mul, R.getRoot()->getType());
 658     }
 659
 660     if (!Acc) {
 661       Acc = Mul;
 662       continue;
 663     }
 664
 665     Acc = Builder.CreateAdd(Mul, Acc);
 666     InsertAfter = cast<Instruction>(Acc);
 667   }
 668
 669   if (!Acc)
 670     Acc = R.is64Bit() ?
 671       ConstantInt::get(IntegerType::get(M->getContext(), 64), 0) :
 672       ConstantInt::get(IntegerType::get(M->getContext(), 32), 0);
 673
 674   IntegerType *Ty = IntegerType::get(M->getContext(), 32);
 675   for (auto &Pair : R.getMulPairs()) {
 676     MulCandidate *LHSMul = Pair.first;
 677     MulCandidate *RHSMul = Pair.second;
 678     LoadInst *BaseLHS = LHSMul->getBaseLoad();
 679     LoadInst *BaseRHS = RHSMul->getBaseLoad();
 680     LoadInst *WideLHS = WideLoads.count(BaseLHS) ?
 681       WideLoads[BaseLHS]->getLoad() : CreateWideLoad(LHSMul->VecLd, Ty);
 682     LoadInst *WideRHS = WideLoads.count(BaseRHS) ?
 683       WideLoads[BaseRHS]->getLoad() : CreateWideLoad(RHSMul->VecLd, Ty);
 684
 685     Acc = CreateSMLAD(WideLHS, WideRHS, Acc, RHSMul->Exchange, InsertAfter);
 686     InsertAfter = cast<Instruction>(Acc);
 687   }
 688   R.UpdateRoot(cast<Instruction>(Acc));
 689 }
 690
 691 LoadInst* ARMParallelDSP::CreateWideLoad(MemInstList &Loads,
 692                                          IntegerType *LoadTy) {
 693   assert(Loads.size() == 2 && "currently only support widening two loads");
 694
 695   LoadInst *Base = Loads[0];
 696   LoadInst *Offset = Loads[1];
 697
 698   Instruction *BaseSExt = dyn_cast<SExtInst>(Base->user_back());
 699   Instruction *OffsetSExt = dyn_cast<SExtInst>(Offset->user_back());
 700
 701   assert((BaseSExt && OffsetSExt)
 702          && "Loads should have a single, extending, user");
 703
 704   std::function<void(Value*, Value*)> MoveBefore =
 705     [&](Value *A, Value *B) -> void {
 706       if (!isa<Instruction>(A) || !isa<Instruction>(B))
 707         return;
 708
 709       auto *Source = cast<Instruction>(A);
 710       auto *Sink = cast<Instruction>(B);
 711
 712       if (DT->dominates(Source, Sink) ||
 713           Source->getParent() != Sink->getParent() ||
 714           isa<PHINode>(Source) || isa<PHINode>(Sink))
 715         return;
 716
 717       Source->moveBefore(Sink);
 718       for (auto &Op : Source->operands())
 719         MoveBefore(Op, Source);
 720     };
 721
 722   // Insert the load at the point of the original dominating load.
 723   LoadInst *DomLoad = DT->dominates(Base, Offset) ? Base : Offset;
 724   IRBuilder<NoFolder> IRB(DomLoad->getParent(),
 725                           ++BasicBlock::iterator(DomLoad));
 726
 727   // Bitcast the pointer to a wider type and create the wide load, while making
 728   // sure to maintain the original alignment as this prevents ldrd from being
 729   // generated when it could be illegal due to memory alignment.
 730   const unsigned AddrSpace = DomLoad->getPointerAddressSpace();
 731   Value *VecPtr = IRB.CreateBitCast(Base->getPointerOperand(),
 732                                     LoadTy->getPointerTo(AddrSpace));
 733   LoadInst *WideLoad = IRB.CreateAlignedLoad(LoadTy, VecPtr,
 734                                              Base->getAlignment());
 735
 736   // Make sure everything is in the correct order in the basic block.
 737   MoveBefore(Base->getPointerOperand(), VecPtr);
 738   MoveBefore(VecPtr, WideLoad);
 739
 740   // From the wide load, create two values that equal the original two loads.
 741   // Loads[0] needs trunc while Loads[1] needs a lshr and trunc.
 742   // TODO: Support big-endian as well.
 743   Value *Bottom = IRB.CreateTrunc(WideLoad, Base->getType());
 744   Value *NewBaseSExt = IRB.CreateSExt(Bottom, BaseSExt->getType());
 745   BaseSExt->replaceAllUsesWith(NewBaseSExt);
 746
 747   IntegerType *OffsetTy = cast<IntegerType>(Offset->getType());
 748   Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth());
 749   Value *Top = IRB.CreateLShr(WideLoad, ShiftVal);
 750   Value *Trunc = IRB.CreateTrunc(Top, OffsetTy);
 751   Value *NewOffsetSExt = IRB.CreateSExt(Trunc, OffsetSExt->getType());
 752   OffsetSExt->replaceAllUsesWith(NewOffsetSExt);
 753
 754   LLVM_DEBUG(dbgs() << "From Base and Offset:\n"
 755              << *Base << "\n" << *Offset << "\n"
 756              << "Created Wide Load:\n"
 757              << *WideLoad << "\n"
 758              << *Bottom << "\n"
 759              << *NewBaseSExt << "\n"
 760              << *Top << "\n"
 761              << *Trunc << "\n"
 762              << *NewOffsetSExt << "\n");
 763   WideLoads.emplace(std::make_pair(Base,
 764                                    std::make_unique<WidenedLoad>(Loads, WideLoad)));
 765   return WideLoad;
 766 }
 767
 768 Pass *llvm::createARMParallelDSPPass() {
 769   return new ARMParallelDSP();
 770 }
 771
 772 char ARMParallelDSP::ID = 0;
 773
 774 INITIALIZE_PASS_BEGIN(ARMParallelDSP, "arm-parallel-dsp",
 775                 "Transform functions to use DSP intrinsics", false, false)
 776 INITIALIZE_PASS_END(ARMParallelDSP, "arm-parallel-dsp",
 777                 "Transform functions to use DSP intrinsics", false, false)