lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h

   1 //===-- ARMFixupKinds.h - ARM Specific Fixup Entries ------------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8
   9 #ifndef LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
  10 #define LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMFIXUPKINDS_H
  11
  12 #include "llvm/MC/MCFixup.h"
  13
  14 namespace llvm {
  15 namespace ARM {
  16 enum Fixups {
  17   // 12-bit PC relative relocation for symbol addresses
  18   fixup_arm_ldst_pcrel_12 = FirstTargetFixupKind,
  19
  20   // Equivalent to fixup_arm_ldst_pcrel_12, with the 16-bit halfwords reordered.
  21   fixup_t2_ldst_pcrel_12,
  22
  23   // 10-bit PC relative relocation for symbol addresses used in
  24   // LDRD/LDRH/LDRB/etc. instructions. All bits are encoded.
  25   fixup_arm_pcrel_10_unscaled,
  26   // 10-bit PC relative relocation for symbol addresses used in VFP instructions
  27   // where the lower 2 bits are not encoded (so it's encoded as an 8-bit
  28   // immediate).
  29   fixup_arm_pcrel_10,
  30   // Equivalent to fixup_arm_pcrel_10, accounting for the short-swapped encoding
  31   // of Thumb2 instructions.
  32   fixup_t2_pcrel_10,
  33   // 9-bit PC relative relocation for symbol addresses used in VFP instructions
  34   // where bit 0 not encoded (so it's encoded as an 8-bit immediate).
  35   fixup_arm_pcrel_9,
  36   // Equivalent to fixup_arm_pcrel_9, accounting for the short-swapped encoding
  37   // of Thumb2 instructions.
  38   fixup_t2_pcrel_9,
  39   // 10-bit PC relative relocation for symbol addresses where the lower 2 bits
  40   // are not encoded (so it's encoded as an 8-bit immediate).
  41   fixup_thumb_adr_pcrel_10,
  42   // 12-bit PC relative relocation for the ADR instruction.
  43   fixup_arm_adr_pcrel_12,
  44   // 12-bit PC relative relocation for the ADR instruction.
  45   fixup_t2_adr_pcrel_12,
  46   // 24-bit PC relative relocation for conditional branch instructions.
  47   fixup_arm_condbranch,
  48   // 24-bit PC relative relocation for branch instructions. (unconditional)
  49   fixup_arm_uncondbranch,
  50   // 20-bit PC relative relocation for Thumb2 direct uconditional branch
  51   // instructions.
  52   fixup_t2_condbranch,
  53   // 20-bit PC relative relocation for Thumb2 direct branch unconditional branch
  54   // instructions.
  55   fixup_t2_uncondbranch,
  56
  57   // 12-bit fixup for Thumb B instructions.
  58   fixup_arm_thumb_br,
  59
  60   // The following fixups handle the ARM BL instructions. These can be
  61   // conditionalised; however, the ARM ELF ABI requires a different relocation
  62   // in that case: R_ARM_JUMP24 instead of R_ARM_CALL. The difference is that
  63   // R_ARM_CALL is allowed to change the instruction to a BLX inline, which has
  64   // no conditional version; R_ARM_JUMP24 would have to insert a veneer.
  65   //
  66   // MachO does not draw a distinction between the two cases, so it will treat
  67   // fixup_arm_uncondbl and fixup_arm_condbl as identical fixups.
  68
  69   // Fixup for unconditional ARM BL instructions.
  70   fixup_arm_uncondbl,
  71
  72   // Fixup for ARM BL instructions with nontrivial conditionalisation.
  73   fixup_arm_condbl,
  74
  75   // Fixup for ARM BLX instructions.
  76   fixup_arm_blx,
  77
  78   // Fixup for Thumb BL instructions.
  79   fixup_arm_thumb_bl,
  80
  81   // Fixup for Thumb BLX instructions.
  82   fixup_arm_thumb_blx,
  83
  84   // Fixup for Thumb branch instructions.
  85   fixup_arm_thumb_cb,
  86
  87   // Fixup for Thumb load/store from constant pool instrs.
  88   fixup_arm_thumb_cp,
  89
  90   // Fixup for Thumb conditional branching instructions.
  91   fixup_arm_thumb_bcc,
  92
  93   // The next two are for the movt/movw pair
  94   // the 16bit imm field are split into imm{15-12} and imm{11-0}
  95   fixup_arm_movt_hi16, // :upper16:
  96   fixup_arm_movw_lo16, // :lower16:
  97   fixup_t2_movt_hi16,  // :upper16:
  98   fixup_t2_movw_lo16,  // :lower16:
  99
 100   // Fixup for mod_imm
 101   fixup_arm_mod_imm,
 102
 103   // Fixup for Thumb2 8-bit rotated operand
 104   fixup_t2_so_imm,
 105
 106   // Fixups for Branch Future.
 107   fixup_bf_branch,
 108   fixup_bf_target,
 109   fixup_bfl_target,
 110   fixup_bfc_target,
 111   fixup_bfcsel_else_target,
 112   fixup_wls,
 113   fixup_le,
 114
 115   // Marker
 116   LastTargetFixupKind,
 117   NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
 118 };
 119 }
 120 } // namespace llvm
 121
 122 #endif