lib/Target/ARM/MCTargetDesc/ARMUnwindOpAsm.cpp

   1 //===-- ARMUnwindOpAsm.cpp - ARM Unwind Opcodes Assembler -------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file implements the unwind opcode assmebler for ARM exception handling
  10 // table.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "ARMUnwindOpAsm.h"
  15 #include "llvm/Support/ARMEHABI.h"
  16 #include "llvm/Support/LEB128.h"
  17 #include "llvm/Support/MathExtras.h"
  18 #include <cassert>
  19
  20 using namespace llvm;
  21
  22 namespace {
  23
  24   /// UnwindOpcodeStreamer - The simple wrapper over SmallVector to emit bytes
  25   /// with MSB to LSB per uint32_t ordering.  For example, the first byte will
  26   /// be placed in Vec[3], and the following bytes will be placed in 2, 1, 0,
  27   /// 7, 6, 5, 4, 11, 10, 9, 8, and so on.
  28   class UnwindOpcodeStreamer {
  29   private:
  30     SmallVectorImpl<uint8_t> &Vec;
  31     size_t Pos = 3;
  32
  33   public:
  34     UnwindOpcodeStreamer(SmallVectorImpl<uint8_t> &V) : Vec(V) {}
  35
  36     /// Emit the byte in MSB to LSB per uint32_t order.
  37     void EmitByte(uint8_t elem) {
  38       Vec[Pos] = elem;
  39       Pos = (((Pos ^ 0x3u) + 1) ^ 0x3u);
  40     }
  41
  42     /// Emit the size prefix.
  43     void EmitSize(size_t Size) {
  44       size_t SizeInWords = (Size + 3) / 4;
  45       assert(SizeInWords <= 0x100u &&
  46              "Only 256 additional words are allowed for unwind opcodes");
  47       EmitByte(static_cast<uint8_t>(SizeInWords - 1));
  48     }
  49
  50     /// Emit the personality index prefix.
  51     void EmitPersonalityIndex(unsigned PI) {
  52       assert(PI < ARM::EHABI::NUM_PERSONALITY_INDEX &&
  53              "Invalid personality prefix");
  54       EmitByte(ARM::EHABI::EHT_COMPACT | PI);
  55     }
  56
  57     /// Fill the rest of bytes with FINISH opcode.
  58     void FillFinishOpcode() {
  59       while (Pos < Vec.size())
  60         EmitByte(ARM::EHABI::UNWIND_OPCODE_FINISH);
  61     }
  62   };
  63
  64 } // end anonymous namespace
  65
  66 void UnwindOpcodeAssembler::EmitRegSave(uint32_t RegSave) {
  67   if (RegSave == 0u)
  68     return;
  69
  70   // One byte opcode to save register r14 and r11-r4
  71   if (RegSave & (1u << 4)) {
  72     // The one byte opcode will always save r4, thus we can't use the one byte
  73     // opcode when r4 is not in .save directive.
  74
  75     // Compute the consecutive registers from r4 to r11.
  76     uint32_t Mask = RegSave & 0xff0u;
  77     uint32_t Range = countTrailingOnes(Mask >> 5); // Exclude r4.
  78     // Mask off non-consecutive registers. Keep r4.
  79     Mask &= ~(0xffffffe0u << Range);
  80
  81     // Emit this opcode when the mask covers every registers.
  82     uint32_t UnmaskedReg = RegSave & 0xfff0u & (~Mask);
  83     if (UnmaskedReg == 0u) {
  84       // Pop r[4 : (4 + n)]
  85       EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4 | Range);
  86       RegSave &= 0x000fu;
  87     } else if (UnmaskedReg == (1u << 14)) {
  88       // Pop r[14] + r[4 : (4 + n)]
  89       EmitInt8(ARM::EHABI::UNWIND_OPCODE_POP_REG_RANGE_R4_R14 | Range);
  90       RegSave &= 0x000fu;
  91     }
  92   }
  93
  94   // Two bytes opcode to save register r15-r4
  95   if ((RegSave & 0xfff0u) != 0)
  96     EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK_R4 | (RegSave >> 4));
  97
  98   // Opcode to save register r3-r0
  99   if ((RegSave & 0x000fu) != 0)
 100     EmitInt16(ARM::EHABI::UNWIND_OPCODE_POP_REG_MASK | (RegSave & 0x000fu));
 101 }
 102
 103 /// Emit unwind opcodes for .vsave directives
 104 void UnwindOpcodeAssembler::EmitVFPRegSave(uint32_t VFPRegSave) {
 105   // We only have 4 bits to save the offset in the opcode so look at the lower
 106   // and upper 16 bits separately.
 107   for (uint32_t Regs : {VFPRegSave & 0xffff0000u, VFPRegSave & 0x0000ffffu}) {
 108     while (Regs) {
 109       // Now look for a run of set bits. Remember the MSB and LSB of the run.
 110       auto RangeMSB = 32 - countLeadingZeros(Regs);
 111       auto RangeLen = countLeadingOnes(Regs << (32 - RangeMSB));
 112       auto RangeLSB = RangeMSB - RangeLen;
 113
 114       int Opcode = RangeLSB >= 16
 115                        ? ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD_D16
 116                        : ARM::EHABI::UNWIND_OPCODE_POP_VFP_REG_RANGE_FSTMFDD;
 117
 118       EmitInt16(Opcode | ((RangeLSB % 16) << 4) | (RangeLen - 1));
 119
 120       // Zero out bits we're done with.
 121       Regs &= ~(-1u << RangeLSB);
 122     }
 123   }
 124 }
 125
 126 /// Emit unwind opcodes to copy address from source register to $sp.
 127 void UnwindOpcodeAssembler::EmitSetSP(uint16_t Reg) {
 128   EmitInt8(ARM::EHABI::UNWIND_OPCODE_SET_VSP | Reg);
 129 }
 130
 131 /// Emit unwind opcodes to add $sp with an offset.
 132 void UnwindOpcodeAssembler::EmitSPOffset(int64_t Offset) {
 133   if (Offset > 0x200) {
 134     uint8_t Buff[16];
 135     Buff[0] = ARM::EHABI::UNWIND_OPCODE_INC_VSP_ULEB128;
 136     size_t ULEBSize = encodeULEB128((Offset - 0x204) >> 2, Buff + 1);
 137     EmitBytes(Buff, ULEBSize + 1);
 138   } else if (Offset > 0) {
 139     if (Offset > 0x100) {
 140       EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP | 0x3fu);
 141       Offset -= 0x100;
 142     }
 143     EmitInt8(ARM::EHABI::UNWIND_OPCODE_INC_VSP |
 144              static_cast<uint8_t>((Offset - 4) >> 2));
 145   } else if (Offset < 0) {
 146     while (Offset < -0x100) {
 147       EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP | 0x3fu);
 148       Offset += 0x100;
 149     }
 150     EmitInt8(ARM::EHABI::UNWIND_OPCODE_DEC_VSP |
 151              static_cast<uint8_t>(((-Offset) - 4) >> 2));
 152   }
 153 }
 154
 155 void UnwindOpcodeAssembler::Finalize(unsigned &PersonalityIndex,
 156                                      SmallVectorImpl<uint8_t> &Result) {
 157   UnwindOpcodeStreamer OpStreamer(Result);
 158
 159   if (HasPersonality) {
 160     // User-specifed personality routine: [ SIZE , OP1 , OP2 , ... ]
 161     PersonalityIndex = ARM::EHABI::NUM_PERSONALITY_INDEX;
 162     size_t TotalSize = Ops.size() + 1;
 163     size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
 164     Result.resize(RoundUpSize);
 165     OpStreamer.EmitSize(RoundUpSize);
 166   } else {
 167     // If no personalityindex is specified, select ane
 168     if (PersonalityIndex == ARM::EHABI::NUM_PERSONALITY_INDEX)
 169       PersonalityIndex = (Ops.size() <= 3) ? ARM::EHABI::AEABI_UNWIND_CPP_PR0
 170                                            : ARM::EHABI::AEABI_UNWIND_CPP_PR1;
 171     if (PersonalityIndex == ARM::EHABI::AEABI_UNWIND_CPP_PR0) {
 172       // __aeabi_unwind_cpp_pr0: [ 0x80 , OP1 , OP2 , OP3 ]
 173       assert(Ops.size() <= 3 && "too many opcodes for __aeabi_unwind_cpp_pr0");
 174       Result.resize(4);
 175       OpStreamer.EmitPersonalityIndex(PersonalityIndex);
 176     } else {
 177       // __aeabi_unwind_cpp_pr{1,2}: [ {0x81,0x82} , SIZE , OP1 , OP2 , ... ]
 178       size_t TotalSize = Ops.size() + 2;
 179       size_t RoundUpSize = (TotalSize + 3) / 4 * 4;
 180       Result.resize(RoundUpSize);
 181       OpStreamer.EmitPersonalityIndex(PersonalityIndex);
 182       OpStreamer.EmitSize(RoundUpSize);
 183     }
 184   }
 185
 186   // Copy the unwind opcodes
 187   for (size_t i = OpBegins.size() - 1; i > 0; --i)
 188     for (size_t j = OpBegins[i - 1], end = OpBegins[i]; j < end; ++j)
 189       OpStreamer.EmitByte(Ops[j]);
 190
 191   // Emit the padding finish opcodes if the size is not multiple of 4.
 192   OpStreamer.FillFinishOpcode();
 193
 194   // Reset the assembler state
 195   Reset();
 196 }