lib/Target/PowerPC/PPCScheduleE500.td

   1 //===-- PPCScheduleE500.td - e500 Scheduling Defs ------*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the itinerary class data for the Freescale e500 32-bit
  10 // Power processor.
  11 //
  12 // All information is derived from the "e500 Core Reference Manual",
  13 // Freescale Document Number E500MCRM, Rev. 1, 03/2012.
  14 //
  15 //===----------------------------------------------------------------------===//
  16 // Relevant functional units in the Freescale e500 core:
  17 //
  18 //  * Decode & Dispatch
  19 //    Can dispatch up to 2 instructions per clock cycle to either the GPR Issue
  20 //    queues (GIQx) or Branch issue queue (BIQ).
  21 def E500_DIS0 : FuncUnit; // Dispatch stage - insn 1
  22 def E500_DIS1 : FuncUnit; // Dispatch stage - insn 2
  23
  24 //  * Execute
  25 //    6 pipelined execution units: SU0, SU1, BU, LSU, MU.
  26 //    Some instructions can only execute in SU0 but not SU1.
  27 def E500_SU0  : FuncUnit; // Simple unit 0
  28 def E500_SU1  : FuncUnit; // Simple unit 1
  29 def E500_BU    : FuncUnit; // Branch unit
  30 def E500_MU    : FuncUnit; // MU pipeline
  31 def E500_LSU_0 : FuncUnit; // LSU pipeline
  32
  33 def E500_GPR_Bypass : Bypass;
  34 def E500_CR_Bypass  : Bypass;
  35 def E500_DivBypass  : Bypass;
  36
  37 def PPCE500Itineraries : ProcessorItineraries<
  38   [E500_DIS0, E500_DIS1, E500_SU0, E500_SU1, E500_BU,
  39    E500_MU, E500_LSU_0],
  40   [E500_CR_Bypass, E500_GPR_Bypass, E500_DivBypass], [
  41   InstrItinData<IIC_IntSimple,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  42                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  43                                  [4, 1, 1], // Latency = 1
  44                                  [E500_GPR_Bypass,
  45                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  46   InstrItinData<IIC_IntGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  47                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  48                                  [4, 1, 1], // Latency = 1
  49                                  [E500_GPR_Bypass,
  50                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  51   InstrItinData<IIC_IntISEL,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  52                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  53                                  [4, 1, 1, 1], // Latency = 1
  54                                  [E500_GPR_Bypass,
  55                                   E500_GPR_Bypass, E500_GPR_Bypass,
  56                                   E500_CR_Bypass]>,
  57   InstrItinData<IIC_IntCompare,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  58                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  59                                  [5, 1, 1], // Latency = 1 or 2
  60                                  [E500_CR_Bypass,
  61                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  62   InstrItinData<IIC_IntDivW,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  63                                   InstrStage<1, [E500_MU], 0>,
  64                                   InstrStage<14, [E500_MU]>],
  65                                  [17, 1, 1], // Latency=4..35, Repeat= 4..35
  66                                  [E500_GPR_Bypass,
  67                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  68   InstrItinData<IIC_IntMulHW,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  69                                   InstrStage<4, [E500_MU]>],
  70                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  71                                  [E500_GPR_Bypass,
  72                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  73   InstrItinData<IIC_IntMulHWU,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  74                                   InstrStage<4, [E500_MU]>],
  75                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  76                                  [E500_GPR_Bypass,
  77                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  78   InstrItinData<IIC_IntMulLI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  79                                   InstrStage<4, [E500_MU]>],
  80                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
  81                                  [E500_GPR_Bypass,
  82                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  83   InstrItinData<IIC_IntRotate,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  84                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  85                                  [4, 1, 1], // Latency = 1
  86                                  [E500_GPR_Bypass,
  87                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  88   InstrItinData<IIC_IntShift,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  89                                   InstrStage<1, [E500_SU0, E500_SU1]>],
  90                                  [4, 1, 1], // Latency = 1
  91                                  [E500_GPR_Bypass,
  92                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
  93   InstrItinData<IIC_IntTrapW,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  94                                   InstrStage<2, [E500_SU0]>],
  95                                  [5, 1], // Latency = 2, Repeat rate = 2
  96                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
  97   InstrItinData<IIC_BrB,         [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
  98                                   InstrStage<1, [E500_BU]>],
  99                                  [4, 1], // Latency = 1
 100                                  [NoBypass, E500_GPR_Bypass]>,
 101   InstrItinData<IIC_BrCR,        [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 102                                   InstrStage<1, [E500_BU]>],
 103                                  [4, 1, 1], // Latency = 1
 104                                  [E500_CR_Bypass,
 105                                   E500_CR_Bypass, E500_CR_Bypass]>,
 106   InstrItinData<IIC_BrMCR,       [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 107                                   InstrStage<1, [E500_BU]>],
 108                                  [4, 1], // Latency = 1
 109                                  [E500_CR_Bypass, E500_CR_Bypass]>,
 110   InstrItinData<IIC_BrMCRX,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 111                                   InstrStage<1, [E500_SU0, E500_SU1]>],
 112                                  [4, 1, 1], // Latency = 1
 113                                  [E500_CR_Bypass, E500_GPR_Bypass]>,
 114   InstrItinData<IIC_LdStDCBA,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 115                                   InstrStage<1, [E500_LSU_0]>],
 116                                  [6, 1], // Latency = 3, Repeat rate = 1
 117                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 118   InstrItinData<IIC_LdStDCBF,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 119                                   InstrStage<1, [E500_LSU_0]>],
 120                                  [6, 1], // Latency = 3
 121                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 122   InstrItinData<IIC_LdStDCBI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 123                                   InstrStage<1, [E500_LSU_0]>],
 124                                  [6, 1], // Latency = 3
 125                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 126   InstrItinData<IIC_LdStLoad,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 127                                   InstrStage<1, [E500_LSU_0]>],
 128                                  [6, 1], // Latency = 3
 129                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 130   InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 131                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 132                                   InstrStage<1, [E500_LSU_0]>],
 133                                  [6, 1], // Latency = 3
 134                                  [E500_GPR_Bypass, E500_GPR_Bypass],
 135                                  2>, // 2 micro-ops
 136   InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 137                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 138                                   InstrStage<1, [E500_LSU_0]>],
 139                                  [6, 1], // Latency = 3
 140                                  [E500_GPR_Bypass, E500_GPR_Bypass],
 141                                  2>, // 2 micro-ops
 142   InstrItinData<IIC_LdStStore,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 143                                   InstrStage<1, [E500_LSU_0]>],
 144                                  [6, 1], // Latency = 3
 145                                  [NoBypass, E500_GPR_Bypass]>,
 146   InstrItinData<IIC_LdStSTU,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 147                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 148                                   InstrStage<1, [E500_LSU_0]>],
 149                                  [6, 1], // Latency = 3
 150                                  [NoBypass, E500_GPR_Bypass],
 151                                  2>, // 2 micro-ops
 152   InstrItinData<IIC_LdStSTUX,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 153                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 154                                   InstrStage<1, [E500_LSU_0]>],
 155                                  [6, 1], // Latency = 3
 156                                  [NoBypass, E500_GPR_Bypass],
 157                                  2>, // 2 micro-ops
 158   InstrItinData<IIC_LdStICBI,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 159                                   InstrStage<1, [E500_LSU_0]>],
 160                                  [6, 1], // Latency = 3
 161                                  [NoBypass, E500_GPR_Bypass]>,
 162   InstrItinData<IIC_LdStLHA,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 163                                   InstrStage<1, [E500_LSU_0]>],
 164                                  [6, 1], // Latency = 3
 165                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 166   InstrItinData<IIC_LdStLHAU,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 167                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 168                                   InstrStage<1, [E500_LSU_0]>],
 169                                  [6, 1], // Latency = 3
 170                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 171   InstrItinData<IIC_LdStLHAUX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 172                                   InstrStage<1, [E500_SU0, E500_SU1], 0>,
 173                                   InstrStage<1, [E500_LSU_0]>],
 174                                  [6, 1], // Latency = 3
 175                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 176   InstrItinData<IIC_LdStLMW,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 177                                   InstrStage<1, [E500_LSU_0]>],
 178                                  [7, 1], // Latency = r+3
 179                                  [NoBypass, E500_GPR_Bypass]>,
 180   InstrItinData<IIC_LdStLWARX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 181                                   InstrStage<3, [E500_LSU_0]>],
 182                                  [6, 1, 1], // Latency = 3, Repeat rate = 3
 183                                  [E500_GPR_Bypass,
 184                                   E500_GPR_Bypass, E500_GPR_Bypass]>,
 185   InstrItinData<IIC_LdStSTWCX,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 186                                   InstrStage<1, [E500_LSU_0]>],
 187                                  [6, 1], // Latency = 3
 188                                  [NoBypass, E500_GPR_Bypass]>,
 189   InstrItinData<IIC_LdStSync,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 190                                   InstrStage<1, [E500_LSU_0]>]>,
 191   InstrItinData<IIC_SprMFSR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 192                                   InstrStage<4, [E500_SU0]>],
 193                                  [7, 1],
 194                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 195   InstrItinData<IIC_SprMTMSR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 196                                   InstrStage<2, [E500_SU0, E500_SU1]>],
 197                                  [5, 1], // Latency = 2, Repeat rate = 4
 198                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 199   InstrItinData<IIC_SprMTSR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 200                                   InstrStage<1, [E500_SU0]>],
 201                                  [5, 1],
 202                                  [NoBypass, E500_GPR_Bypass]>,
 203   InstrItinData<IIC_SprTLBSYNC,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 204                                   InstrStage<1, [E500_LSU_0], 0>]>,
 205   InstrItinData<IIC_SprMFCR,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 206                                   InstrStage<5, [E500_SU0]>],
 207                                  [8, 1],
 208                                  [E500_GPR_Bypass, E500_CR_Bypass]>,
 209   InstrItinData<IIC_SprMFCRF,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 210                                   InstrStage<5, [E500_SU0]>],
 211                                  [8, 1],
 212                                  [E500_GPR_Bypass, E500_CR_Bypass]>,
 213   InstrItinData<IIC_SprMFPMR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 214                                   InstrStage<4, [E500_SU0]>],
 215                                  [7, 1], // Latency = 4, Repeat rate = 4
 216                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 217   InstrItinData<IIC_SprMFMSR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 218                                   InstrStage<4, [E500_SU0]>],
 219                                  [7, 1], // Latency = 4, Repeat rate = 4
 220                                  [E500_GPR_Bypass, E500_GPR_Bypass]>,
 221   InstrItinData<IIC_SprMFSPR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 222                                   InstrStage<1, [E500_SU0, E500_SU1]>],
 223                                  [4, 1], // Latency = 1, Repeat rate = 1
 224                                  [E500_GPR_Bypass, E500_CR_Bypass]>,
 225   InstrItinData<IIC_SprMTPMR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 226                                   InstrStage<1, [E500_SU0]>],
 227                                  [4, 1], // Latency = 1, Repeat rate = 1
 228                                  [E500_CR_Bypass, E500_GPR_Bypass]>,
 229   InstrItinData<IIC_SprMFTB,     [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 230                                   InstrStage<4, [E500_SU0]>],
 231                                  [7, 1], // Latency = 4, Repeat rate = 4
 232                                  [NoBypass, E500_GPR_Bypass]>,
 233   InstrItinData<IIC_SprMTSPR,    [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 234                                   InstrStage<1, [E500_SU0, E500_SU1]>],
 235                                  [4, 1], // Latency = 1, Repeat rate = 1
 236                                  [E500_CR_Bypass, E500_GPR_Bypass]>,
 237   InstrItinData<IIC_SprMTSRIN,   [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 238                                   InstrStage<1, [E500_SU0]>],
 239                                  [4, 1],
 240                                  [NoBypass, E500_GPR_Bypass]>,
 241   InstrItinData<IIC_FPDGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 242                                   InstrStage<6, [E500_MU]>],
 243                                  [9, 1, 1],  // Latency = 6, Repeat rate = 1
 244                                  [NoBypass]>,
 245   InstrItinData<IIC_FPSGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 246                                   InstrStage<4, [E500_MU]>],
 247                                  [7, 1, 1],  // Latency = 4, Repeat rate = 1
 248                                  [NoBypass]>,
 249   InstrItinData<IIC_FPDivD,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 250                                   InstrStage<32, [E500_MU]>],
 251                                  [35, 1, 1], // Latency = 32, Repeat rate = 32
 252                                  [E500_DivBypass]>,
 253   InstrItinData<IIC_FPDivS,      [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 254                                   InstrStage<29, [E500_MU]>],
 255                                  [32, 1, 1], // Latency = 29, Repeat rate = 29
 256                                  [E500_DivBypass]>,
 257   InstrItinData<IIC_VecGeneral,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 258                                   InstrStage<1, [E500_SU0]>],
 259                                  [4, 1, 1], // Latency = 1, Repeat rate = 1
 260                                  [NoBypass]>,
 261   InstrItinData<IIC_VecComplex,  [InstrStage<1, [E500_DIS0, E500_DIS1], 0>,
 262                                   InstrStage<4, [E500_MU]>],
 263                                  [7, 1, 1], // Latency = 4, Repeat rate = 1
 264                                  [NoBypass]>
 265 ]>;
 266
 267 // ===---------------------------------------------------------------------===//
 268 // e500 machine model for scheduling and other instruction cost heuristics.
 269
 270 def PPCE500Model : SchedMachineModel {
 271   let IssueWidth = 2;  // 2 micro-ops are dispatched per cycle.
 272   let LoadLatency = 5; // Optimistic load latency assuming bypass.
 273                        // This is overriden by OperandCycles if the
 274                        // Itineraries are queried instead.
 275
 276   let CompleteModel = 0;
 277
 278   let Itineraries = PPCE500Itineraries;
 279 }