lib/Target/X86/X86.td

   1 //===-- X86.td - Target definition file for the Intel X86 --*- tablegen -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This is a target description file for the Intel i386 architecture, referred
  10 // to here as the "X86" architecture.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing...
  15 //
  16 include "llvm/Target/Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // X86 Subtarget state
  20 //
  21
  22 def Mode64Bit : SubtargetFeature<"64bit-mode", "In64BitMode", "true",
  23                                   "64-bit mode (x86_64)">;
  24 def Mode32Bit : SubtargetFeature<"32bit-mode", "In32BitMode", "true",
  25                                   "32-bit mode (80386)">;
  26 def Mode16Bit : SubtargetFeature<"16bit-mode", "In16BitMode", "true",
  27                                   "16-bit mode (i8086)">;
  28
  29 //===----------------------------------------------------------------------===//
  30 // X86 Subtarget features
  31 //===----------------------------------------------------------------------===//
  32
  33 def FeatureX87     : SubtargetFeature<"x87","HasX87", "true",
  34                                       "Enable X87 float instructions">;
  35
  36 def FeatureNOPL    : SubtargetFeature<"nopl", "HasNOPL", "true",
  37                                       "Enable NOPL instruction">;
  38
  39 def FeatureCMOV    : SubtargetFeature<"cmov","HasCMov", "true",
  40                                       "Enable conditional move instructions">;
  41
  42 def FeatureCMPXCHG8B : SubtargetFeature<"cx8", "HasCmpxchg8b", "true",
  43                                         "Support CMPXCHG8B instructions">;
  44
  45 def FeaturePOPCNT   : SubtargetFeature<"popcnt", "HasPOPCNT", "true",
  46                                        "Support POPCNT instruction">;
  47
  48 def FeatureFXSR    : SubtargetFeature<"fxsr", "HasFXSR", "true",
  49                                       "Support fxsave/fxrestore instructions">;
  50
  51 def FeatureXSAVE   : SubtargetFeature<"xsave", "HasXSAVE", "true",
  52                                        "Support xsave instructions">;
  53
  54 def FeatureXSAVEOPT: SubtargetFeature<"xsaveopt", "HasXSAVEOPT", "true",
  55                                        "Support xsaveopt instructions">;
  56
  57 def FeatureXSAVEC  : SubtargetFeature<"xsavec", "HasXSAVEC", "true",
  58                                        "Support xsavec instructions">;
  59
  60 def FeatureXSAVES  : SubtargetFeature<"xsaves", "HasXSAVES", "true",
  61                                        "Support xsaves instructions">;
  62
  63 def FeatureSSE1    : SubtargetFeature<"sse", "X86SSELevel", "SSE1",
  64                                       "Enable SSE instructions">;
  65 def FeatureSSE2    : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
  66                                       "Enable SSE2 instructions",
  67                                       [FeatureSSE1]>;
  68 def FeatureSSE3    : SubtargetFeature<"sse3", "X86SSELevel", "SSE3",
  69                                       "Enable SSE3 instructions",
  70                                       [FeatureSSE2]>;
  71 def FeatureSSSE3   : SubtargetFeature<"ssse3", "X86SSELevel", "SSSE3",
  72                                       "Enable SSSE3 instructions",
  73                                       [FeatureSSE3]>;
  74 def FeatureSSE41   : SubtargetFeature<"sse4.1", "X86SSELevel", "SSE41",
  75                                       "Enable SSE 4.1 instructions",
  76                                       [FeatureSSSE3]>;
  77 def FeatureSSE42   : SubtargetFeature<"sse4.2", "X86SSELevel", "SSE42",
  78                                       "Enable SSE 4.2 instructions",
  79                                       [FeatureSSE41]>;
  80 // The MMX subtarget feature is separate from the rest of the SSE features
  81 // because it's important (for odd compatibility reasons) to be able to
  82 // turn it off explicitly while allowing SSE+ to be on.
  83 def FeatureMMX     : SubtargetFeature<"mmx","X863DNowLevel", "MMX",
  84                                       "Enable MMX instructions">;
  85 def Feature3DNow   : SubtargetFeature<"3dnow", "X863DNowLevel", "ThreeDNow",
  86                                       "Enable 3DNow! instructions",
  87                                       [FeatureMMX]>;
  88 def Feature3DNowA  : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
  89                                       "Enable 3DNow! Athlon instructions",
  90                                       [Feature3DNow]>;
  91 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
  92 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
  93 // without disabling 64-bit mode. Nothing should imply this feature bit. It
  94 // is used to enforce that only 64-bit capable CPUs are used in 64-bit mode.
  95 def Feature64Bit   : SubtargetFeature<"64bit", "HasX86_64", "true",
  96                                       "Support 64-bit instructions">;
  97 def FeatureCMPXCHG16B : SubtargetFeature<"cx16", "HasCmpxchg16b", "true",
  98                                       "64-bit with cmpxchg16b",
  99                                       [FeatureCMPXCHG8B]>;
 100 def FeatureSlowSHLD : SubtargetFeature<"slow-shld", "IsSHLDSlow", "true",
 101                                        "SHLD instruction is slow">;
 102 def FeatureSlowPMULLD : SubtargetFeature<"slow-pmulld", "IsPMULLDSlow", "true",
 103                                         "PMULLD instruction is slow">;
 104 def FeatureSlowPMADDWD : SubtargetFeature<"slow-pmaddwd", "IsPMADDWDSlow",
 105                                           "true",
 106                                           "PMADDWD is slower than PMULLD">;
 107 // FIXME: This should not apply to CPUs that do not have SSE.
 108 def FeatureSlowUAMem16 : SubtargetFeature<"slow-unaligned-mem-16",
 109                                 "IsUAMem16Slow", "true",
 110                                 "Slow unaligned 16-byte memory access">;
 111 def FeatureSlowUAMem32 : SubtargetFeature<"slow-unaligned-mem-32",
 112                                 "IsUAMem32Slow", "true",
 113                                 "Slow unaligned 32-byte memory access">;
 114 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
 115                                       "Support SSE 4a instructions",
 116                                       [FeatureSSE3]>;
 117
 118 def FeatureAVX     : SubtargetFeature<"avx", "X86SSELevel", "AVX",
 119                                       "Enable AVX instructions",
 120                                       [FeatureSSE42]>;
 121 def FeatureAVX2    : SubtargetFeature<"avx2", "X86SSELevel", "AVX2",
 122                                       "Enable AVX2 instructions",
 123                                       [FeatureAVX]>;
 124 def FeatureFMA     : SubtargetFeature<"fma", "HasFMA", "true",
 125                                       "Enable three-operand fused multiple-add",
 126                                       [FeatureAVX]>;
 127 def FeatureF16C    : SubtargetFeature<"f16c", "HasF16C", "true",
 128                        "Support 16-bit floating point conversion instructions",
 129                        [FeatureAVX]>;
 130 def FeatureAVX512   : SubtargetFeature<"avx512f", "X86SSELevel", "AVX512F",
 131                                       "Enable AVX-512 instructions",
 132                                       [FeatureAVX2, FeatureFMA, FeatureF16C]>;
 133 def FeatureERI      : SubtargetFeature<"avx512er", "HasERI", "true",
 134                       "Enable AVX-512 Exponential and Reciprocal Instructions",
 135                                       [FeatureAVX512]>;
 136 def FeatureCDI      : SubtargetFeature<"avx512cd", "HasCDI", "true",
 137                       "Enable AVX-512 Conflict Detection Instructions",
 138                                       [FeatureAVX512]>;
 139 def FeatureVPOPCNTDQ : SubtargetFeature<"avx512vpopcntdq", "HasVPOPCNTDQ",
 140                        "true", "Enable AVX-512 Population Count Instructions",
 141                                       [FeatureAVX512]>;
 142 def FeaturePFI      : SubtargetFeature<"avx512pf", "HasPFI", "true",
 143                       "Enable AVX-512 PreFetch Instructions",
 144                                       [FeatureAVX512]>;
 145 def FeaturePREFETCHWT1  : SubtargetFeature<"prefetchwt1", "HasPREFETCHWT1",
 146                                    "true",
 147                                    "Prefetch with Intent to Write and T1 Hint">;
 148 def FeatureDQI     : SubtargetFeature<"avx512dq", "HasDQI", "true",
 149                       "Enable AVX-512 Doubleword and Quadword Instructions",
 150                                       [FeatureAVX512]>;
 151 def FeatureBWI     : SubtargetFeature<"avx512bw", "HasBWI", "true",
 152                       "Enable AVX-512 Byte and Word Instructions",
 153                                       [FeatureAVX512]>;
 154 def FeatureVLX     : SubtargetFeature<"avx512vl", "HasVLX", "true",
 155                       "Enable AVX-512 Vector Length eXtensions",
 156                                       [FeatureAVX512]>;
 157 def FeatureVBMI     : SubtargetFeature<"avx512vbmi", "HasVBMI", "true",
 158                       "Enable AVX-512 Vector Byte Manipulation Instructions",
 159                                       [FeatureBWI]>;
 160 def FeatureVBMI2    : SubtargetFeature<"avx512vbmi2", "HasVBMI2", "true",
 161                       "Enable AVX-512 further Vector Byte Manipulation Instructions",
 162                                       [FeatureBWI]>;
 163 def FeatureIFMA     : SubtargetFeature<"avx512ifma", "HasIFMA", "true",
 164                       "Enable AVX-512 Integer Fused Multiple-Add",
 165                                       [FeatureAVX512]>;
 166 def FeaturePKU   : SubtargetFeature<"pku", "HasPKU", "true",
 167                       "Enable protection keys">;
 168 def FeatureVNNI    : SubtargetFeature<"avx512vnni", "HasVNNI", "true",
 169                           "Enable AVX-512 Vector Neural Network Instructions",
 170                                       [FeatureAVX512]>;
 171 def FeatureBF16    : SubtargetFeature<"avx512bf16", "HasBF16", "true",
 172                            "Support bfloat16 floating point",
 173                                       [FeatureBWI]>;
 174 def FeatureBITALG  : SubtargetFeature<"avx512bitalg", "HasBITALG", "true",
 175                        "Enable AVX-512 Bit Algorithms",
 176                         [FeatureBWI]>;
 177 def FeatureVP2INTERSECT  : SubtargetFeature<"avx512vp2intersect",
 178                                             "HasVP2INTERSECT", "true",
 179                                             "Enable AVX-512 vp2intersect",
 180                                             [FeatureAVX512]>;
 181 def FeaturePCLMUL  : SubtargetFeature<"pclmul", "HasPCLMUL", "true",
 182                          "Enable packed carry-less multiplication instructions",
 183                                [FeatureSSE2]>;
 184 def FeatureGFNI    : SubtargetFeature<"gfni", "HasGFNI", "true",
 185                          "Enable Galois Field Arithmetic Instructions",
 186                                [FeatureSSE2]>;
 187 def FeatureVPCLMULQDQ : SubtargetFeature<"vpclmulqdq", "HasVPCLMULQDQ", "true",
 188                                          "Enable vpclmulqdq instructions",
 189                                          [FeatureAVX, FeaturePCLMUL]>;
 190 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
 191                                       "Enable four-operand fused multiple-add",
 192                                       [FeatureAVX, FeatureSSE4A]>;
 193 def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
 194                                       "Enable XOP instructions",
 195                                       [FeatureFMA4]>;
 196 def FeatureSSEUnalignedMem : SubtargetFeature<"sse-unaligned-mem",
 197                                           "HasSSEUnalignedMem", "true",
 198                       "Allow unaligned memory operands with SSE instructions">;
 199 def FeatureAES     : SubtargetFeature<"aes", "HasAES", "true",
 200                                       "Enable AES instructions",
 201                                       [FeatureSSE2]>;
 202 def FeatureVAES    : SubtargetFeature<"vaes", "HasVAES", "true",
 203                        "Promote selected AES instructions to AVX512/AVX registers",
 204                         [FeatureAVX, FeatureAES]>;
 205 def FeatureTBM     : SubtargetFeature<"tbm", "HasTBM", "true",
 206                                       "Enable TBM instructions">;
 207 def FeatureLWP     : SubtargetFeature<"lwp", "HasLWP", "true",
 208                                       "Enable LWP instructions">;
 209 def FeatureMOVBE   : SubtargetFeature<"movbe", "HasMOVBE", "true",
 210                                       "Support MOVBE instruction">;
 211 def FeatureRDRAND  : SubtargetFeature<"rdrnd", "HasRDRAND", "true",
 212                                       "Support RDRAND instruction">;
 213 def FeatureFSGSBase : SubtargetFeature<"fsgsbase", "HasFSGSBase", "true",
 214                                        "Support FS/GS Base instructions">;
 215 def FeatureLZCNT   : SubtargetFeature<"lzcnt", "HasLZCNT", "true",
 216                                       "Support LZCNT instruction">;
 217 def FeatureBMI     : SubtargetFeature<"bmi", "HasBMI", "true",
 218                                       "Support BMI instructions">;
 219 def FeatureBMI2    : SubtargetFeature<"bmi2", "HasBMI2", "true",
 220                                       "Support BMI2 instructions">;
 221 def FeatureRTM     : SubtargetFeature<"rtm", "HasRTM", "true",
 222                                       "Support RTM instructions">;
 223 def FeatureADX     : SubtargetFeature<"adx", "HasADX", "true",
 224                                       "Support ADX instructions">;
 225 def FeatureSHA     : SubtargetFeature<"sha", "HasSHA", "true",
 226                                       "Enable SHA instructions",
 227                                       [FeatureSSE2]>;
 228 def FeatureSHSTK   : SubtargetFeature<"shstk", "HasSHSTK", "true",
 229                        "Support CET Shadow-Stack instructions">;
 230 def FeaturePRFCHW  : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
 231                                       "Support PRFCHW instructions">;
 232 def FeatureRDSEED  : SubtargetFeature<"rdseed", "HasRDSEED", "true",
 233                                       "Support RDSEED instruction">;
 234 def FeatureLAHFSAHF : SubtargetFeature<"sahf", "HasLAHFSAHF", "true",
 235                                        "Support LAHF and SAHF instructions">;
 236 def FeatureMWAITX  : SubtargetFeature<"mwaitx", "HasMWAITX", "true",
 237                                       "Enable MONITORX/MWAITX timer functionality">;
 238 def FeatureCLZERO  : SubtargetFeature<"clzero", "HasCLZERO", "true",
 239                                       "Enable Cache Line Zero">;
 240 def FeatureCLDEMOTE  : SubtargetFeature<"cldemote", "HasCLDEMOTE", "true",
 241                                       "Enable Cache Demote">;
 242 def FeaturePTWRITE  : SubtargetFeature<"ptwrite", "HasPTWRITE", "true",
 243                                       "Support ptwrite instruction">;
 244 // FIXME: This feature is deprecated in 10.0 and should not be used for
 245 // anything, but removing it would break IR files that may contain it in a
 246 // target-feature attribute.
 247 def FeatureDeprecatedMPX : SubtargetFeature<"mpx", "DeprecatedHasMPX", "false",
 248                                       "Deprecated. Support MPX instructions">;
 249 def FeatureLEAForSP : SubtargetFeature<"lea-sp", "UseLeaForSP", "true",
 250                                      "Use LEA for adjusting the stack pointer">;
 251 def FeatureSlowDivide32 : SubtargetFeature<"idivl-to-divb",
 252                                      "HasSlowDivide32", "true",
 253                                      "Use 8-bit divide for positive values less than 256">;
 254 def FeatureSlowDivide64 : SubtargetFeature<"idivq-to-divl",
 255                                      "HasSlowDivide64", "true",
 256                                      "Use 32-bit divide for positive values less than 2^32">;
 257 def FeaturePadShortFunctions : SubtargetFeature<"pad-short-functions",
 258                                      "PadShortFunctions", "true",
 259                                      "Pad short functions">;
 260 def FeatureINVPCID : SubtargetFeature<"invpcid", "HasINVPCID", "true",
 261                                       "Invalidate Process-Context Identifier">;
 262 def FeatureSGX     : SubtargetFeature<"sgx", "HasSGX", "true",
 263                                       "Enable Software Guard Extensions">;
 264 def FeatureCLFLUSHOPT : SubtargetFeature<"clflushopt", "HasCLFLUSHOPT", "true",
 265                                       "Flush A Cache Line Optimized">;
 266 def FeatureCLWB    : SubtargetFeature<"clwb", "HasCLWB", "true",
 267                                       "Cache Line Write Back">;
 268 def FeatureWBNOINVD    : SubtargetFeature<"wbnoinvd", "HasWBNOINVD", "true",
 269                                       "Write Back No Invalidate">;
 270 def FeatureRDPID : SubtargetFeature<"rdpid", "HasRDPID", "true",
 271                                     "Support RDPID instructions">;
 272 def FeatureWAITPKG  : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
 273                                       "Wait and pause enhancements">;
 274 def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
 275                                      "Has ENQCMD instructions">;
 276 // On some processors, instructions that implicitly take two memory operands are
 277 // slow. In practice, this means that CALL, PUSH, and POP with memory operands
 278 // should be avoided in favor of a MOV + register CALL/PUSH/POP.
 279 def FeatureSlowTwoMemOps : SubtargetFeature<"slow-two-mem-ops",
 280                                      "SlowTwoMemOps", "true",
 281                                      "Two memory operand instructions are slow">;
 282 def FeatureLEAUsesAG : SubtargetFeature<"lea-uses-ag", "LEAUsesAG", "true",
 283                                    "LEA instruction needs inputs at AG stage">;
 284 def FeatureSlowLEA : SubtargetFeature<"slow-lea", "SlowLEA", "true",
 285                                    "LEA instruction with certain arguments is slow">;
 286 def FeatureSlow3OpsLEA : SubtargetFeature<"slow-3ops-lea", "Slow3OpsLEA", "true",
 287                                    "LEA instruction with 3 ops or certain registers is slow">;
 288 def FeatureSlowIncDec : SubtargetFeature<"slow-incdec", "SlowIncDec", "true",
 289                                    "INC and DEC instructions are slower than ADD and SUB">;
 290 def FeatureSoftFloat
 291     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
 292                        "Use software floating point features">;
 293 def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
 294                                      "HasPOPCNTFalseDeps", "true",
 295                                      "POPCNT has a false dependency on dest register">;
 296 def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
 297                                      "HasLZCNTFalseDeps", "true",
 298                                      "LZCNT/TZCNT have a false dependency on dest register">;
 299 def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
 300                                       "platform configuration instruction">;
 301 // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
 302 // using a variable mask over multiple fixed shuffles.
 303 def FeatureFastVariableShuffle
 304     : SubtargetFeature<"fast-variable-shuffle",
 305                        "HasFastVariableShuffle",
 306                        "true", "Shuffles with variable masks are fast">;
 307 // On some X86 processors, there is no performance hazard to writing only the
 308 // lower parts of a YMM or ZMM register without clearing the upper part.
 309 def FeatureFastPartialYMMorZMMWrite
 310     : SubtargetFeature<"fast-partial-ymm-or-zmm-write",
 311                        "HasFastPartialYMMorZMMWrite",
 312                        "true", "Partial writes to YMM/ZMM registers are fast">;
 313 // FeatureFastScalarFSQRT should be enabled if scalar FSQRT has shorter latency
 314 // than the corresponding NR code. FeatureFastVectorFSQRT should be enabled if
 315 // vector FSQRT has higher throughput than the corresponding NR code.
 316 // The idea is that throughput bound code is likely to be vectorized, so for
 317 // vectorized code we should care about the throughput of SQRT operations.
 318 // But if the code is scalar that probably means that the code has some kind of
 319 // dependency and we should care more about reducing the latency.
 320 def FeatureFastScalarFSQRT
 321     : SubtargetFeature<"fast-scalar-fsqrt", "HasFastScalarFSQRT",
 322                        "true", "Scalar SQRT is fast (disable Newton-Raphson)">;
 323 def FeatureFastVectorFSQRT
 324     : SubtargetFeature<"fast-vector-fsqrt", "HasFastVectorFSQRT",
 325                        "true", "Vector SQRT is fast (disable Newton-Raphson)">;
 326 // If lzcnt has equivalent latency/throughput to most simple integer ops, it can
 327 // be used to replace test/set sequences.
 328 def FeatureFastLZCNT
 329     : SubtargetFeature<
 330           "fast-lzcnt", "HasFastLZCNT", "true",
 331           "LZCNT instructions are as fast as most simple integer ops">;
 332 // If the target can efficiently decode NOPs upto 11-bytes in length.
 333 def FeatureFast11ByteNOP
 334     : SubtargetFeature<
 335           "fast-11bytenop", "HasFast11ByteNOP", "true",
 336           "Target can quickly decode up to 11 byte NOPs">;
 337 // If the target can efficiently decode NOPs upto 15-bytes in length.
 338 def FeatureFast15ByteNOP
 339     : SubtargetFeature<
 340           "fast-15bytenop", "HasFast15ByteNOP", "true",
 341           "Target can quickly decode up to 15 byte NOPs">;
 342 // Sandy Bridge and newer processors can use SHLD with the same source on both
 343 // inputs to implement rotate to avoid the partial flag update of the normal
 344 // rotate instructions.
 345 def FeatureFastSHLDRotate
 346     : SubtargetFeature<
 347           "fast-shld-rotate", "HasFastSHLDRotate", "true",
 348           "SHLD can be used as a faster rotate">;
 349
 350 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 351 // "string operations"). See "REP String Enhancement" in the Intel Software
 352 // Development Manual. This feature essentially means that REP MOVSB will copy
 353 // using the largest available size instead of copying bytes one by one, making
 354 // it at least as fast as REPMOVS{W,D,Q}.
 355 def FeatureERMSB
 356     : SubtargetFeature<
 357           "ermsb", "HasERMSB", "true",
 358           "REP MOVS/STOS are fast">;
 359
 360 // Bulldozer and newer processors can merge CMP/TEST (but not other
 361 // instructions) with conditional branches.
 362 def FeatureBranchFusion
 363     : SubtargetFeature<"branchfusion", "HasBranchFusion", "true",
 364                  "CMP/TEST can be fused with conditional branches">;
 365
 366 // Sandy Bridge and newer processors have many instructions that can be
 367 // fused with conditional branches and pass through the CPU as a single
 368 // operation.
 369 def FeatureMacroFusion
 370     : SubtargetFeature<"macrofusion", "HasMacroFusion", "true",
 371                  "Various instructions can be fused with conditional branches">;
 372
 373 // Gather is available since Haswell (AVX2 set). So technically, we can
 374 // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
 375 // Skylake Client processor has faster Gathers than HSW and performance is
 376 // similar to Skylake Server (AVX-512).
 377 def FeatureHasFastGather
 378     : SubtargetFeature<"fast-gather", "HasFastGather", "true",
 379                        "Indicates if gather is reasonably fast">;
 380
 381 def FeaturePrefer256Bit
 382     : SubtargetFeature<"prefer-256-bit", "Prefer256Bit", "true",
 383                        "Prefer 256-bit AVX instructions">;
 384
 385 // Lower indirect calls using a special construct called a `retpoline` to
 386 // mitigate potential Spectre v2 attacks against them.
 387 def FeatureRetpolineIndirectCalls
 388     : SubtargetFeature<
 389           "retpoline-indirect-calls", "UseRetpolineIndirectCalls", "true",
 390           "Remove speculation of indirect calls from the generated code">;
 391
 392 // Lower indirect branches and switches either using conditional branch trees
 393 // or using a special construct called a `retpoline` to mitigate potential
 394 // Spectre v2 attacks against them.
 395 def FeatureRetpolineIndirectBranches
 396     : SubtargetFeature<
 397           "retpoline-indirect-branches", "UseRetpolineIndirectBranches", "true",
 398           "Remove speculation of indirect branches from the generated code">;
 399
 400 // Deprecated umbrella feature for enabling both `retpoline-indirect-calls` and
 401 // `retpoline-indirect-branches` above.
 402 def FeatureRetpoline
 403     : SubtargetFeature<"retpoline", "DeprecatedUseRetpoline", "true",
 404                        "Remove speculation of indirect branches from the "
 405                        "generated code, either by avoiding them entirely or "
 406                        "lowering them with a speculation blocking construct",
 407                        [FeatureRetpolineIndirectCalls,
 408                         FeatureRetpolineIndirectBranches]>;
 409
 410 // Rely on external thunks for the emitted retpoline calls. This allows users
 411 // to provide their own custom thunk definitions in highly specialized
 412 // environments such as a kernel that does boot-time hot patching.
 413 def FeatureRetpolineExternalThunk
 414     : SubtargetFeature<
 415           "retpoline-external-thunk", "UseRetpolineExternalThunk", "true",
 416           "When lowering an indirect call or branch using a `retpoline`, rely "
 417           "on the specified user provided thunk rather than emitting one "
 418           "ourselves. Only has effect when combined with some other retpoline "
 419           "feature", [FeatureRetpolineIndirectCalls]>;
 420
 421 // Direct Move instructions.
 422 def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
 423                                        "Support movdiri instruction">;
 424 def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
 425                                         "Support movdir64b instruction">;
 426
 427 def FeatureFastBEXTR : SubtargetFeature<"fast-bextr", "HasFastBEXTR", "true",
 428           "Indicates that the BEXTR instruction is implemented as a single uop "
 429           "with good throughput">;
 430
 431 // Combine vector math operations with shuffles into horizontal math
 432 // instructions if a CPU implements horizontal operations (introduced with
 433 // SSE3) with better latency/throughput than the alternative sequence.
 434 def FeatureFastHorizontalOps
 435     : SubtargetFeature<
 436         "fast-hops", "HasFastHorizontalOps", "true",
 437         "Prefer horizontal vector math instructions (haddp, phsub, etc.) over "
 438         "normal vector instructions with shuffles", [FeatureSSE3]>;
 439
 440 def FeatureFastScalarShiftMasks
 441     : SubtargetFeature<
 442         "fast-scalar-shift-masks", "HasFastScalarShiftMasks", "true",
 443         "Prefer a left/right scalar logical shift pair over a shift+and pair">;
 444
 445 def FeatureFastVectorShiftMasks
 446     : SubtargetFeature<
 447         "fast-vector-shift-masks", "HasFastVectorShiftMasks", "true",
 448         "Prefer a left/right vector logical shift pair over a shift+and pair">;
 449
 450 // Merge branches using three-way conditional code.
 451 def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch",
 452                                         "ThreewayBranchProfitable", "true",
 453                                         "Merge branches to a three-way "
 454                                         "conditional branch">;
 455
 456 // Bonnell
 457 def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
 458 // Silvermont
 459 def ProcIntelSLM  : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
 460 // Goldmont
 461 def ProcIntelGLM  : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">;
 462 // Goldmont Plus
 463 def ProcIntelGLP  : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">;
 464 // Tremont
 465 def ProcIntelTRM  : SubtargetFeature<"", "X86ProcFamily", "IntelTRM", "">;
 466
 467 //===----------------------------------------------------------------------===//
 468 // Register File Description
 469 //===----------------------------------------------------------------------===//
 470
 471 include "X86RegisterInfo.td"
 472 include "X86RegisterBanks.td"
 473
 474 //===----------------------------------------------------------------------===//
 475 // Instruction Descriptions
 476 //===----------------------------------------------------------------------===//
 477
 478 include "X86Schedule.td"
 479 include "X86InstrInfo.td"
 480 include "X86SchedPredicates.td"
 481
 482 def X86InstrInfo : InstrInfo;
 483
 484 //===----------------------------------------------------------------------===//
 485 // X86 Scheduler Models
 486 //===----------------------------------------------------------------------===//
 487
 488 include "X86ScheduleAtom.td"
 489 include "X86SchedSandyBridge.td"
 490 include "X86SchedHaswell.td"
 491 include "X86SchedBroadwell.td"
 492 include "X86ScheduleSLM.td"
 493 include "X86ScheduleZnver1.td"
 494 include "X86ScheduleBdVer2.td"
 495 include "X86ScheduleBtVer2.td"
 496 include "X86SchedSkylakeClient.td"
 497 include "X86SchedSkylakeServer.td"
 498
 499 //===----------------------------------------------------------------------===//
 500 // X86 Processor Feature Lists
 501 //===----------------------------------------------------------------------===//
 502
 503 def ProcessorFeatures {
 504   // Nehalem
 505   list<SubtargetFeature> NHMInheritableFeatures = [FeatureX87,
 506                                                    FeatureCMPXCHG8B,
 507                                                    FeatureCMOV,
 508                                                    FeatureMMX,
 509                                                    FeatureSSE42,
 510                                                    FeatureFXSR,
 511                                                    FeatureNOPL,
 512                                                    Feature64Bit,
 513                                                    FeatureCMPXCHG16B,
 514                                                    FeaturePOPCNT,
 515                                                    FeatureLAHFSAHF,
 516                                                    FeatureMacroFusion];
 517   list<SubtargetFeature> NHMSpecificFeatures = [];
 518   list<SubtargetFeature> NHMFeatures =
 519     !listconcat(NHMInheritableFeatures, NHMSpecificFeatures);
 520
 521   // Westmere
 522   list<SubtargetFeature> WSMAdditionalFeatures = [FeaturePCLMUL];
 523   list<SubtargetFeature> WSMSpecificFeatures = [];
 524   list<SubtargetFeature> WSMInheritableFeatures =
 525     !listconcat(NHMInheritableFeatures, WSMAdditionalFeatures);
 526   list<SubtargetFeature> WSMFeatures =
 527     !listconcat(WSMInheritableFeatures, WSMSpecificFeatures);
 528
 529   // Sandybridge
 530   list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
 531                                                   FeatureSlowDivide64,
 532                                                   FeatureXSAVE,
 533                                                   FeatureXSAVEOPT,
 534                                                   FeatureSlow3OpsLEA,
 535                                                   FeatureFastScalarFSQRT,
 536                                                   FeatureFastSHLDRotate,
 537                                                   FeatureMergeToThreeWayBranch];
 538   list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32,
 539                                                 FeaturePOPCNTFalseDeps];
 540   list<SubtargetFeature> SNBInheritableFeatures =
 541     !listconcat(WSMInheritableFeatures, SNBAdditionalFeatures);
 542   list<SubtargetFeature> SNBFeatures =
 543     !listconcat(SNBInheritableFeatures, SNBSpecificFeatures);
 544
 545   // Ivybridge
 546   list<SubtargetFeature> IVBAdditionalFeatures = [FeatureRDRAND,
 547                                                   FeatureF16C,
 548                                                   FeatureFSGSBase];
 549   list<SubtargetFeature> IVBSpecificFeatures = [FeatureSlowUAMem32,
 550                                                 FeaturePOPCNTFalseDeps];
 551   list<SubtargetFeature> IVBInheritableFeatures =
 552     !listconcat(SNBInheritableFeatures, IVBAdditionalFeatures);
 553   list<SubtargetFeature> IVBFeatures =
 554     !listconcat(IVBInheritableFeatures, IVBSpecificFeatures);
 555
 556   // Haswell
 557   list<SubtargetFeature> HSWAdditionalFeatures = [FeatureAVX2,
 558                                                   FeatureBMI,
 559                                                   FeatureBMI2,
 560                                                   FeatureERMSB,
 561                                                   FeatureFMA,
 562                                                   FeatureINVPCID,
 563                                                   FeatureLZCNT,
 564                                                   FeatureMOVBE,
 565                                                   FeatureFastVariableShuffle];
 566   list<SubtargetFeature> HSWSpecificFeatures = [FeaturePOPCNTFalseDeps,
 567                                                 FeatureLZCNTFalseDeps];
 568   list<SubtargetFeature> HSWInheritableFeatures =
 569     !listconcat(IVBInheritableFeatures, HSWAdditionalFeatures);
 570   list<SubtargetFeature> HSWFeatures =
 571     !listconcat(HSWInheritableFeatures, HSWSpecificFeatures);
 572
 573   // Broadwell
 574   list<SubtargetFeature> BDWAdditionalFeatures = [FeatureADX,
 575                                                   FeatureRDSEED,
 576                                                   FeaturePRFCHW];
 577   list<SubtargetFeature> BDWSpecificFeatures = [FeaturePOPCNTFalseDeps,
 578                                                 FeatureLZCNTFalseDeps];
 579   list<SubtargetFeature> BDWInheritableFeatures =
 580     !listconcat(HSWInheritableFeatures, BDWAdditionalFeatures);
 581   list<SubtargetFeature> BDWFeatures =
 582     !listconcat(BDWInheritableFeatures, BDWSpecificFeatures);
 583
 584   // Skylake
 585   list<SubtargetFeature> SKLAdditionalFeatures = [FeatureAES,
 586                                                   FeatureXSAVEC,
 587                                                   FeatureXSAVES,
 588                                                   FeatureCLFLUSHOPT,
 589                                                   FeatureFastVectorFSQRT];
 590   list<SubtargetFeature> SKLSpecificFeatures = [FeatureHasFastGather,
 591                                                 FeaturePOPCNTFalseDeps,
 592                                                 FeatureSGX];
 593   list<SubtargetFeature> SKLInheritableFeatures =
 594     !listconcat(BDWInheritableFeatures, SKLAdditionalFeatures);
 595   list<SubtargetFeature> SKLFeatures =
 596     !listconcat(SKLInheritableFeatures, SKLSpecificFeatures);
 597
 598   // Skylake-AVX512
 599   list<SubtargetFeature> SKXAdditionalFeatures = [FeatureAVX512,
 600                                                   FeatureCDI,
 601                                                   FeatureDQI,
 602                                                   FeatureBWI,
 603                                                   FeatureVLX,
 604                                                   FeaturePKU,
 605                                                   FeatureCLWB];
 606   list<SubtargetFeature> SKXSpecificFeatures = [FeatureHasFastGather,
 607                                                 FeaturePOPCNTFalseDeps];
 608   list<SubtargetFeature> SKXInheritableFeatures =
 609     !listconcat(SKLInheritableFeatures, SKXAdditionalFeatures);
 610   list<SubtargetFeature> SKXFeatures =
 611     !listconcat(SKXInheritableFeatures, SKXSpecificFeatures);
 612
 613   // Cascadelake
 614   list<SubtargetFeature> CLXAdditionalFeatures = [FeatureVNNI];
 615   list<SubtargetFeature> CLXSpecificFeatures = [FeatureHasFastGather,
 616                                                 FeaturePOPCNTFalseDeps];
 617   list<SubtargetFeature> CLXInheritableFeatures =
 618     !listconcat(SKXInheritableFeatures, CLXAdditionalFeatures);
 619   list<SubtargetFeature> CLXFeatures =
 620     !listconcat(CLXInheritableFeatures, CLXSpecificFeatures);
 621
 622   // Cooperlake
 623   list<SubtargetFeature> CPXAdditionalFeatures = [FeatureBF16];
 624   list<SubtargetFeature> CPXSpecificFeatures = [FeatureHasFastGather,
 625                                                 FeaturePOPCNTFalseDeps];
 626   list<SubtargetFeature> CPXInheritableFeatures =
 627     !listconcat(CLXInheritableFeatures, CPXAdditionalFeatures);
 628   list<SubtargetFeature> CPXFeatures =
 629     !listconcat(CPXInheritableFeatures, CPXSpecificFeatures);
 630
 631   // Cannonlake
 632   list<SubtargetFeature> CNLAdditionalFeatures = [FeatureAVX512,
 633                                                   FeatureCDI,
 634                                                   FeatureDQI,
 635                                                   FeatureBWI,
 636                                                   FeatureVLX,
 637                                                   FeaturePKU,
 638                                                   FeatureVBMI,
 639                                                   FeatureIFMA,
 640                                                   FeatureSHA,
 641                                                   FeatureSGX];
 642   list<SubtargetFeature> CNLSpecificFeatures = [FeatureHasFastGather];
 643   list<SubtargetFeature> CNLInheritableFeatures =
 644     !listconcat(SKLInheritableFeatures, CNLAdditionalFeatures);
 645   list<SubtargetFeature> CNLFeatures =
 646     !listconcat(CNLInheritableFeatures, CNLSpecificFeatures);
 647
 648   // Icelake
 649   list<SubtargetFeature> ICLAdditionalFeatures = [FeatureBITALG,
 650                                                   FeatureVAES,
 651                                                   FeatureVBMI2,
 652                                                   FeatureVNNI,
 653                                                   FeatureVPCLMULQDQ,
 654                                                   FeatureVPOPCNTDQ,
 655                                                   FeatureGFNI,
 656                                                   FeatureCLWB,
 657                                                   FeatureRDPID];
 658   list<SubtargetFeature> ICLSpecificFeatures = [FeatureHasFastGather];
 659   list<SubtargetFeature> ICLInheritableFeatures =
 660     !listconcat(CNLInheritableFeatures, ICLAdditionalFeatures);
 661   list<SubtargetFeature> ICLFeatures =
 662     !listconcat(ICLInheritableFeatures, ICLSpecificFeatures);
 663
 664   // Icelake Server
 665   list<SubtargetFeature> ICXSpecificFeatures = [FeaturePCONFIG,
 666                                                 FeatureWBNOINVD,
 667                                                 FeatureHasFastGather];
 668   list<SubtargetFeature> ICXFeatures =
 669     !listconcat(ICLInheritableFeatures, ICXSpecificFeatures);
 670
 671   //Tigerlake
 672   list<SubtargetFeature> TGLAdditionalFeatures = [FeatureVP2INTERSECT,
 673                                                   FeatureMOVDIRI,
 674                                                   FeatureMOVDIR64B,
 675                                                   FeatureSHSTK];
 676   list<SubtargetFeature> TGLSpecificFeatures = [FeatureHasFastGather];
 677   list<SubtargetFeature> TGLInheritableFeatures =
 678     !listconcat(TGLAdditionalFeatures ,TGLSpecificFeatures);
 679   list<SubtargetFeature> TGLFeatures =
 680     !listconcat(ICLFeatures, TGLInheritableFeatures );
 681
 682   // Atom
 683   list<SubtargetFeature> AtomInheritableFeatures = [FeatureX87,
 684                                                     FeatureCMPXCHG8B,
 685                                                     FeatureCMOV,
 686                                                     FeatureMMX,
 687                                                     FeatureSSSE3,
 688                                                     FeatureFXSR,
 689                                                     FeatureNOPL,
 690                                                     Feature64Bit,
 691                                                     FeatureCMPXCHG16B,
 692                                                     FeatureMOVBE,
 693                                                     FeatureSlowTwoMemOps,
 694                                                     FeatureLAHFSAHF];
 695   list<SubtargetFeature> AtomSpecificFeatures = [ProcIntelAtom,
 696                                                  FeatureSlowUAMem16,
 697                                                  FeatureLEAForSP,
 698                                                  FeatureSlowDivide32,
 699                                                  FeatureSlowDivide64,
 700                                                  FeatureLEAUsesAG,
 701                                                  FeaturePadShortFunctions];
 702   list<SubtargetFeature> AtomFeatures =
 703     !listconcat(AtomInheritableFeatures, AtomSpecificFeatures);
 704
 705   // Silvermont
 706   list<SubtargetFeature> SLMAdditionalFeatures = [FeatureSSE42,
 707                                                   FeaturePOPCNT,
 708                                                   FeaturePCLMUL,
 709                                                   FeaturePRFCHW,
 710                                                   FeatureSlowLEA,
 711                                                   FeatureSlowIncDec,
 712                                                   FeatureRDRAND];
 713   list<SubtargetFeature> SLMSpecificFeatures = [ProcIntelSLM,
 714                                                 FeatureSlowDivide64,
 715                                                 FeatureSlowPMULLD,
 716                                                 FeaturePOPCNTFalseDeps];
 717   list<SubtargetFeature> SLMInheritableFeatures =
 718     !listconcat(AtomInheritableFeatures, SLMAdditionalFeatures);
 719   list<SubtargetFeature> SLMFeatures =
 720     !listconcat(SLMInheritableFeatures, SLMSpecificFeatures);
 721
 722   // Goldmont
 723   list<SubtargetFeature> GLMAdditionalFeatures = [FeatureAES,
 724                                                   FeatureSHA,
 725                                                   FeatureRDSEED,
 726                                                   FeatureXSAVE,
 727                                                   FeatureXSAVEOPT,
 728                                                   FeatureXSAVEC,
 729                                                   FeatureXSAVES,
 730                                                   FeatureCLFLUSHOPT,
 731                                                   FeatureFSGSBase];
 732   list<SubtargetFeature> GLMSpecificFeatures = [ProcIntelGLM,
 733                                                 FeaturePOPCNTFalseDeps];
 734   list<SubtargetFeature> GLMInheritableFeatures =
 735     !listconcat(SLMInheritableFeatures, GLMAdditionalFeatures);
 736   list<SubtargetFeature> GLMFeatures =
 737     !listconcat(GLMInheritableFeatures, GLMSpecificFeatures);
 738
 739   // Goldmont Plus
 740   list<SubtargetFeature> GLPAdditionalFeatures = [FeaturePTWRITE,
 741                                                   FeatureRDPID,
 742                                                   FeatureSGX];
 743   list<SubtargetFeature> GLPSpecificFeatures = [ProcIntelGLP];
 744   list<SubtargetFeature> GLPInheritableFeatures =
 745     !listconcat(GLMInheritableFeatures, GLPAdditionalFeatures);
 746   list<SubtargetFeature> GLPFeatures =
 747     !listconcat(GLPInheritableFeatures, GLPSpecificFeatures);
 748
 749   // Tremont
 750   list<SubtargetFeature> TRMAdditionalFeatures = [FeatureCLDEMOTE,
 751                                                   FeatureGFNI,
 752                                                   FeatureMOVDIRI,
 753                                                   FeatureMOVDIR64B,
 754                                                   FeatureWAITPKG];
 755   list<SubtargetFeature> TRMSpecificFeatures = [ProcIntelTRM];
 756   list<SubtargetFeature> TRMFeatures =
 757     !listconcat(GLPInheritableFeatures, TRMAdditionalFeatures,
 758                 TRMSpecificFeatures);
 759
 760   // Knights Landing
 761   list<SubtargetFeature> KNLFeatures = [FeatureX87,
 762                                         FeatureCMPXCHG8B,
 763                                         FeatureCMOV,
 764                                         FeatureMMX,
 765                                         FeatureFXSR,
 766                                         FeatureNOPL,
 767                                         Feature64Bit,
 768                                         FeatureCMPXCHG16B,
 769                                         FeaturePOPCNT,
 770                                         FeatureSlowDivide64,
 771                                         FeaturePCLMUL,
 772                                         FeatureXSAVE,
 773                                         FeatureXSAVEOPT,
 774                                         FeatureLAHFSAHF,
 775                                         FeatureSlow3OpsLEA,
 776                                         FeatureSlowIncDec,
 777                                         FeatureAES,
 778                                         FeatureRDRAND,
 779                                         FeatureF16C,
 780                                         FeatureFSGSBase,
 781                                         FeatureAVX512,
 782                                         FeatureERI,
 783                                         FeatureCDI,
 784                                         FeaturePFI,
 785                                         FeaturePREFETCHWT1,
 786                                         FeatureADX,
 787                                         FeatureRDSEED,
 788                                         FeatureMOVBE,
 789                                         FeatureLZCNT,
 790                                         FeatureBMI,
 791                                         FeatureBMI2,
 792                                         FeatureFMA,
 793                                         FeaturePRFCHW,
 794                                         FeatureSlowTwoMemOps,
 795                                         FeatureFastPartialYMMorZMMWrite,
 796                                         FeatureHasFastGather,
 797                                         FeatureSlowPMADDWD];
 798   // TODO Add AVX5124FMAPS/AVX5124VNNIW features
 799   list<SubtargetFeature> KNMFeatures =
 800     !listconcat(KNLFeatures, [FeatureVPOPCNTDQ]);
 801
 802   // Barcelona
 803   list<SubtargetFeature> BarcelonaInheritableFeatures = [FeatureX87,
 804                                                          FeatureCMPXCHG8B,
 805                                                          FeatureSSE4A,
 806                                                          Feature3DNowA,
 807                                                          FeatureFXSR,
 808                                                          FeatureNOPL,
 809                                                          FeatureCMPXCHG16B,
 810                                                          FeatureLZCNT,
 811                                                          FeaturePOPCNT,
 812                                                          FeatureSlowSHLD,
 813                                                          FeatureLAHFSAHF,
 814                                                          FeatureCMOV,
 815                                                          Feature64Bit,
 816                                                          FeatureFastScalarShiftMasks];
 817   list<SubtargetFeature> BarcelonaFeatures = BarcelonaInheritableFeatures;
 818
 819   // Bobcat
 820   list<SubtargetFeature> BtVer1InheritableFeatures = [FeatureX87,
 821                                                       FeatureCMPXCHG8B,
 822                                                       FeatureCMOV,
 823                                                       FeatureMMX,
 824                                                       FeatureSSSE3,
 825                                                       FeatureSSE4A,
 826                                                       FeatureFXSR,
 827                                                       FeatureNOPL,
 828                                                       Feature64Bit,
 829                                                       FeatureCMPXCHG16B,
 830                                                       FeaturePRFCHW,
 831                                                       FeatureLZCNT,
 832                                                       FeaturePOPCNT,
 833                                                       FeatureSlowSHLD,
 834                                                       FeatureLAHFSAHF,
 835                                                       FeatureFast15ByteNOP,
 836                                                       FeatureFastScalarShiftMasks,
 837                                                       FeatureFastVectorShiftMasks];
 838   list<SubtargetFeature> BtVer1Features = BtVer1InheritableFeatures;
 839
 840   // Jaguar
 841   list<SubtargetFeature> BtVer2AdditionalFeatures = [FeatureAVX,
 842                                                      FeatureAES,
 843                                                      FeaturePCLMUL,
 844                                                      FeatureBMI,
 845                                                      FeatureF16C,
 846                                                      FeatureMOVBE,
 847                                                      FeatureXSAVE,
 848                                                      FeatureXSAVEOPT];
 849   list<SubtargetFeature> BtVer2SpecificFeatures = [FeatureFastLZCNT,
 850                                                    FeatureFastBEXTR,
 851                                                    FeatureFastPartialYMMorZMMWrite,
 852                                                    FeatureFastHorizontalOps];
 853   list<SubtargetFeature> BtVer2InheritableFeatures =
 854     !listconcat(BtVer1InheritableFeatures, BtVer2AdditionalFeatures);
 855   list<SubtargetFeature> BtVer2Features =
 856     !listconcat(BtVer2InheritableFeatures, BtVer2SpecificFeatures);
 857
 858   // Bulldozer
 859   list<SubtargetFeature> BdVer1InheritableFeatures = [FeatureX87,
 860                                                       FeatureCMPXCHG8B,
 861                                                       FeatureCMOV,
 862                                                       FeatureXOP,
 863                                                       Feature64Bit,
 864                                                       FeatureCMPXCHG16B,
 865                                                       FeatureAES,
 866                                                       FeaturePRFCHW,
 867                                                       FeaturePCLMUL,
 868                                                       FeatureMMX,
 869                                                       FeatureFXSR,
 870                                                       FeatureNOPL,
 871                                                       FeatureLZCNT,
 872                                                       FeaturePOPCNT,
 873                                                       FeatureXSAVE,
 874                                                       FeatureLWP,
 875                                                       FeatureSlowSHLD,
 876                                                       FeatureLAHFSAHF,
 877                                                       FeatureFast11ByteNOP,
 878                                                       FeatureFastScalarShiftMasks,
 879                                                       FeatureBranchFusion];
 880   list<SubtargetFeature> BdVer1Features = BdVer1InheritableFeatures;
 881
 882   // PileDriver
 883   list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
 884                                                      FeatureBMI,
 885                                                      FeatureTBM,
 886                                                      FeatureFMA,
 887                                                      FeatureFastBEXTR];
 888   list<SubtargetFeature> BdVer2InheritableFeatures =
 889     !listconcat(BdVer1InheritableFeatures, BdVer2AdditionalFeatures);
 890   list<SubtargetFeature> BdVer2Features = BdVer2InheritableFeatures;
 891
 892   // Steamroller
 893   list<SubtargetFeature> BdVer3AdditionalFeatures = [FeatureXSAVEOPT,
 894                                                      FeatureFSGSBase];
 895   list<SubtargetFeature> BdVer3InheritableFeatures =
 896     !listconcat(BdVer2InheritableFeatures, BdVer3AdditionalFeatures);
 897   list<SubtargetFeature> BdVer3Features = BdVer3InheritableFeatures;
 898
 899   // Excavator
 900   list<SubtargetFeature> BdVer4AdditionalFeatures = [FeatureAVX2,
 901                                                      FeatureBMI2,
 902                                                      FeatureMWAITX];
 903   list<SubtargetFeature> BdVer4InheritableFeatures =
 904     !listconcat(BdVer3InheritableFeatures, BdVer4AdditionalFeatures);
 905   list<SubtargetFeature> BdVer4Features = BdVer4InheritableFeatures;
 906
 907
 908   // AMD Zen Processors common ISAs
 909   list<SubtargetFeature> ZNFeatures = [FeatureADX,
 910                                        FeatureAES,
 911                                        FeatureAVX2,
 912                                        FeatureBMI,
 913                                        FeatureBMI2,
 914                                        FeatureCLFLUSHOPT,
 915                                        FeatureCLZERO,
 916                                        FeatureCMOV,
 917                                        Feature64Bit,
 918                                        FeatureCMPXCHG16B,
 919                                        FeatureF16C,
 920                                        FeatureFMA,
 921                                        FeatureFSGSBase,
 922                                        FeatureFXSR,
 923                                        FeatureNOPL,
 924                                        FeatureFastLZCNT,
 925                                        FeatureLAHFSAHF,
 926                                        FeatureLZCNT,
 927                                        FeatureFastBEXTR,
 928                                        FeatureFast15ByteNOP,
 929                                        FeatureBranchFusion,
 930                                        FeatureFastScalarShiftMasks,
 931                                        FeatureMMX,
 932                                        FeatureMOVBE,
 933                                        FeatureMWAITX,
 934                                        FeaturePCLMUL,
 935                                        FeaturePOPCNT,
 936                                        FeaturePRFCHW,
 937                                        FeatureRDRAND,
 938                                        FeatureRDSEED,
 939                                        FeatureSHA,
 940                                        FeatureSSE4A,
 941                                        FeatureSlowSHLD,
 942                                        FeatureX87,
 943                                        FeatureXSAVE,
 944                                        FeatureXSAVEC,
 945                                        FeatureXSAVEOPT,
 946                                        FeatureXSAVES];
 947   list<SubtargetFeature> ZN2AdditionalFeatures = [FeatureCLWB,
 948                                                   FeatureRDPID,
 949                                                   FeatureWBNOINVD];
 950   list<SubtargetFeature> ZN2Features =
 951     !listconcat(ZNFeatures, ZN2AdditionalFeatures);
 952 }
 953
 954 //===----------------------------------------------------------------------===//
 955 // X86 processors supported.
 956 //===----------------------------------------------------------------------===//
 957
 958 class Proc<string Name, list<SubtargetFeature> Features>
 959  : ProcessorModel<Name, GenericModel, Features>;
 960
 961 // NOTE: CMPXCHG8B is here for legacy compatbility so that it is only disabled
 962 // if i386/i486 is specifically requested.
 963 def : Proc<"generic",         [FeatureX87, FeatureSlowUAMem16,
 964                                FeatureCMPXCHG8B]>;
 965 def : Proc<"i386",            [FeatureX87, FeatureSlowUAMem16]>;
 966 def : Proc<"i486",            [FeatureX87, FeatureSlowUAMem16]>;
 967 def : Proc<"i586",            [FeatureX87, FeatureSlowUAMem16,
 968                                FeatureCMPXCHG8B]>;
 969 def : Proc<"pentium",         [FeatureX87, FeatureSlowUAMem16,
 970                                FeatureCMPXCHG8B]>;
 971 def : Proc<"pentium-mmx",     [FeatureX87, FeatureSlowUAMem16,
 972                                FeatureCMPXCHG8B, FeatureMMX]>;
 973
 974 def : Proc<"i686", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 975                     FeatureCMOV]>;
 976 def : Proc<"pentiumpro", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 977                           FeatureCMOV, FeatureNOPL]>;
 978
 979 def : Proc<"pentium2",        [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
 980                                FeatureMMX, FeatureCMOV, FeatureFXSR,
 981                                FeatureNOPL]>;
 982
 983 foreach P = ["pentium3", "pentium3m"] in {
 984   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,FeatureMMX,
 985                  FeatureSSE1, FeatureFXSR, FeatureNOPL, FeatureCMOV]>;
 986 }
 987
 988 // Enable the PostRAScheduler for SSE2 and SSE3 class cpus.
 989 // The intent is to enable it for pentium4 which is the current default
 990 // processor in a vanilla 32-bit clang compilation when no specific
 991 // architecture is specified.  This generally gives a nice performance
 992 // increase on silvermont, with largely neutral behavior on other
 993 // contemporary large core processors.
 994 // pentium-m, pentium4m, prescott and nocona are included as a preventative
 995 // measure to avoid performance surprises, in case clang's default cpu
 996 // changes slightly.
 997
 998 def : ProcessorModel<"pentium-m", GenericPostRAModel,
 999                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1000                       FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
1001                       FeatureCMOV]>;
1002
1003 foreach P = ["pentium4", "pentium4m"] in {
1004   def : ProcessorModel<P, GenericPostRAModel,
1005                        [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1006                         FeatureMMX, FeatureSSE2, FeatureFXSR, FeatureNOPL,
1007                         FeatureCMOV]>;
1008 }
1009
1010 // Intel Quark.
1011 def : Proc<"lakemont",        []>;
1012
1013 // Intel Core Duo.
1014 def : ProcessorModel<"yonah", SandyBridgeModel,
1015                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1016                       FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
1017                       FeatureCMOV]>;
1018
1019 // NetBurst.
1020 def : ProcessorModel<"prescott", GenericPostRAModel,
1021                      [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1022                       FeatureMMX, FeatureSSE3, FeatureFXSR, FeatureNOPL,
1023                       FeatureCMOV]>;
1024 def : ProcessorModel<"nocona", GenericPostRAModel, [
1025   FeatureX87,
1026   FeatureSlowUAMem16,
1027   FeatureCMPXCHG8B,
1028   FeatureCMOV,
1029   FeatureMMX,
1030   FeatureSSE3,
1031   FeatureFXSR,
1032   FeatureNOPL,
1033   Feature64Bit,
1034   FeatureCMPXCHG16B
1035 ]>;
1036
1037 // Intel Core 2 Solo/Duo.
1038 def : ProcessorModel<"core2", SandyBridgeModel, [
1039   FeatureX87,
1040   FeatureSlowUAMem16,
1041   FeatureCMPXCHG8B,
1042   FeatureCMOV,
1043   FeatureMMX,
1044   FeatureSSSE3,
1045   FeatureFXSR,
1046   FeatureNOPL,
1047   Feature64Bit,
1048   FeatureCMPXCHG16B,
1049   FeatureLAHFSAHF,
1050   FeatureMacroFusion
1051 ]>;
1052 def : ProcessorModel<"penryn", SandyBridgeModel, [
1053   FeatureX87,
1054   FeatureSlowUAMem16,
1055   FeatureCMPXCHG8B,
1056   FeatureCMOV,
1057   FeatureMMX,
1058   FeatureSSE41,
1059   FeatureFXSR,
1060   FeatureNOPL,
1061   Feature64Bit,
1062   FeatureCMPXCHG16B,
1063   FeatureLAHFSAHF,
1064   FeatureMacroFusion
1065 ]>;
1066
1067 // Atom CPUs.
1068 foreach P = ["bonnell", "atom"] in {
1069   def : ProcessorModel<P, AtomModel, ProcessorFeatures.AtomFeatures>;
1070 }
1071
1072 foreach P = ["silvermont", "slm"] in {
1073   def : ProcessorModel<P, SLMModel, ProcessorFeatures.SLMFeatures>;
1074 }
1075
1076 def : ProcessorModel<"goldmont", SLMModel, ProcessorFeatures.GLMFeatures>;
1077 def : ProcessorModel<"goldmont-plus", SLMModel, ProcessorFeatures.GLPFeatures>;
1078 def : ProcessorModel<"tremont", SLMModel, ProcessorFeatures.TRMFeatures>;
1079
1080 // "Arrandale" along with corei3 and corei5
1081 foreach P = ["nehalem", "corei7"] in {
1082   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.NHMFeatures>;
1083 }
1084
1085 // Westmere is the corei3/i5/i7 path from nehalem to sandybridge
1086 def : ProcessorModel<"westmere", SandyBridgeModel,
1087                      ProcessorFeatures.WSMFeatures>;
1088
1089 foreach P = ["sandybridge", "corei7-avx"] in {
1090   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.SNBFeatures>;
1091 }
1092
1093 foreach P = ["ivybridge", "core-avx-i"] in {
1094   def : ProcessorModel<P, SandyBridgeModel, ProcessorFeatures.IVBFeatures>;
1095 }
1096
1097 foreach P = ["haswell", "core-avx2"] in {
1098   def : ProcessorModel<P, HaswellModel, ProcessorFeatures.HSWFeatures>;
1099 }
1100
1101 def : ProcessorModel<"broadwell", BroadwellModel,
1102                      ProcessorFeatures.BDWFeatures>;
1103
1104 def : ProcessorModel<"skylake", SkylakeClientModel,
1105                      ProcessorFeatures.SKLFeatures>;
1106
1107 // FIXME: define KNL scheduler model
1108 def : ProcessorModel<"knl", HaswellModel, ProcessorFeatures.KNLFeatures>;
1109 def : ProcessorModel<"knm", HaswellModel, ProcessorFeatures.KNMFeatures>;
1110
1111 foreach P = ["skylake-avx512", "skx"] in {
1112   def : ProcessorModel<P, SkylakeServerModel, ProcessorFeatures.SKXFeatures>;
1113 }
1114
1115 def : ProcessorModel<"cascadelake", SkylakeServerModel,
1116                      ProcessorFeatures.CLXFeatures>;
1117 def : ProcessorModel<"cooperlake", SkylakeServerModel,
1118                      ProcessorFeatures.CPXFeatures>;
1119 def : ProcessorModel<"cannonlake", SkylakeServerModel,
1120                      ProcessorFeatures.CNLFeatures>;
1121 def : ProcessorModel<"icelake-client", SkylakeServerModel,
1122                      ProcessorFeatures.ICLFeatures>;
1123 def : ProcessorModel<"icelake-server", SkylakeServerModel,
1124                      ProcessorFeatures.ICXFeatures>;
1125 def : ProcessorModel<"tigerlake", SkylakeServerModel,
1126                      ProcessorFeatures.TGLFeatures>;
1127
1128 // AMD CPUs.
1129
1130 def : Proc<"k6",   [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1131                     FeatureMMX]>;
1132 def : Proc<"k6-2", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1133                     Feature3DNow]>;
1134 def : Proc<"k6-3", [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1135                                Feature3DNow]>;
1136
1137 foreach P = ["athlon", "athlon-tbird"] in {
1138   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
1139                  Feature3DNowA, FeatureNOPL, FeatureSlowSHLD]>;
1140 }
1141
1142 foreach P = ["athlon-4", "athlon-xp", "athlon-mp"] in {
1143   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureCMOV,
1144                  FeatureSSE1, Feature3DNowA, FeatureFXSR, FeatureNOPL,
1145                  FeatureSlowSHLD]>;
1146 }
1147
1148 foreach P = ["k8", "opteron", "athlon64", "athlon-fx"] in {
1149   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1150                  FeatureSSE2, Feature3DNowA, FeatureFXSR, FeatureNOPL,
1151                  Feature64Bit, FeatureSlowSHLD, FeatureCMOV,
1152                  FeatureFastScalarShiftMasks]>;
1153 }
1154
1155 foreach P = ["k8-sse3", "opteron-sse3", "athlon64-sse3"] in {
1156   def : Proc<P, [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B, FeatureSSE3,
1157                  Feature3DNowA, FeatureFXSR, FeatureNOPL, FeatureCMPXCHG16B,
1158                  FeatureSlowSHLD, FeatureCMOV, Feature64Bit,
1159                  FeatureFastScalarShiftMasks]>;
1160 }
1161
1162 foreach P = ["amdfam10", "barcelona"] in {
1163   def : Proc<P, ProcessorFeatures.BarcelonaFeatures>;
1164 }
1165
1166 // Bobcat
1167 def : Proc<"btver1", ProcessorFeatures.BtVer1Features>;
1168 // Jaguar
1169 def : ProcessorModel<"btver2", BtVer2Model, ProcessorFeatures.BtVer2Features>;
1170
1171 // Bulldozer
1172 def : ProcessorModel<"bdver1", BdVer2Model, ProcessorFeatures.BdVer1Features>;
1173 // Piledriver
1174 def : ProcessorModel<"bdver2", BdVer2Model, ProcessorFeatures.BdVer2Features>;
1175 // Steamroller
1176 def : Proc<"bdver3", ProcessorFeatures.BdVer3Features>;
1177 // Excavator
1178 def : Proc<"bdver4", ProcessorFeatures.BdVer4Features>;
1179
1180 def : ProcessorModel<"znver1", Znver1Model, ProcessorFeatures.ZNFeatures>;
1181 def : ProcessorModel<"znver2", Znver1Model, ProcessorFeatures.ZN2Features>;
1182
1183 def : Proc<"geode",           [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1184                                Feature3DNowA]>;
1185
1186 def : Proc<"winchip-c6",      [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;
1187 def : Proc<"winchip2",        [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1188 def : Proc<"c3",              [FeatureX87, FeatureSlowUAMem16, Feature3DNow]>;
1189 def : Proc<"c3-2",            [FeatureX87, FeatureSlowUAMem16, FeatureCMPXCHG8B,
1190                                FeatureMMX, FeatureSSE1, FeatureFXSR,
1191                                FeatureCMOV]>;
1192
1193 // We also provide a generic 64-bit specific x86 processor model which tries to
1194 // be good for modern chips without enabling instruction set encodings past the
1195 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
1196 // modern 64-bit x86 chip, and enables features that are generally beneficial.
1197 //
1198 // We currently use the Sandy Bridge model as the default scheduling model as
1199 // we use it across Nehalem, Westmere, Sandy Bridge, and Ivy Bridge which
1200 // covers a huge swath of x86 processors. If there are specific scheduling
1201 // knobs which need to be tuned differently for AMD chips, we might consider
1202 // forming a common base for them.
1203 def : ProcessorModel<"x86-64", SandyBridgeModel, [
1204   FeatureX87,
1205   FeatureCMPXCHG8B,
1206   FeatureCMOV,
1207   FeatureMMX,
1208   FeatureSSE2,
1209   FeatureFXSR,
1210   FeatureNOPL,
1211   Feature64Bit,
1212   FeatureSlow3OpsLEA,
1213   FeatureSlowIncDec,
1214   FeatureMacroFusion
1215 ]>;
1216
1217 //===----------------------------------------------------------------------===//
1218 // Calling Conventions
1219 //===----------------------------------------------------------------------===//
1220
1221 include "X86CallingConv.td"
1222
1223
1224 //===----------------------------------------------------------------------===//
1225 // Assembly Parser
1226 //===----------------------------------------------------------------------===//
1227
1228 def ATTAsmParserVariant : AsmParserVariant {
1229   int Variant = 0;
1230
1231   // Variant name.
1232   string Name = "att";
1233
1234   // Discard comments in assembly strings.
1235   string CommentDelimiter = "#";
1236
1237   // Recognize hard coded registers.
1238   string RegisterPrefix = "%";
1239 }
1240
1241 def IntelAsmParserVariant : AsmParserVariant {
1242   int Variant = 1;
1243
1244   // Variant name.
1245   string Name = "intel";
1246
1247   // Discard comments in assembly strings.
1248   string CommentDelimiter = ";";
1249
1250   // Recognize hard coded registers.
1251   string RegisterPrefix = "";
1252 }
1253
1254 //===----------------------------------------------------------------------===//
1255 // Assembly Printers
1256 //===----------------------------------------------------------------------===//
1257
1258 // The X86 target supports two different syntaxes for emitting machine code.
1259 // This is controlled by the -x86-asm-syntax={att|intel}
1260 def ATTAsmWriter : AsmWriter {
1261   string AsmWriterClassName  = "ATTInstPrinter";
1262   int Variant = 0;
1263 }
1264 def IntelAsmWriter : AsmWriter {
1265   string AsmWriterClassName  = "IntelInstPrinter";
1266   int Variant = 1;
1267 }
1268
1269 def X86 : Target {
1270   // Information about the instructions...
1271   let InstructionSet = X86InstrInfo;
1272   let AssemblyParserVariants = [ATTAsmParserVariant, IntelAsmParserVariant];
1273   let AssemblyWriters = [ATTAsmWriter, IntelAsmWriter];
1274   let AllowRegisterRenaming = 1;
1275 }
1276
1277 //===----------------------------------------------------------------------===//
1278 // Pfm Counters
1279 //===----------------------------------------------------------------------===//
1280
1281 include "X86PfmCounters.td"