lib/Target/X86/X86SchedBroadwell.td

   1 //=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the machine model for Broadwell to support instruction
  10 // scheduling and other instruction cost heuristics.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 def BroadwellModel : SchedMachineModel {
  15   // All x86 instructions are modeled as a single micro-op, and BW can decode 4
  16   // instructions per cycle.
  17   let IssueWidth = 4;
  18   let MicroOpBufferSize = 192; // Based on the reorder buffer.
  19   let LoadLatency = 5;
  20   let MispredictPenalty = 16;
  21
  22   // Based on the LSD (loop-stream detector) queue size and benchmarking data.
  23   let LoopMicroOpBufferSize = 50;
  24
  25   // This flag is set to allow the scheduler to assign a default model to
  26   // unrecognized opcodes.
  27   let CompleteModel = 0;
  28 }
  29
  30 let SchedModel = BroadwellModel in {
  31
  32 // Broadwell can issue micro-ops to 8 different ports in one cycle.
  33
  34 // Ports 0, 1, 5, and 6 handle all computation.
  35 // Port 4 gets the data half of stores. Store data can be available later than
  36 // the store address, but since we don't model the latency of stores, we can
  37 // ignore that.
  38 // Ports 2 and 3 are identical. They handle loads and the address half of
  39 // stores. Port 7 can handle address calculations.
  40 def BWPort0 : ProcResource<1>;
  41 def BWPort1 : ProcResource<1>;
  42 def BWPort2 : ProcResource<1>;
  43 def BWPort3 : ProcResource<1>;
  44 def BWPort4 : ProcResource<1>;
  45 def BWPort5 : ProcResource<1>;
  46 def BWPort6 : ProcResource<1>;
  47 def BWPort7 : ProcResource<1>;
  48
  49 // Many micro-ops are capable of issuing on multiple ports.
  50 def BWPort01  : ProcResGroup<[BWPort0, BWPort1]>;
  51 def BWPort23  : ProcResGroup<[BWPort2, BWPort3]>;
  52 def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
  53 def BWPort04  : ProcResGroup<[BWPort0, BWPort4]>;
  54 def BWPort05  : ProcResGroup<[BWPort0, BWPort5]>;
  55 def BWPort06  : ProcResGroup<[BWPort0, BWPort6]>;
  56 def BWPort15  : ProcResGroup<[BWPort1, BWPort5]>;
  57 def BWPort16  : ProcResGroup<[BWPort1, BWPort6]>;
  58 def BWPort56  : ProcResGroup<[BWPort5, BWPort6]>;
  59 def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
  60 def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
  61 def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
  62
  63 // 60 Entry Unified Scheduler
  64 def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
  65                               BWPort5, BWPort6, BWPort7]> {
  66   let BufferSize=60;
  67 }
  68
  69 // Integer division issued on port 0.
  70 def BWDivider : ProcResource<1>;
  71 // FP division and sqrt on port 0.
  72 def BWFPDivider : ProcResource<1>;
  73
  74 // Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
  75 // cycles after the memory operand.
  76 def : ReadAdvance<ReadAfterLd, 5>;
  77
  78 // Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
  79 // until 5/5/6 cycles after the memory operand.
  80 def : ReadAdvance<ReadAfterVecLd, 5>;
  81 def : ReadAdvance<ReadAfterVecXLd, 5>;
  82 def : ReadAdvance<ReadAfterVecYLd, 6>;
  83
  84 def : ReadAdvance<ReadInt2Fpu, 0>;
  85
  86 // Many SchedWrites are defined in pairs with and without a folded load.
  87 // Instructions with folded loads are usually micro-fused, so they only appear
  88 // as two micro-ops when queued in the reservation station.
  89 // This multiclass defines the resource usage for variants with and without
  90 // folded loads.
  91 multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
  92                           list<ProcResourceKind> ExePorts,
  93                           int Lat, list<int> Res = [1], int UOps = 1,
  94                           int LoadLat = 5> {
  95   // Register variant is using a single cycle on ExePort.
  96   def : WriteRes<SchedRW, ExePorts> {
  97     let Latency = Lat;
  98     let ResourceCycles = Res;
  99     let NumMicroOps = UOps;
 100   }
 101
 102   // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
 103   // the latency (default = 5).
 104   def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
 105     let Latency = !add(Lat, LoadLat);
 106     let ResourceCycles = !listconcat([1], Res);
 107     let NumMicroOps = !add(UOps, 1);
 108   }
 109 }
 110
 111 // A folded store needs a cycle on port 4 for the store data, and an extra port
 112 // 2/3/7 cycle to recompute the address.
 113 def : WriteRes<WriteRMW, [BWPort237,BWPort4]>;
 114
 115 // Arithmetic.
 116 defm : BWWriteResPair<WriteALU,    [BWPort0156], 1>; // Simple integer ALU op.
 117 defm : BWWriteResPair<WriteADC,    [BWPort06], 1>; // Integer ALU + flags op.
 118
 119 // Integer multiplication.
 120 defm : BWWriteResPair<WriteIMul8,     [BWPort1],   3>;
 121 defm : BWWriteResPair<WriteIMul16,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,2], 4>;
 122 defm : X86WriteRes<WriteIMul16Imm,    [BWPort1,BWPort0156], 4, [1,1], 2>;
 123 defm : X86WriteRes<WriteIMul16ImmLd,  [BWPort1,BWPort0156,BWPort23], 8, [1,1,1], 3>;
 124 defm : BWWriteResPair<WriteIMul16Reg, [BWPort1],   3>;
 125 defm : BWWriteResPair<WriteIMul32,    [BWPort1,BWPort06,BWPort0156], 4, [1,1,1], 3>;
 126 defm : BWWriteResPair<WriteIMul32Imm, [BWPort1],   3>;
 127 defm : BWWriteResPair<WriteIMul32Reg, [BWPort1],   3>;
 128 defm : BWWriteResPair<WriteIMul64,    [BWPort1,BWPort5], 4, [1,1], 2>;
 129 defm : BWWriteResPair<WriteIMul64Imm, [BWPort1],   3>;
 130 defm : BWWriteResPair<WriteIMul64Reg, [BWPort1],   3>;
 131 def : WriteRes<WriteIMulH, []> { let Latency = 3; }
 132
 133 // TODO: Why isn't the BWDivider used consistently?
 134 defm : X86WriteRes<WriteDiv8,      [BWPort0, BWDivider], 25, [1, 10], 1>;
 135 defm : X86WriteRes<WriteDiv16,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 136 defm : X86WriteRes<WriteDiv32,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 137 defm : X86WriteRes<WriteDiv64,     [BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156], 80, [7,7,3,3,1,11], 32>;
 138 defm : X86WriteRes<WriteDiv8Ld,    [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 139 defm : X86WriteRes<WriteDiv16Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 140 defm : X86WriteRes<WriteDiv32Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 141 defm : X86WriteRes<WriteDiv64Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 34, [2,2,2,1,1], 8>;
 142
 143 defm : X86WriteRes<WriteIDiv8,     [BWPort0, BWDivider], 25, [1,10], 1>;
 144 defm : X86WriteRes<WriteIDiv16,    [BWPort0, BWDivider], 25, [1,10], 1>;
 145 defm : X86WriteRes<WriteIDiv32,    [BWPort0, BWDivider], 25, [1,10], 1>;
 146 defm : X86WriteRes<WriteIDiv64,    [BWPort0, BWDivider], 25, [1,10], 1>;
 147 defm : X86WriteRes<WriteIDiv8Ld,   [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 148 defm : X86WriteRes<WriteIDiv16Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 149 defm : X86WriteRes<WriteIDiv32Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 150 defm : X86WriteRes<WriteIDiv64Ld,  [BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156], 35, [2,2,2,1,1], 8>;
 151
 152 defm : X86WriteRes<WriteCMPXCHG,[BWPort06, BWPort0156], 5, [2, 3], 5>;
 153 defm : X86WriteRes<WriteCMPXCHGRMW,[BWPort23, BWPort06, BWPort0156, BWPort237, BWPort4], 8, [1, 2, 1, 1, 1], 6>;
 154 defm : X86WriteRes<WriteBSWAP32,   [BWPort15], 1, [1], 1>;
 155 defm : X86WriteRes<WriteBSWAP64,   [BWPort06, BWPort15], 2, [1, 1], 2>;
 156 defm : X86WriteRes<WriteXCHG,      [BWPort0156], 2, [3], 3>;
 157
 158 defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 159
 160 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 161
 162 defm : BWWriteResPair<WriteCMOV,  [BWPort06], 1>; // Conditional move.
 163 defm : X86WriteRes<WriteFCMOV, [BWPort1], 3, [1], 1>; // x87 conditional move.
 164
 165 def  : WriteRes<WriteSETCC, [BWPort06]>; // Setcc.
 166 def  : WriteRes<WriteSETCCStore, [BWPort06,BWPort4,BWPort237]> {
 167   let Latency = 2;
 168   let NumMicroOps = 3;
 169 }
 170
 171 defm : X86WriteRes<WriteLAHFSAHF,        [BWPort06], 1, [1], 1>;
 172 defm : X86WriteRes<WriteBitTest,         [BWPort06], 1, [1], 1>; // Bit Test instrs
 173 defm : X86WriteRes<WriteBitTestImmLd,    [BWPort06,BWPort23], 6, [1,1], 2>;
 174 defm : X86WriteRes<WriteBitTestRegLd,    [BWPort0156,BWPort23], 6, [1,1], 2>;
 175 defm : X86WriteRes<WriteBitTestSet,      [BWPort06], 1, [1], 1>; // Bit Test + Set instrs
 176 defm : X86WriteRes<WriteBitTestSetImmLd, [BWPort06,BWPort23], 5, [1,1], 3>;
 177 defm : X86WriteRes<WriteBitTestSetRegLd, [BWPort0156,BWPort23], 5, [1,1], 2>;
 178
 179 // Bit counts.
 180 defm : BWWriteResPair<WriteBSF, [BWPort1], 3>;
 181 defm : BWWriteResPair<WriteBSR, [BWPort1], 3>;
 182 defm : BWWriteResPair<WriteLZCNT,          [BWPort1], 3>;
 183 defm : BWWriteResPair<WriteTZCNT,          [BWPort1], 3>;
 184 defm : BWWriteResPair<WritePOPCNT,         [BWPort1], 3>;
 185
 186 // Integer shifts and rotates.
 187 defm : BWWriteResPair<WriteShift,    [BWPort06],  1>;
 188 defm : BWWriteResPair<WriteShiftCL,  [BWPort06,BWPort0156],  3, [2,1], 3>;
 189 defm : BWWriteResPair<WriteRotate,   [BWPort06],  1, [1], 1>;
 190 defm : BWWriteResPair<WriteRotateCL, [BWPort06,BWPort0156],  3, [2,1], 3>;
 191
 192 // SHLD/SHRD.
 193 defm : X86WriteRes<WriteSHDrri, [BWPort1], 3, [1], 1>;
 194 defm : X86WriteRes<WriteSHDrrcl,[BWPort1,BWPort06,BWPort0156], 6, [1, 1, 2], 4>;
 195 defm : X86WriteRes<WriteSHDmri, [BWPort1,BWPort23,BWPort237,BWPort0156], 9, [1, 1, 1, 1], 4>;
 196 defm : X86WriteRes<WriteSHDmrcl,[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156], 11, [1, 1, 1, 1, 2], 6>;
 197
 198 // BMI1 BEXTR/BLS, BMI2 BZHI
 199 defm : BWWriteResPair<WriteBEXTR, [BWPort06,BWPort15], 2, [1,1], 2>;
 200 defm : BWWriteResPair<WriteBLS,   [BWPort15], 1>;
 201 defm : BWWriteResPair<WriteBZHI,  [BWPort15], 1>;
 202
 203 // Loads, stores, and moves, not folded with other operations.
 204 defm : X86WriteRes<WriteLoad,    [BWPort23], 5, [1], 1>;
 205 defm : X86WriteRes<WriteStore,   [BWPort237, BWPort4], 1, [1,1], 1>;
 206 defm : X86WriteRes<WriteStoreNT, [BWPort237, BWPort4], 1, [1,1], 2>;
 207 defm : X86WriteRes<WriteMove,    [BWPort0156], 1, [1], 1>;
 208
 209 // Idioms that clear a register, like xorps %xmm0, %xmm0.
 210 // These can often bypass execution ports completely.
 211 def : WriteRes<WriteZero,  []>;
 212
 213 // Treat misc copies as a move.
 214 def : InstRW<[WriteMove], (instrs COPY)>;
 215
 216 // Branches don't produce values, so they have no latency, but they still
 217 // consume resources. Indirect branches can fold loads.
 218 defm : BWWriteResPair<WriteJump,  [BWPort06],   1>;
 219
 220 // Floating point. This covers both scalar and vector operations.
 221 defm : X86WriteRes<WriteFLD0,          [BWPort01], 1, [1], 1>;
 222 defm : X86WriteRes<WriteFLD1,          [BWPort01], 1, [2], 2>;
 223 defm : X86WriteRes<WriteFLDC,          [BWPort01], 1, [2], 2>;
 224 defm : X86WriteRes<WriteFLoad,         [BWPort23], 5, [1], 1>;
 225 defm : X86WriteRes<WriteFLoadX,        [BWPort23], 5, [1], 1>;
 226 defm : X86WriteRes<WriteFLoadY,        [BWPort23], 6, [1], 1>;
 227 defm : X86WriteRes<WriteFMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 228 defm : X86WriteRes<WriteFMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 229 defm : X86WriteRes<WriteFStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 230 defm : X86WriteRes<WriteFStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 231 defm : X86WriteRes<WriteFStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 232 defm : X86WriteRes<WriteFStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 233 defm : X86WriteRes<WriteFStoreNTX,     [BWPort237,BWPort4], 1, [1,1], 2>;
 234 defm : X86WriteRes<WriteFStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 235
 236 defm : X86WriteRes<WriteFMaskedStore32,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 237 defm : X86WriteRes<WriteFMaskedStore32Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 238 defm : X86WriteRes<WriteFMaskedStore64,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 239 defm : X86WriteRes<WriteFMaskedStore64Y, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 240
 241 defm : X86WriteRes<WriteFMove,         [BWPort5], 1, [1], 1>;
 242 defm : X86WriteRes<WriteFMoveX,        [BWPort5], 1, [1], 1>;
 243 defm : X86WriteRes<WriteFMoveY,        [BWPort5], 1, [1], 1>;
 244
 245 defm : BWWriteResPair<WriteFAdd,    [BWPort1],  3, [1], 1, 5>; // Floating point add/sub.
 246 defm : BWWriteResPair<WriteFAddX,   [BWPort1],  3, [1], 1, 5>; // Floating point add/sub (XMM).
 247 defm : BWWriteResPair<WriteFAddY,   [BWPort1],  3, [1], 1, 6>; // Floating point add/sub (YMM/ZMM).
 248 defm : X86WriteResPairUnsupported<WriteFAddZ>;
 249 defm : BWWriteResPair<WriteFAdd64,  [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub.
 250 defm : BWWriteResPair<WriteFAdd64X, [BWPort1],  3, [1], 1, 5>; // Floating point double add/sub (XMM).
 251 defm : BWWriteResPair<WriteFAdd64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double add/sub (YMM/ZMM).
 252 defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
 253
 254 defm : BWWriteResPair<WriteFCmp,    [BWPort1],  3, [1], 1, 5>; // Floating point compare.
 255 defm : BWWriteResPair<WriteFCmpX,   [BWPort1],  3, [1], 1, 5>; // Floating point compare (XMM).
 256 defm : BWWriteResPair<WriteFCmpY,   [BWPort1],  3, [1], 1, 6>; // Floating point compare (YMM/ZMM).
 257 defm : X86WriteResPairUnsupported<WriteFCmpZ>;
 258 defm : BWWriteResPair<WriteFCmp64,  [BWPort1],  3, [1], 1, 5>; // Floating point double compare.
 259 defm : BWWriteResPair<WriteFCmp64X, [BWPort1],  3, [1], 1, 5>; // Floating point double compare (XMM).
 260 defm : BWWriteResPair<WriteFCmp64Y, [BWPort1],  3, [1], 1, 6>; // Floating point double compare (YMM/ZMM).
 261 defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
 262
 263 defm : BWWriteResPair<WriteFCom,    [BWPort1],  3>; // Floating point compare to flags.
 264
 265 defm : BWWriteResPair<WriteFMul,    [BWPort01], 3, [1], 1, 5>; // Floating point multiplication.
 266 defm : BWWriteResPair<WriteFMulX,   [BWPort01], 3, [1], 1, 5>; // Floating point multiplication (XMM).
 267 defm : BWWriteResPair<WriteFMulY,   [BWPort01], 3, [1], 1, 6>; // Floating point multiplication (YMM/ZMM).
 268 defm : X86WriteResPairUnsupported<WriteFMulZ>;
 269 defm : BWWriteResPair<WriteFMul64,  [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication.
 270 defm : BWWriteResPair<WriteFMul64X, [BWPort01], 3, [1], 1, 5>; // Floating point double multiplication (XMM).
 271 defm : BWWriteResPair<WriteFMul64Y, [BWPort01], 3, [1], 1, 6>; // Floating point double multiplication (YMM/ZMM).
 272 defm : X86WriteResPairUnsupported<WriteFMul64Z>;
 273
 274 //defm : BWWriteResPair<WriteFDiv,     [BWPort0,BWFPDivider], 11, [1,3], 1, 5>; // Floating point division.
 275 defm : BWWriteResPair<WriteFDivX,    [BWPort0,BWFPDivider], 11, [1,5], 1, 5>; // Floating point division (XMM).
 276 defm : BWWriteResPair<WriteFDivY,    [BWPort0,BWPort015,BWFPDivider], 17, [2,1,10], 3, 6>; // Floating point division (YMM).
 277 defm : X86WriteResPairUnsupported<WriteFDivZ>;
 278 //defm : BWWriteResPair<WriteFDiv64,   [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division.
 279 defm : BWWriteResPair<WriteFDiv64X,  [BWPort0,BWFPDivider], 14, [1,8], 1, 5>; // Floating point division (XMM).
 280 defm : BWWriteResPair<WriteFDiv64Y,  [BWPort0,BWPort015,BWFPDivider], 23, [2,1,16], 3, 6>; // Floating point division (YMM).
 281 defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
 282
 283 defm : X86WriteRes<WriteFSqrt,       [BWPort0,BWFPDivider], 11, [1,4], 1>; // Floating point square root.
 284 defm : X86WriteRes<WriteFSqrtLd,     [BWPort0,BWPort23,BWFPDivider], 16, [1,1,7], 2>;
 285 defm : BWWriteResPair<WriteFSqrtX,   [BWPort0,BWFPDivider], 11, [1,7], 1, 5>; // Floating point square root (XMM).
 286 defm : BWWriteResPair<WriteFSqrtY,   [BWPort0,BWPort015,BWFPDivider], 21, [2,1,14], 3, 6>; // Floating point square root (YMM).
 287 defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
 288 defm : X86WriteRes<WriteFSqrt64,     [BWPort0,BWFPDivider], 16, [1,8], 1>; // Floating point double square root.
 289 defm : X86WriteRes<WriteFSqrt64Ld,   [BWPort0,BWPort23,BWFPDivider], 21, [1,1,14], 2>;
 290 defm : BWWriteResPair<WriteFSqrt64X, [BWPort0,BWFPDivider], 16, [1,14],1, 5>; // Floating point double square root (XMM).
 291 defm : BWWriteResPair<WriteFSqrt64Y, [BWPort0,BWPort015,BWFPDivider], 29, [2,1,28], 3, 6>; // Floating point double square root (YMM).
 292 defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
 293 defm : BWWriteResPair<WriteFSqrt80,  [BWPort0,BWFPDivider], 23, [1,9]>; // Floating point long double square root.
 294
 295 defm : BWWriteResPair<WriteFRcp,   [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate.
 296 defm : BWWriteResPair<WriteFRcpX,  [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal estimate (XMM).
 297 defm : BWWriteResPair<WriteFRcpY,  [BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal estimate (YMM/ZMM).
 298 defm : X86WriteResPairUnsupported<WriteFRcpZ>;
 299
 300 defm : BWWriteResPair<WriteFRsqrt, [BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate.
 301 defm : BWWriteResPair<WriteFRsqrtX,[BWPort0],  5, [1], 1, 5>; // Floating point reciprocal square root estimate (XMM).
 302 defm : BWWriteResPair<WriteFRsqrtY,[BWPort0,BWPort015], 11, [2,1], 3, 6>; // Floating point reciprocal square root estimate (YMM/ZMM).
 303 defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
 304
 305 defm : BWWriteResPair<WriteFMA,    [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add.
 306 defm : BWWriteResPair<WriteFMAX,   [BWPort01], 5, [1], 1, 5>; // Fused Multiply Add (XMM).
 307 defm : BWWriteResPair<WriteFMAY,   [BWPort01], 5, [1], 1, 6>; // Fused Multiply Add (YMM/ZMM).
 308 defm : X86WriteResPairUnsupported<WriteFMAZ>;
 309 defm : BWWriteResPair<WriteDPPD,   [BWPort0,BWPort1,BWPort5],  9, [1,1,1], 3, 5>; // Floating point double dot product.
 310 defm : BWWriteResPair<WriteDPPS,   [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 5>; // Floating point single dot product.
 311 defm : BWWriteResPair<WriteDPPSY,  [BWPort0,BWPort1,BWPort5], 14, [2,1,1], 4, 6>; // Floating point single dot product (YMM).
 312 defm : X86WriteResPairUnsupported<WriteDPPSZ>;
 313 defm : BWWriteResPair<WriteFSign,     [BWPort5], 1>; // Floating point fabs/fchs.
 314 defm : X86WriteRes<WriteFRnd,            [BWPort23],  6, [1],   1>; // Floating point rounding.
 315 defm : X86WriteRes<WriteFRndY,           [BWPort23],  6, [1],   1>; // Floating point rounding (YMM/ZMM).
 316 defm : X86WriteResPairUnsupported<WriteFRndZ>;
 317 defm : X86WriteRes<WriteFRndLd,  [BWPort1,BWPort23], 11, [2,1], 3>;
 318 defm : X86WriteRes<WriteFRndYLd, [BWPort1,BWPort23], 12, [2,1], 3>;
 319 defm : BWWriteResPair<WriteFLogic,    [BWPort5], 1, [1], 1, 5>; // Floating point and/or/xor logicals.
 320 defm : BWWriteResPair<WriteFLogicY,   [BWPort5], 1, [1], 1, 6>; // Floating point and/or/xor logicals (YMM/ZMM).
 321 defm : X86WriteResPairUnsupported<WriteFLogicZ>;
 322 defm : BWWriteResPair<WriteFTest,     [BWPort0], 1, [1], 1, 5>; // Floating point TEST instructions.
 323 defm : BWWriteResPair<WriteFTestY,    [BWPort0], 1, [1], 1, 6>; // Floating point TEST instructions (YMM/ZMM).
 324 defm : X86WriteResPairUnsupported<WriteFTestZ>;
 325 defm : BWWriteResPair<WriteFShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector shuffles.
 326 defm : BWWriteResPair<WriteFShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector shuffles (YMM/ZMM).
 327 defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
 328 defm : BWWriteResPair<WriteFVarShuffle,  [BWPort5], 1, [1], 1, 5>; // Floating point vector variable shuffles.
 329 defm : BWWriteResPair<WriteFVarShuffleY, [BWPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles.
 330 defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
 331 defm : BWWriteResPair<WriteFBlend,  [BWPort015], 1, [1], 1, 5>; // Floating point vector blends.
 332 defm : BWWriteResPair<WriteFBlendY, [BWPort015], 1, [1], 1, 6>; // Floating point vector blends.
 333 defm : X86WriteResPairUnsupported<WriteFBlendZ>;
 334 defm : BWWriteResPair<WriteFVarBlend,  [BWPort5], 2, [2], 2, 5>; // Fp vector variable blends.
 335 defm : BWWriteResPair<WriteFVarBlendY, [BWPort5], 2, [2], 2, 6>; // Fp vector variable blends.
 336 defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
 337
 338 // FMA Scheduling helper class.
 339 // class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
 340
 341 // Vector integer operations.
 342 defm : X86WriteRes<WriteVecLoad,         [BWPort23], 5, [1], 1>;
 343 defm : X86WriteRes<WriteVecLoadX,        [BWPort23], 5, [1], 1>;
 344 defm : X86WriteRes<WriteVecLoadY,        [BWPort23], 6, [1], 1>;
 345 defm : X86WriteRes<WriteVecLoadNT,       [BWPort23], 5, [1], 1>;
 346 defm : X86WriteRes<WriteVecLoadNTY,      [BWPort23], 6, [1], 1>;
 347 defm : X86WriteRes<WriteVecMaskedLoad,   [BWPort23,BWPort5], 7, [1,2], 3>;
 348 defm : X86WriteRes<WriteVecMaskedLoadY,  [BWPort23,BWPort5], 8, [1,2], 3>;
 349 defm : X86WriteRes<WriteVecStore,        [BWPort237,BWPort4], 1, [1,1], 2>;
 350 defm : X86WriteRes<WriteVecStoreX,       [BWPort237,BWPort4], 1, [1,1], 2>;
 351 defm : X86WriteRes<WriteVecStoreY,       [BWPort237,BWPort4], 1, [1,1], 2>;
 352 defm : X86WriteRes<WriteVecStoreNT,      [BWPort237,BWPort4], 1, [1,1], 2>;
 353 defm : X86WriteRes<WriteVecStoreNTY,     [BWPort237,BWPort4], 1, [1,1], 2>;
 354 defm : X86WriteRes<WriteVecMaskedStore,  [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 355 defm : X86WriteRes<WriteVecMaskedStoreY, [BWPort0,BWPort4,BWPort237,BWPort15], 5, [1,1,1,1], 4>;
 356 defm : X86WriteRes<WriteVecMove,         [BWPort015], 1, [1], 1>;
 357 defm : X86WriteRes<WriteVecMoveX,        [BWPort015], 1, [1], 1>;
 358 defm : X86WriteRes<WriteVecMoveY,        [BWPort015], 1, [1], 1>;
 359 defm : X86WriteRes<WriteVecMoveToGpr,    [BWPort0], 1, [1], 1>;
 360 defm : X86WriteRes<WriteVecMoveFromGpr,  [BWPort5], 1, [1], 1>;
 361
 362 defm : X86WriteRes<WriteEMMS,            [BWPort01,BWPort15,BWPort015,BWPort0156], 31, [8,1,21,1], 31>;
 363
 364 defm : BWWriteResPair<WriteVecALU,   [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 365 defm : BWWriteResPair<WriteVecALUX,  [BWPort15], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
 366 defm : BWWriteResPair<WriteVecALUY,  [BWPort15], 1, [1], 1, 6>; // Vector integer ALU op, no logicals (YMM/ZMM).
 367 defm : X86WriteResPairUnsupported<WriteVecALUZ>;
 368 defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 369 defm : BWWriteResPair<WriteVecLogicX,[BWPort015], 1, [1], 1, 5>; // Vector integer and/or/xor.
 370 defm : BWWriteResPair<WriteVecLogicY,[BWPort015], 1, [1], 1, 6>; // Vector integer and/or/xor (YMM/ZMM).
 371 defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
 372 defm : BWWriteResPair<WriteVecTest,  [BWPort0,BWPort5], 2, [1,1], 2, 5>; // Vector integer TEST instructions.
 373 defm : BWWriteResPair<WriteVecTestY, [BWPort0,BWPort5], 4, [1,1], 2, 6>; // Vector integer TEST instructions (YMM/ZMM).
 374 defm : X86WriteResPairUnsupported<WriteVecTestZ>;
 375 defm : BWWriteResPair<WriteVecIMul,  [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 376 defm : BWWriteResPair<WriteVecIMulX, [BWPort0],  5, [1], 1, 5>; // Vector integer multiply.
 377 defm : BWWriteResPair<WriteVecIMulY, [BWPort0],  5, [1], 1, 6>; // Vector integer multiply.
 378 defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
 379 defm : BWWriteResPair<WritePMULLD,   [BWPort0], 10, [2], 2, 5>; // Vector PMULLD.
 380 defm : BWWriteResPair<WritePMULLDY,  [BWPort0], 10, [2], 2, 6>; // Vector PMULLD (YMM/ZMM).
 381 defm : X86WriteResPairUnsupported<WritePMULLDZ>;
 382 defm : BWWriteResPair<WriteShuffle,  [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 383 defm : BWWriteResPair<WriteShuffleX, [BWPort5], 1, [1], 1, 5>; // Vector shuffles.
 384 defm : BWWriteResPair<WriteShuffleY, [BWPort5], 1, [1], 1, 6>; // Vector shuffles (YMM/ZMM).
 385 defm : X86WriteResPairUnsupported<WriteShuffleZ>;
 386 defm : BWWriteResPair<WriteVarShuffle, [BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 387 defm : BWWriteResPair<WriteVarShuffleX,[BWPort5], 1, [1], 1, 5>; // Vector variable shuffles.
 388 defm : BWWriteResPair<WriteVarShuffleY,[BWPort5], 1, [1], 1, 6>; // Vector variable shuffles (YMM/ZMM).
 389 defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
 390 defm : BWWriteResPair<WriteBlend,  [BWPort5], 1, [1], 1, 5>; // Vector blends.
 391 defm : BWWriteResPair<WriteBlendY, [BWPort5], 1, [1], 1, 6>; // Vector blends (YMM/ZMM).
 392 defm : X86WriteResPairUnsupported<WriteBlendZ>;
 393 defm : BWWriteResPair<WriteVarBlend,  [BWPort5], 2, [2], 2, 5>; // Vector variable blends.
 394 defm : BWWriteResPair<WriteVarBlendY, [BWPort5], 2, [2], 2, 6>; // Vector variable blends (YMM/ZMM).
 395 defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
 396 defm : BWWriteResPair<WriteMPSAD,  [BWPort0, BWPort5], 7, [1, 2], 3, 5>; // Vector MPSAD.
 397 defm : BWWriteResPair<WriteMPSADY, [BWPort0, BWPort5], 7, [1, 2], 3, 6>; // Vector MPSAD.
 398 defm : X86WriteResPairUnsupported<WriteMPSADZ>;
 399 defm : BWWriteResPair<WritePSADBW,   [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 400 defm : BWWriteResPair<WritePSADBWX,  [BWPort0], 5, [1], 1, 5>; // Vector PSADBW.
 401 defm : BWWriteResPair<WritePSADBWY,  [BWPort0], 5, [1], 1, 6>; // Vector PSADBW (YMM/ZMM).
 402 defm : X86WriteResPairUnsupported<WritePSADBWZ>;
 403 defm : BWWriteResPair<WritePHMINPOS, [BWPort0], 5>; // Vector PHMINPOS.
 404
 405 // Vector integer shifts.
 406 defm : BWWriteResPair<WriteVecShift,     [BWPort0], 1, [1], 1, 5>;
 407 defm : BWWriteResPair<WriteVecShiftX,    [BWPort0,BWPort5],  2, [1,1], 2, 5>;
 408 defm : X86WriteRes<WriteVecShiftY,       [BWPort0,BWPort5],  4, [1,1], 2>;
 409 defm : X86WriteRes<WriteVecShiftYLd,     [BWPort0,BWPort23], 7, [1,1], 2>;
 410 defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
 411
 412 defm : BWWriteResPair<WriteVecShiftImm,  [BWPort0],  1, [1], 1, 5>;
 413 defm : BWWriteResPair<WriteVecShiftImmX, [BWPort0],  1, [1], 1, 5>; // Vector integer immediate shifts (XMM).
 414 defm : BWWriteResPair<WriteVecShiftImmY, [BWPort0],  1, [1], 1, 6>; // Vector integer immediate shifts (YMM/ZMM).
 415 defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
 416 defm : BWWriteResPair<WriteVarVecShift,  [BWPort0, BWPort5], 3, [2,1], 3, 5>; // Variable vector shifts.
 417 defm : BWWriteResPair<WriteVarVecShiftY, [BWPort0, BWPort5], 3, [2,1], 3, 6>; // Variable vector shifts (YMM/ZMM).
 418 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
 419
 420 // Vector insert/extract operations.
 421 def : WriteRes<WriteVecInsert, [BWPort5]> {
 422   let Latency = 2;
 423   let NumMicroOps = 2;
 424   let ResourceCycles = [2];
 425 }
 426 def : WriteRes<WriteVecInsertLd, [BWPort5,BWPort23]> {
 427   let Latency = 6;
 428   let NumMicroOps = 2;
 429 }
 430
 431 def : WriteRes<WriteVecExtract, [BWPort0,BWPort5]> {
 432   let Latency = 2;
 433   let NumMicroOps = 2;
 434 }
 435 def : WriteRes<WriteVecExtractSt, [BWPort4,BWPort5,BWPort237]> {
 436   let Latency = 2;
 437   let NumMicroOps = 3;
 438 }
 439
 440 // Conversion between integer and float.
 441 defm : BWWriteResPair<WriteCvtSS2I,   [BWPort1], 3>;
 442 defm : BWWriteResPair<WriteCvtPS2I,   [BWPort1], 3>;
 443 defm : BWWriteResPair<WriteCvtPS2IY,  [BWPort1], 3>;
 444 defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
 445 defm : BWWriteResPair<WriteCvtSD2I,   [BWPort1], 3>;
 446 defm : BWWriteResPair<WriteCvtPD2I,   [BWPort1], 3>;
 447 defm : BWWriteResPair<WriteCvtPD2IY,  [BWPort1], 3>;
 448 defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
 449
 450 defm : BWWriteResPair<WriteCvtI2SS,   [BWPort1], 4>;
 451 defm : BWWriteResPair<WriteCvtI2PS,   [BWPort1], 4>;
 452 defm : BWWriteResPair<WriteCvtI2PSY,  [BWPort1], 4>;
 453 defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
 454 defm : BWWriteResPair<WriteCvtI2SD,   [BWPort1], 4>;
 455 defm : BWWriteResPair<WriteCvtI2PD,   [BWPort1], 4>;
 456 defm : BWWriteResPair<WriteCvtI2PDY,  [BWPort1], 4>;
 457 defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
 458
 459 defm : BWWriteResPair<WriteCvtSS2SD,  [BWPort1], 3>;
 460 defm : BWWriteResPair<WriteCvtPS2PD,  [BWPort1], 3>;
 461 defm : BWWriteResPair<WriteCvtPS2PDY, [BWPort1], 3>;
 462 defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
 463 defm : BWWriteResPair<WriteCvtSD2SS,  [BWPort1], 3>;
 464 defm : BWWriteResPair<WriteCvtPD2PS,  [BWPort1], 3>;
 465 defm : BWWriteResPair<WriteCvtPD2PSY, [BWPort1], 3>;
 466 defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
 467
 468 defm : X86WriteRes<WriteCvtPH2PS,     [BWPort0,BWPort5], 2, [1,1], 2>;
 469 defm : X86WriteRes<WriteCvtPH2PSY,    [BWPort0,BWPort5], 2, [1,1], 2>;
 470 defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
 471 defm : X86WriteRes<WriteCvtPH2PSLd,  [BWPort0,BWPort23], 6, [1,1], 2>;
 472 defm : X86WriteRes<WriteCvtPH2PSYLd, [BWPort0,BWPort23], 6, [1,1], 2>;
 473 defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
 474
 475 defm : X86WriteRes<WriteCvtPS2PH,    [BWPort1,BWPort5], 4, [1,1], 2>;
 476 defm : X86WriteRes<WriteCvtPS2PHY,   [BWPort1,BWPort5], 6, [1,1], 2>;
 477 defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
 478 defm : X86WriteRes<WriteCvtPS2PHSt,  [BWPort1,BWPort4,BWPort237], 5, [1,1,1], 3>;
 479 defm : X86WriteRes<WriteCvtPS2PHYSt, [BWPort1,BWPort4,BWPort237], 7, [1,1,1], 3>;
 480 defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
 481
 482 // Strings instructions.
 483
 484 // Packed Compare Implicit Length Strings, Return Mask
 485 def : WriteRes<WritePCmpIStrM, [BWPort0]> {
 486   let Latency = 11;
 487   let NumMicroOps = 3;
 488   let ResourceCycles = [3];
 489 }
 490 def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
 491   let Latency = 16;
 492   let NumMicroOps = 4;
 493   let ResourceCycles = [3,1];
 494 }
 495
 496 // Packed Compare Explicit Length Strings, Return Mask
 497 def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
 498   let Latency = 19;
 499   let NumMicroOps = 9;
 500   let ResourceCycles = [4,3,1,1];
 501 }
 502 def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
 503   let Latency = 24;
 504   let NumMicroOps = 10;
 505   let ResourceCycles = [4,3,1,1,1];
 506 }
 507
 508 // Packed Compare Implicit Length Strings, Return Index
 509 def : WriteRes<WritePCmpIStrI, [BWPort0]> {
 510   let Latency = 11;
 511   let NumMicroOps = 3;
 512   let ResourceCycles = [3];
 513 }
 514 def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
 515   let Latency = 16;
 516   let NumMicroOps = 4;
 517   let ResourceCycles = [3,1];
 518 }
 519
 520 // Packed Compare Explicit Length Strings, Return Index
 521 def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
 522   let Latency = 18;
 523   let NumMicroOps = 8;
 524   let ResourceCycles = [4,3,1];
 525 }
 526 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
 527   let Latency = 23;
 528   let NumMicroOps = 9;
 529   let ResourceCycles = [4,3,1,1];
 530 }
 531
 532 // MOVMSK Instructions.
 533 def : WriteRes<WriteFMOVMSK,    [BWPort0]> { let Latency = 3; }
 534 def : WriteRes<WriteVecMOVMSK,  [BWPort0]> { let Latency = 3; }
 535 def : WriteRes<WriteVecMOVMSKY, [BWPort0]> { let Latency = 3; }
 536 def : WriteRes<WriteMMXMOVMSK,  [BWPort0]> { let Latency = 1; }
 537
 538 // AES instructions.
 539 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
 540   let Latency = 7;
 541   let NumMicroOps = 1;
 542   let ResourceCycles = [1];
 543 }
 544 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
 545   let Latency = 12;
 546   let NumMicroOps = 2;
 547   let ResourceCycles = [1,1];
 548 }
 549
 550 def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
 551   let Latency = 14;
 552   let NumMicroOps = 2;
 553   let ResourceCycles = [2];
 554 }
 555 def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
 556   let Latency = 19;
 557   let NumMicroOps = 3;
 558   let ResourceCycles = [2,1];
 559 }
 560
 561 def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
 562   let Latency = 29;
 563   let NumMicroOps = 11;
 564   let ResourceCycles = [2,7,2];
 565 }
 566 def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
 567   let Latency = 33;
 568   let NumMicroOps = 11;
 569   let ResourceCycles = [2,7,1,1];
 570 }
 571
 572 // Carry-less multiplication instructions.
 573 defm : BWWriteResPair<WriteCLMul,  [BWPort0], 5>;
 574
 575 // Catch-all for expensive system instructions.
 576 def : WriteRes<WriteSystem,     [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
 577
 578 // AVX2.
 579 defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector shuffles.
 580 defm : BWWriteResPair<WriteFVarShuffle256, [BWPort5], 3, [1], 1, 6>; // Fp 256-bit width vector variable shuffles.
 581 defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector shuffles.
 582 defm : BWWriteResPair<WriteVarShuffle256, [BWPort5], 3, [1], 1, 6>;  // 256-bit width vector variable shuffles.
 583
 584 // Old microcoded instructions that nobody use.
 585 def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
 586
 587 // Fence instructions.
 588 def : WriteRes<WriteFence,  [BWPort23, BWPort4]>;
 589
 590 // Load/store MXCSR.
 591 def : WriteRes<WriteLDMXCSR, [BWPort0,BWPort23,BWPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 592 def : WriteRes<WriteSTMXCSR, [BWPort4,BWPort5,BWPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
 593
 594 // Nop, not very useful expect it provides a model for nops!
 595 def : WriteRes<WriteNop, []>;
 596
 597 ////////////////////////////////////////////////////////////////////////////////
 598 // Horizontal add/sub  instructions.
 599 ////////////////////////////////////////////////////////////////////////////////
 600
 601 defm : BWWriteResPair<WriteFHAdd,   [BWPort1,BWPort5], 5, [1,2], 3, 5>;
 602 defm : BWWriteResPair<WriteFHAddY,  [BWPort1,BWPort5], 5, [1,2], 3, 6>;
 603 defm : BWWriteResPair<WritePHAdd,  [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 604 defm : BWWriteResPair<WritePHAddX, [BWPort5,BWPort15], 3, [2,1], 3, 5>;
 605 defm : BWWriteResPair<WritePHAddY, [BWPort5,BWPort15], 3, [2,1], 3, 6>;
 606
 607 // Remaining instrs.
 608
 609 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
 610   let Latency = 1;
 611   let NumMicroOps = 1;
 612   let ResourceCycles = [1];
 613 }
 614 def: InstRW<[BWWriteResGroup1], (instregex "VPSLLVQ(Y?)rr",
 615                                            "VPSRLVQ(Y?)rr")>;
 616
 617 def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
 618   let Latency = 1;
 619   let NumMicroOps = 1;
 620   let ResourceCycles = [1];
 621 }
 622 def: InstRW<[BWWriteResGroup2], (instregex "COM(P?)_FST0r",
 623                                            "UCOM_F(P?)r")>;
 624
 625 def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
 626   let Latency = 1;
 627   let NumMicroOps = 1;
 628   let ResourceCycles = [1];
 629 }
 630 def: InstRW<[BWWriteResGroup3], (instrs MMX_MOVQ2DQrr)>;
 631
 632 def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
 633   let Latency = 1;
 634   let NumMicroOps = 1;
 635   let ResourceCycles = [1];
 636 }
 637 def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
 638
 639 def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
 640   let Latency = 1;
 641   let NumMicroOps = 1;
 642   let ResourceCycles = [1];
 643 }
 644 def: InstRW<[BWWriteResGroup5], (instrs FINCSTP, FNOP)>;
 645
 646 def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
 647   let Latency = 1;
 648   let NumMicroOps = 1;
 649   let ResourceCycles = [1];
 650 }
 651 def: InstRW<[BWWriteResGroup6], (instrs CDQ, CQO)>;
 652
 653 def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
 654   let Latency = 1;
 655   let NumMicroOps = 1;
 656   let ResourceCycles = [1];
 657 }
 658 def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr")>;
 659
 660 def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
 661   let Latency = 1;
 662   let NumMicroOps = 1;
 663   let ResourceCycles = [1];
 664 }
 665 def: InstRW<[BWWriteResGroup8], (instregex "VPBLENDD(Y?)rri")>;
 666
 667 def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
 668   let Latency = 1;
 669   let NumMicroOps = 1;
 670   let ResourceCycles = [1];
 671 }
 672 def: InstRW<[BWWriteResGroup9], (instrs SGDT64m,
 673                                         SIDT64m,
 674                                         SMSW16m,
 675                                         STRm,
 676                                         SYSCALL)>;
 677
 678 def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
 679   let Latency = 1;
 680   let NumMicroOps = 2;
 681   let ResourceCycles = [1,1];
 682 }
 683 def: InstRW<[BWWriteResGroup10], (instrs FBSTPm)>;
 684 def: InstRW<[BWWriteResGroup10], (instregex "ST_FP(32|64|80)m")>;
 685
 686 def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
 687   let Latency = 2;
 688   let NumMicroOps = 2;
 689   let ResourceCycles = [2];
 690 }
 691 def: InstRW<[BWWriteResGroup12], (instrs FDECSTP)>;
 692
 693 def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
 694   let Latency = 2;
 695   let NumMicroOps = 2;
 696   let ResourceCycles = [2];
 697 }
 698 def: InstRW<[BWWriteResGroup14], (instrs LFENCE,
 699                                          MFENCE,
 700                                          WAIT,
 701                                          XGETBV)>;
 702
 703 def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
 704   let Latency = 2;
 705   let NumMicroOps = 2;
 706   let ResourceCycles = [1,1];
 707 }
 708 def: InstRW<[BWWriteResGroup15], (instregex "(V?)CVTPS2PDrr",
 709                                             "(V?)CVTSS2SDrr")>;
 710
 711 def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
 712   let Latency = 2;
 713   let NumMicroOps = 2;
 714   let ResourceCycles = [1,1];
 715 }
 716 def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
 717
 718 def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
 719   let Latency = 2;
 720   let NumMicroOps = 2;
 721   let ResourceCycles = [1,1];
 722 }
 723 def: InstRW<[BWWriteResGroup17], (instrs MMX_MOVDQ2Qrr)>;
 724
 725 def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
 726   let Latency = 2;
 727   let NumMicroOps = 2;
 728   let ResourceCycles = [1,1];
 729 }
 730 def: InstRW<[BWWriteResGroup18], (instrs SFENCE)>;
 731
 732 def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
 733   let Latency = 2;
 734   let NumMicroOps = 2;
 735   let ResourceCycles = [1,1];
 736 }
 737 def: InstRW<[BWWriteResGroup20], (instrs CWD,
 738                                          JCXZ, JECXZ, JRCXZ,
 739                                          ADC8i8, SBB8i8,
 740                                          ADC16i16, SBB16i16,
 741                                          ADC32i32, SBB32i32,
 742                                          ADC64i32, SBB64i32)>;
 743
 744 def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
 745   let Latency = 2;
 746   let NumMicroOps = 3;
 747   let ResourceCycles = [1,1,1];
 748 }
 749 def: InstRW<[BWWriteResGroup22], (instrs FNSTCW16m)>;
 750
 751 def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
 752   let Latency = 2;
 753   let NumMicroOps = 3;
 754   let ResourceCycles = [1,1,1];
 755 }
 756 def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
 757
 758 def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 759   let Latency = 2;
 760   let NumMicroOps = 3;
 761   let ResourceCycles = [1,1,1];
 762 }
 763 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
 764                                          STOSB, STOSL, STOSQ, STOSW)>;
 765 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr")>;
 766
 767 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
 768   let Latency = 3;
 769   let NumMicroOps = 1;
 770   let ResourceCycles = [1];
 771 }
 772 def: InstRW<[BWWriteResGroup27], (instrs MMX_CVTPI2PSirr)>;
 773 def: InstRW<[BWWriteResGroup27], (instregex "P(DEP|EXT)(32|64)rr",
 774                                             "(V?)CVTDQ2PS(Y?)rr")>;
 775
 776 def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
 777   let Latency = 3;
 778   let NumMicroOps = 1;
 779   let ResourceCycles = [1];
 780 }
 781 def: InstRW<[BWWriteResGroup28], (instrs VPBROADCASTBrr,
 782                                          VPBROADCASTWrr)>;
 783
 784 def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
 785   let Latency = 3;
 786   let NumMicroOps = 3;
 787   let ResourceCycles = [2,1];
 788 }
 789 def: InstRW<[BWWriteResGroup33], (instrs MMX_PACKSSDWirr,
 790                                          MMX_PACKSSWBirr,
 791                                          MMX_PACKUSWBirr)>;
 792
 793 def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
 794   let Latency = 3;
 795   let NumMicroOps = 3;
 796   let ResourceCycles = [1,2];
 797 }
 798 def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
 799
 800 def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
 801   let Latency = 3;
 802   let NumMicroOps = 3;
 803   let ResourceCycles = [1,2];
 804 }
 805 def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r(1|i)",
 806                                             "RCR(8|16|32|64)r(1|i)")>;
 807
 808 def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
 809   let Latency = 3;
 810   let NumMicroOps = 4;
 811   let ResourceCycles = [1,1,1,1];
 812 }
 813 def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
 814
 815 def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
 816   let Latency = 3;
 817   let NumMicroOps = 4;
 818   let ResourceCycles = [1,1,1,1];
 819 }
 820 def: InstRW<[BWWriteResGroup38], (instrs CALL64pcrel32)>;
 821
 822 def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
 823   let Latency = 4;
 824   let NumMicroOps = 2;
 825   let ResourceCycles = [1,1];
 826 }
 827 def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVT(T?)SD2SI64rr",
 828                                             "(V?)CVT(T?)SD2SIrr",
 829                                             "(V?)CVT(T?)SS2SI64rr",
 830                                             "(V?)CVT(T?)SS2SIrr")>;
 831
 832 def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
 833   let Latency = 4;
 834   let NumMicroOps = 2;
 835   let ResourceCycles = [1,1];
 836 }
 837 def: InstRW<[BWWriteResGroup40], (instrs VCVTPS2PDYrr)>;
 838
 839 def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
 840   let Latency = 4;
 841   let NumMicroOps = 2;
 842   let ResourceCycles = [1,1];
 843 }
 844 def: InstRW<[BWWriteResGroup41], (instrs FNSTSW16r)>;
 845
 846 def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
 847   let Latency = 4;
 848   let NumMicroOps = 2;
 849   let ResourceCycles = [1,1];
 850 }
 851 def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDirr)>;
 852 def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIirr",
 853                                             "MMX_CVT(T?)PS2PIirr",
 854                                             "(V?)CVTDQ2PDrr",
 855                                             "(V?)CVTPD2PSrr",
 856                                             "(V?)CVTSD2SSrr",
 857                                             "(V?)CVTSI642SDrr",
 858                                             "(V?)CVTSI2SDrr",
 859                                             "(V?)CVTSI2SSrr",
 860                                             "(V?)CVT(T?)PD2DQrr")>;
 861
 862 def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
 863   let Latency = 4;
 864   let NumMicroOps = 3;
 865   let ResourceCycles = [1,1,1];
 866 }
 867 def: InstRW<[BWWriteResGroup43], (instrs FNSTSWm)>;
 868
 869 def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
 870   let Latency = 4;
 871   let NumMicroOps = 3;
 872   let ResourceCycles = [1,1,1];
 873 }
 874 def: InstRW<[BWWriteResGroup44], (instregex "IST(T?)_FP(16|32|64)m",
 875                                             "IST_F(16|32)m")>;
 876
 877 def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
 878   let Latency = 4;
 879   let NumMicroOps = 4;
 880   let ResourceCycles = [4];
 881 }
 882 def: InstRW<[BWWriteResGroup45], (instrs FNCLEX)>;
 883
 884 def BWWriteResGroup46 : SchedWriteRes<[]> {
 885   let Latency = 0;
 886   let NumMicroOps = 4;
 887   let ResourceCycles = [];
 888 }
 889 def: InstRW<[BWWriteResGroup46], (instrs VZEROUPPER)>;
 890
 891 def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
 892   let Latency = 5;
 893   let NumMicroOps = 1;
 894   let ResourceCycles = [1];
 895 }
 896 def: InstRW<[BWWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
 897
 898 def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
 899   let Latency = 5;
 900   let NumMicroOps = 1;
 901   let ResourceCycles = [1];
 902 }
 903 def: InstRW<[BWWriteResGroup49], (instregex "MOVSX(16|32|64)rm(8|16|32)",
 904                                             "MOVZX(16|32|64)rm(8|16)")>;
 905 def: InstRW<[BWWriteResGroup49], (instrs VBROADCASTSSrm,
 906                                          VMOVDDUPrm, MOVDDUPrm,
 907                                          VMOVSHDUPrm, MOVSHDUPrm,
 908                                          VMOVSLDUPrm, MOVSLDUPrm,
 909                                          VPBROADCASTDrm,
 910                                          VPBROADCASTQrm)>;
 911
 912 def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
 913   let Latency = 5;
 914   let NumMicroOps = 3;
 915   let ResourceCycles = [1,2];
 916 }
 917 def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr")>;
 918
 919 def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
 920   let Latency = 5;
 921   let NumMicroOps = 3;
 922   let ResourceCycles = [1,1,1];
 923 }
 924 def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
 925
 926 def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
 927   let Latency = 5;
 928   let NumMicroOps = 5;
 929   let ResourceCycles = [1,4];
 930 }
 931 def: InstRW<[BWWriteResGroup54], (instrs PAUSE)>;
 932
 933 def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
 934   let Latency = 5;
 935   let NumMicroOps = 5;
 936   let ResourceCycles = [1,4];
 937 }
 938 def: InstRW<[BWWriteResGroup55], (instrs XSETBV)>;
 939
 940 def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
 941   let Latency = 5;
 942   let NumMicroOps = 6;
 943   let ResourceCycles = [1,1,4];
 944 }
 945 def: InstRW<[BWWriteResGroup57], (instregex "PUSHF(16|64)")>;
 946
 947 def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
 948   let Latency = 6;
 949   let NumMicroOps = 1;
 950   let ResourceCycles = [1];
 951 }
 952 def: InstRW<[BWWriteResGroup58], (instregex "LD_F(32|64|80)m")>;
 953 def: InstRW<[BWWriteResGroup58], (instrs VBROADCASTF128,
 954                                          VBROADCASTI128,
 955                                          VBROADCASTSDYrm,
 956                                          VBROADCASTSSYrm,
 957                                          VMOVDDUPYrm,
 958                                          VMOVSHDUPYrm,
 959                                          VMOVSLDUPYrm,
 960                                          VPBROADCASTDYrm,
 961                                          VPBROADCASTQYrm)>;
 962
 963 def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
 964   let Latency = 6;
 965   let NumMicroOps = 2;
 966   let ResourceCycles = [1,1];
 967 }
 968 def: InstRW<[BWWriteResGroup59], (instrs CVTPS2PDrm, VCVTPS2PDrm,
 969                                          CVTSS2SDrm, VCVTSS2SDrm,
 970                                          CVTSS2SDrm_Int, VCVTSS2SDrm_Int,
 971                                          VPSLLVQrm,
 972                                          VPSRLVQrm)>;
 973
 974 def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
 975   let Latency = 6;
 976   let NumMicroOps = 2;
 977   let ResourceCycles = [1,1];
 978 }
 979 def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
 980                                          VCVTPD2PSYrr,
 981                                          VCVTPD2DQYrr,
 982                                          VCVTTPD2DQYrr)>;
 983
 984 def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
 985   let Latency = 6;
 986   let NumMicroOps = 2;
 987   let ResourceCycles = [1,1];
 988 }
 989 def: InstRW<[BWWriteResGroup62], (instrs FARJMP64)>;
 990 def: InstRW<[BWWriteResGroup62], (instregex "JMP(16|32|64)m")>;
 991
 992 def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
 993   let Latency = 6;
 994   let NumMicroOps = 2;
 995   let ResourceCycles = [1,1];
 996 }
 997 def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
 998                                             "MOVBE(16|32|64)rm")>;
 999
1000 def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1001   let Latency = 6;
1002   let NumMicroOps = 2;
1003   let ResourceCycles = [1,1];
1004 }
1005 def: InstRW<[BWWriteResGroup65], (instrs VINSERTF128rm,
1006                                          VINSERTI128rm,
1007                                          VPBLENDDrmi)>;
1008
1009 def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1010   let Latency = 6;
1011   let NumMicroOps = 2;
1012   let ResourceCycles = [1,1];
1013 }
1014 def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
1015 def: InstRW<[BWWriteResGroup66], (instregex "POP(16|32|64)rmr")>;
1016
1017 def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1018   let Latency = 6;
1019   let NumMicroOps = 4;
1020   let ResourceCycles = [1,1,1,1];
1021 }
1022 def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1023
1024 def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1025   let Latency = 6;
1026   let NumMicroOps = 4;
1027   let ResourceCycles = [1,1,1,1];
1028 }
1029 def: InstRW<[BWWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
1030                                             "SHL(8|16|32|64)m(1|i)",
1031                                             "SHR(8|16|32|64)m(1|i)")>;
1032
1033 def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1034   let Latency = 6;
1035   let NumMicroOps = 4;
1036   let ResourceCycles = [1,1,1,1];
1037 }
1038 def: InstRW<[BWWriteResGroup70], (instregex "POP(16|32|64)rmm",
1039                                             "PUSH(16|32|64)rmm")>;
1040
1041 def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1042   let Latency = 6;
1043   let NumMicroOps = 6;
1044   let ResourceCycles = [1,5];
1045 }
1046 def: InstRW<[BWWriteResGroup71], (instrs STD)>;
1047
1048 def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1049   let Latency = 7;
1050   let NumMicroOps = 2;
1051   let ResourceCycles = [1,1];
1052 }
1053 def: InstRW<[BWWriteResGroup73], (instrs VPSLLVQYrm,
1054                                          VPSRLVQYrm)>;
1055
1056 def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1057   let Latency = 7;
1058   let NumMicroOps = 2;
1059   let ResourceCycles = [1,1];
1060 }
1061 def: InstRW<[BWWriteResGroup74], (instregex "FCOM(P?)(32|64)m")>;
1062
1063 def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1064   let Latency = 7;
1065   let NumMicroOps = 2;
1066   let ResourceCycles = [1,1];
1067 }
1068 def: InstRW<[BWWriteResGroup77], (instrs VPBLENDDYrmi)>;
1069
1070 def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1071   let Latency = 7;
1072   let NumMicroOps = 3;
1073   let ResourceCycles = [2,1];
1074 }
1075 def: InstRW<[BWWriteResGroup79], (instrs MMX_PACKSSDWirm,
1076                                          MMX_PACKSSWBirm,
1077                                          MMX_PACKUSWBirm)>;
1078
1079 def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1080   let Latency = 7;
1081   let NumMicroOps = 3;
1082   let ResourceCycles = [1,2];
1083 }
1084 def: InstRW<[BWWriteResGroup80], (instrs LEAVE, LEAVE64,
1085                                          SCASB, SCASL, SCASQ, SCASW)>;
1086
1087 def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1088   let Latency = 7;
1089   let NumMicroOps = 3;
1090   let ResourceCycles = [1,1,1];
1091 }
1092 def: InstRW<[BWWriteResGroup82], (instrs FLDCW16m)>;
1093
1094 def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1095   let Latency = 7;
1096   let NumMicroOps = 3;
1097   let ResourceCycles = [1,1,1];
1098 }
1099 def: InstRW<[BWWriteResGroup84], (instrs LRETQ, RETQ)>;
1100
1101 def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1102   let Latency = 7;
1103   let NumMicroOps = 5;
1104   let ResourceCycles = [1,1,1,2];
1105 }
1106 def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m(1|i)",
1107                                             "ROR(8|16|32|64)m(1|i)")>;
1108
1109 def BWWriteResGroup87_1 : SchedWriteRes<[BWPort06]> {
1110   let Latency = 2;
1111   let NumMicroOps = 2;
1112   let ResourceCycles = [2];
1113 }
1114 def: InstRW<[BWWriteResGroup87_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1115                                            ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1116
1117 def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1118   let Latency = 7;
1119   let NumMicroOps = 5;
1120   let ResourceCycles = [1,1,1,2];
1121 }
1122 def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
1123
1124 def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1125   let Latency = 7;
1126   let NumMicroOps = 5;
1127   let ResourceCycles = [1,1,1,1,1];
1128 }
1129 def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m")>;
1130 def: InstRW<[BWWriteResGroup89], (instrs FARCALL64)>;
1131
1132 def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1133   let Latency = 7;
1134   let NumMicroOps = 7;
1135   let ResourceCycles = [2,2,1,2];
1136 }
1137 def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
1138
1139 def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1140   let Latency = 8;
1141   let NumMicroOps = 2;
1142   let ResourceCycles = [1,1];
1143 }
1144 def: InstRW<[BWWriteResGroup91], (instrs MMX_CVTPI2PSirm,
1145                                          CVTDQ2PSrm,
1146                                          VCVTDQ2PSrm)>;
1147 def: InstRW<[BWWriteResGroup91], (instregex "P(DEP|EXT)(32|64)rm")>;
1148
1149 def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1150   let Latency = 8;
1151   let NumMicroOps = 2;
1152   let ResourceCycles = [1,1];
1153 }
1154 def: InstRW<[BWWriteResGroup92], (instrs VPMOVSXBDYrm,
1155                                          VPMOVSXBQYrm,
1156                                          VPMOVSXBWYrm,
1157                                          VPMOVSXDQYrm,
1158                                          VPMOVSXWDYrm,
1159                                          VPMOVSXWQYrm,
1160                                          VPMOVZXWDYrm)>;
1161
1162 def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
1163   let Latency = 8;
1164   let NumMicroOps = 5;
1165   let ResourceCycles = [1,1,1,2];
1166 }
1167 def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m(1|i)",
1168                                             "RCR(8|16|32|64)m(1|i)")>;
1169
1170 def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1171   let Latency = 8;
1172   let NumMicroOps = 6;
1173   let ResourceCycles = [1,1,1,3];
1174 }
1175 def: InstRW<[BWWriteResGroup99], (instregex "XCHG(8|16|32|64)rm")>;
1176
1177 def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1178   let Latency = 8;
1179   let NumMicroOps = 6;
1180   let ResourceCycles = [1,1,1,2,1];
1181 }
1182 def : SchedAlias<WriteADCRMW, BWWriteResGroup100>;
1183 def: InstRW<[BWWriteResGroup100], (instregex "ROL(8|16|32|64)mCL",
1184                                              "ROR(8|16|32|64)mCL",
1185                                              "SAR(8|16|32|64)mCL",
1186                                              "SHL(8|16|32|64)mCL",
1187                                              "SHR(8|16|32|64)mCL")>;
1188
1189 def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
1190   let Latency = 9;
1191   let NumMicroOps = 2;
1192   let ResourceCycles = [1,1];
1193 }
1194 def: InstRW<[BWWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1195                                              "ILD_F(16|32|64)m")>;
1196 def: InstRW<[BWWriteResGroup101], (instrs VCVTPS2DQYrm,
1197                                           VCVTTPS2DQYrm)>;
1198
1199 def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1200   let Latency = 9;
1201   let NumMicroOps = 3;
1202   let ResourceCycles = [1,1,1];
1203 }
1204 def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSS2SI(64)?rm",
1205                                              "(V?)CVT(T?)SD2SI64rm",
1206                                              "(V?)CVT(T?)SD2SIrm",
1207                                              "VCVTTSS2SI64rm",
1208                                              "(V?)CVTTSS2SIrm")>;
1209
1210 def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1211   let Latency = 9;
1212   let NumMicroOps = 3;
1213   let ResourceCycles = [1,1,1];
1214 }
1215 def: InstRW<[BWWriteResGroup106], (instrs VCVTPS2PDYrm)>;
1216
1217 def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1218   let Latency = 9;
1219   let NumMicroOps = 3;
1220   let ResourceCycles = [1,1,1];
1221 }
1222 def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
1223                                           CVTPD2DQrm,
1224                                           CVTTPD2DQrm,
1225                                           MMX_CVTPI2PDirm)>;
1226 def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIirm",
1227                                              "(V?)CVTDQ2PDrm",
1228                                              "(V?)CVTSD2SSrm")>;
1229
1230 def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
1231   let Latency = 9;
1232   let NumMicroOps = 3;
1233   let ResourceCycles = [1,1,1];
1234 }
1235 def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
1236                                              "VPBROADCASTW(Y?)rm")>;
1237
1238 def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1239   let Latency = 9;
1240   let NumMicroOps = 5;
1241   let ResourceCycles = [1,1,3];
1242 }
1243 def: InstRW<[BWWriteResGroup112], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>;
1244
1245 def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1246   let Latency = 9;
1247   let NumMicroOps = 5;
1248   let ResourceCycles = [1,2,1,1];
1249 }
1250 def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
1251                                              "LSL(16|32|64)rm")>;
1252
1253 def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
1254   let Latency = 10;
1255   let NumMicroOps = 2;
1256   let ResourceCycles = [1,1];
1257 }
1258 def: InstRW<[BWWriteResGroup115], (instregex "(V?)PCMPGTQrm")>;
1259
1260 def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
1261   let Latency = 10;
1262   let NumMicroOps = 3;
1263   let ResourceCycles = [2,1];
1264 }
1265 def: InstRW<[BWWriteResGroup117], (instregex "FICOM(P?)(16|32)m")>;
1266
1267 def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
1268   let Latency = 10;
1269   let NumMicroOps = 4;
1270   let ResourceCycles = [1,1,1,1];
1271 }
1272 def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
1273
1274 def BWWriteResGroup122_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1275   let Latency = 11;
1276   let NumMicroOps = 1;
1277   let ResourceCycles = [1,3]; // Really 2.5 cycle throughput
1278 }
1279 def : SchedAlias<WriteFDiv, BWWriteResGroup122_1>; // TODO - convert to ZnWriteResFpuPair
1280
1281 def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
1282   let Latency = 11;
1283   let NumMicroOps = 2;
1284   let ResourceCycles = [1,1];
1285 }
1286 def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
1287 def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
1288
1289 def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
1290   let Latency = 11;
1291   let NumMicroOps = 3;
1292   let ResourceCycles = [1,1,1];
1293 }
1294 def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
1295
1296 def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1297   let Latency = 11;
1298   let NumMicroOps = 7;
1299   let ResourceCycles = [2,2,3];
1300 }
1301 def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
1302                                              "RCR(16|32|64)rCL")>;
1303
1304 def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1305   let Latency = 11;
1306   let NumMicroOps = 9;
1307   let ResourceCycles = [1,4,1,3];
1308 }
1309 def: InstRW<[BWWriteResGroup132], (instrs RCL8rCL)>;
1310
1311 def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
1312   let Latency = 11;
1313   let NumMicroOps = 11;
1314   let ResourceCycles = [2,9];
1315 }
1316 def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
1317 def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
1318
1319 def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
1320   let Latency = 12;
1321   let NumMicroOps = 3;
1322   let ResourceCycles = [2,1];
1323 }
1324 def: InstRW<[BWWriteResGroup135], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1325
1326 def BWWriteResGroup139_1 : SchedWriteRes<[BWPort0,BWFPDivider]> {
1327   let Latency = 14;
1328   let NumMicroOps = 1;
1329   let ResourceCycles = [1,4];
1330 }
1331 def : SchedAlias<WriteFDiv64, BWWriteResGroup139_1>; // TODO - convert to ZnWriteResFpuPair
1332
1333 def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1334   let Latency = 14;
1335   let NumMicroOps = 3;
1336   let ResourceCycles = [1,1,1];
1337 }
1338 def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI(16|32)m")>;
1339
1340 def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
1341   let Latency = 14;
1342   let NumMicroOps = 8;
1343   let ResourceCycles = [2,2,1,3];
1344 }
1345 def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
1346
1347 def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
1348   let Latency = 14;
1349   let NumMicroOps = 10;
1350   let ResourceCycles = [2,3,1,4];
1351 }
1352 def: InstRW<[BWWriteResGroup145], (instrs RCR8rCL)>;
1353
1354 def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
1355   let Latency = 14;
1356   let NumMicroOps = 12;
1357   let ResourceCycles = [2,1,4,5];
1358 }
1359 def: InstRW<[BWWriteResGroup146], (instrs XCH_F)>;
1360
1361 def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
1362   let Latency = 15;
1363   let NumMicroOps = 1;
1364   let ResourceCycles = [1];
1365 }
1366 def: InstRW<[BWWriteResGroup147], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1367
1368 def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1369   let Latency = 15;
1370   let NumMicroOps = 10;
1371   let ResourceCycles = [1,1,1,4,1,2];
1372 }
1373 def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
1374
1375 def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1376   let Latency = 16;
1377   let NumMicroOps = 2;
1378   let ResourceCycles = [1,1,5];
1379 }
1380 def : SchedAlias<WriteFDivLd, BWWriteResGroup150>; // TODO - convert to ZnWriteResFpuPair
1381
1382 def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1383   let Latency = 16;
1384   let NumMicroOps = 14;
1385   let ResourceCycles = [1,1,1,4,2,5];
1386 }
1387 def: InstRW<[BWWriteResGroup153], (instrs CMPXCHG8B)>;
1388
1389 def BWWriteResGroup154 : SchedWriteRes<[BWPort5,BWPort6]> {
1390   let Latency = 8;
1391   let NumMicroOps = 20;
1392   let ResourceCycles = [1,1];
1393 }
1394 def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
1395
1396 def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
1397   let Latency = 18;
1398   let NumMicroOps = 8;
1399   let ResourceCycles = [1,1,1,5];
1400 }
1401 def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
1402 def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
1403
1404 def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
1405   let Latency = 18;
1406   let NumMicroOps = 11;
1407   let ResourceCycles = [2,1,1,3,1,3];
1408 }
1409 def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
1410
1411 def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23,BWFPDivider]> {
1412   let Latency = 19;
1413   let NumMicroOps = 2;
1414   let ResourceCycles = [1,1,8];
1415 }
1416 def : SchedAlias<WriteFDiv64Ld, BWWriteResGroup161>; // TODO - convert to ZnWriteResFpuPair
1417
1418 def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
1419   let Latency = 20;
1420   let NumMicroOps = 1;
1421   let ResourceCycles = [1];
1422 }
1423 def: InstRW<[BWWriteResGroup165], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1424
1425 def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1426   let Latency = 20;
1427   let NumMicroOps = 8;
1428   let ResourceCycles = [1,1,1,1,1,1,2];
1429 }
1430 def: InstRW<[BWWriteResGroup167], (instrs INSB, INSL, INSW)>;
1431
1432 def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
1433   let Latency = 21;
1434   let NumMicroOps = 2;
1435   let ResourceCycles = [1,1];
1436 }
1437 def: InstRW<[BWWriteResGroup169], (instregex "DIV_F(32|64)m")>;
1438
1439 def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1440   let Latency = 21;
1441   let NumMicroOps = 19;
1442   let ResourceCycles = [2,1,4,1,1,4,6];
1443 }
1444 def: InstRW<[BWWriteResGroup171], (instrs CMPXCHG16B)>;
1445
1446 def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1447   let Latency = 22;
1448   let NumMicroOps = 18;
1449   let ResourceCycles = [1,1,16];
1450 }
1451 def: InstRW<[BWWriteResGroup172], (instrs POPF64)>;
1452
1453 def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1454   let Latency = 23;
1455   let NumMicroOps = 19;
1456   let ResourceCycles = [3,1,15];
1457 }
1458 def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
1459
1460 def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1461   let Latency = 24;
1462   let NumMicroOps = 3;
1463   let ResourceCycles = [1,1,1];
1464 }
1465 def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI(16|32)m")>;
1466
1467 def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
1468   let Latency = 26;
1469   let NumMicroOps = 2;
1470   let ResourceCycles = [1,1];
1471 }
1472 def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F(32|64)m")>;
1473
1474 def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
1475   let Latency = 29;
1476   let NumMicroOps = 3;
1477   let ResourceCycles = [1,1,1];
1478 }
1479 def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI(16|32)m")>;
1480
1481 def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1482   let Latency = 22;
1483   let NumMicroOps = 7;
1484   let ResourceCycles = [1,3,2,1];
1485 }
1486 def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
1487
1488 def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1489   let Latency = 23;
1490   let NumMicroOps = 9;
1491   let ResourceCycles = [1,3,4,1];
1492 }
1493 def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
1494
1495 def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1496   let Latency = 24;
1497   let NumMicroOps = 9;
1498   let ResourceCycles = [1,5,2,1];
1499 }
1500 def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
1501
1502 def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1503   let Latency = 25;
1504   let NumMicroOps = 7;
1505   let ResourceCycles = [1,3,2,1];
1506 }
1507 def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
1508                                             VGATHERDPSrm)>;
1509
1510 def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1511   let Latency = 26;
1512   let NumMicroOps = 9;
1513   let ResourceCycles = [1,5,2,1];
1514 }
1515 def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
1516
1517 def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1518   let Latency = 26;
1519   let NumMicroOps = 14;
1520   let ResourceCycles = [1,4,8,1];
1521 }
1522 def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
1523
1524 def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
1525   let Latency = 27;
1526   let NumMicroOps = 9;
1527   let ResourceCycles = [1,5,2,1];
1528 }
1529 def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
1530
1531 def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1532   let Latency = 29;
1533   let NumMicroOps = 27;
1534   let ResourceCycles = [1,5,1,1,19];
1535 }
1536 def: InstRW<[BWWriteResGroup185], (instrs XSAVE64)>;
1537
1538 def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1539   let Latency = 30;
1540   let NumMicroOps = 28;
1541   let ResourceCycles = [1,6,1,1,19];
1542 }
1543 def: InstRW<[BWWriteResGroup186], (instrs XSAVE)>;
1544 def: InstRW<[BWWriteResGroup186], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>;
1545
1546 def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
1547   let Latency = 34;
1548   let NumMicroOps = 23;
1549   let ResourceCycles = [1,5,3,4,10];
1550 }
1551 def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
1552                                              "IN(8|16|32)rr")>;
1553
1554 def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
1555   let Latency = 35;
1556   let NumMicroOps = 23;
1557   let ResourceCycles = [1,5,2,1,4,10];
1558 }
1559 def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
1560                                              "OUT(8|16|32)rr")>;
1561
1562 def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
1563   let Latency = 42;
1564   let NumMicroOps = 22;
1565   let ResourceCycles = [2,20];
1566 }
1567 def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
1568
1569 def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
1570   let Latency = 60;
1571   let NumMicroOps = 64;
1572   let ResourceCycles = [2,2,8,1,10,2,39];
1573 }
1574 def: InstRW<[BWWriteResGroup197], (instrs FLDENVm)>;
1575
1576 def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1577   let Latency = 63;
1578   let NumMicroOps = 88;
1579   let ResourceCycles = [4,4,31,1,2,1,45];
1580 }
1581 def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
1582
1583 def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
1584   let Latency = 63;
1585   let NumMicroOps = 90;
1586   let ResourceCycles = [4,2,33,1,2,1,47];
1587 }
1588 def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
1589
1590 def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
1591   let Latency = 75;
1592   let NumMicroOps = 15;
1593   let ResourceCycles = [6,3,6];
1594 }
1595 def: InstRW<[BWWriteResGroup200], (instrs FNINIT)>;
1596
1597 def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
1598   let Latency = 115;
1599   let NumMicroOps = 100;
1600   let ResourceCycles = [9,9,11,8,1,11,21,30];
1601 }
1602 def: InstRW<[BWWriteResGroup202], (instrs FSTENVm)>;
1603
1604 def: InstRW<[WriteZero], (instrs CLC)>;
1605
1606
1607 // Intruction variants handled by the renamer. These might not need execution
1608 // ports in certain conditions.
1609 // See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1610 // section "Haswell and Broadwell Pipeline" > "Register allocation and
1611 // renaming".
1612 // These can be investigated with llvm-exegesis, e.g.
1613 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1614 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1615
1616 def BWWriteZeroLatency : SchedWriteRes<[]> {
1617   let Latency = 0;
1618 }
1619
1620 def BWWriteZeroIdiom : SchedWriteVariant<[
1621     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1622     SchedVar<NoSchedPred,                          [WriteALU]>
1623 ]>;
1624 def : InstRW<[BWWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1625                                          XOR32rr, XOR64rr)>;
1626
1627 def BWWriteFZeroIdiom : SchedWriteVariant<[
1628     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1629     SchedVar<NoSchedPred,                          [WriteFLogic]>
1630 ]>;
1631 def : InstRW<[BWWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1632                                           VXORPDrr)>;
1633
1634 def BWWriteFZeroIdiomY : SchedWriteVariant<[
1635     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1636     SchedVar<NoSchedPred,                          [WriteFLogicY]>
1637 ]>;
1638 def : InstRW<[BWWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1639
1640 def BWWriteVZeroIdiomLogicX : SchedWriteVariant<[
1641     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1642     SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1643 ]>;
1644 def : InstRW<[BWWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1645
1646 def BWWriteVZeroIdiomLogicY : SchedWriteVariant<[
1647     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1648     SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1649 ]>;
1650 def : InstRW<[BWWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1651
1652 def BWWriteVZeroIdiomALUX : SchedWriteVariant<[
1653     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1654     SchedVar<NoSchedPred,                          [WriteVecALUX]>
1655 ]>;
1656 def : InstRW<[BWWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1657                                               PSUBDrr, VPSUBDrr,
1658                                               PSUBQrr, VPSUBQrr,
1659                                               PSUBWrr, VPSUBWrr,
1660                                               PCMPGTBrr, VPCMPGTBrr,
1661                                               PCMPGTDrr, VPCMPGTDrr,
1662                                               PCMPGTWrr, VPCMPGTWrr)>;
1663
1664 def BWWriteVZeroIdiomALUY : SchedWriteVariant<[
1665     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1666     SchedVar<NoSchedPred,                          [WriteVecALUY]>
1667 ]>;
1668 def : InstRW<[BWWriteVZeroIdiomALUY], (instrs VPSUBBYrr,
1669                                               VPSUBDYrr,
1670                                               VPSUBQYrr,
1671                                               VPSUBWYrr,
1672                                               VPCMPGTBYrr,
1673                                               VPCMPGTDYrr,
1674                                               VPCMPGTWYrr)>;
1675
1676 def BWWritePCMPGTQ : SchedWriteRes<[BWPort0]> {
1677   let Latency = 5;
1678   let NumMicroOps = 1;
1679   let ResourceCycles = [1];
1680 }
1681
1682 def BWWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1683     SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [BWWriteZeroLatency]>,
1684     SchedVar<NoSchedPred,                          [BWWritePCMPGTQ]>
1685 ]>;
1686 def : InstRW<[BWWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1687                                                  VPCMPGTQYrr)>;
1688
1689
1690 // CMOVs that use both Z and C flag require an extra uop.
1691 def BWWriteCMOVA_CMOVBErr : SchedWriteRes<[BWPort06,BWPort0156]> {
1692   let Latency = 2;
1693   let ResourceCycles = [1,1];
1694   let NumMicroOps = 2;
1695 }
1696
1697 def BWWriteCMOVA_CMOVBErm : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1698   let Latency = 7;
1699   let ResourceCycles = [1,1,1];
1700   let NumMicroOps = 3;
1701 }
1702
1703 def BWCMOVA_CMOVBErr :  SchedWriteVariant<[
1704   SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [BWWriteCMOVA_CMOVBErr]>,
1705   SchedVar<NoSchedPred,                             [WriteCMOV]>
1706 ]>;
1707
1708 def BWCMOVA_CMOVBErm :  SchedWriteVariant<[
1709   SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [BWWriteCMOVA_CMOVBErm]>,
1710   SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1711 ]>;
1712
1713 def : InstRW<[BWCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1714 def : InstRW<[BWCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1715
1716 // SETCCs that use both Z and C flag require an extra uop.
1717 def BWWriteSETA_SETBEr : SchedWriteRes<[BWPort06,BWPort0156]> {
1718   let Latency = 2;
1719   let ResourceCycles = [1,1];
1720   let NumMicroOps = 2;
1721 }
1722
1723 def BWWriteSETA_SETBEm : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1724   let Latency = 3;
1725   let ResourceCycles = [1,1,1,1];
1726   let NumMicroOps = 4;
1727 }
1728
1729 def BWSETA_SETBErr :  SchedWriteVariant<[
1730   SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [BWWriteSETA_SETBEr]>,
1731   SchedVar<NoSchedPred,                         [WriteSETCC]>
1732 ]>;
1733
1734 def BWSETA_SETBErm :  SchedWriteVariant<[
1735   SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [BWWriteSETA_SETBEm]>,
1736   SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1737 ]>;
1738
1739 def : InstRW<[BWSETA_SETBErr], (instrs SETCCr)>;
1740 def : InstRW<[BWSETA_SETBErm], (instrs SETCCm)>;
1741
1742 } // SchedModel