[Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignment
[llvm-core.git] / lib / Target / XCore / XCoreRegisterInfo.h
blob35a42e1a1457782ffe065d41670bb54ea0db5a4d
1 //===-- XCoreRegisterInfo.h - XCore Register Information Impl ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains the XCore implementation of the MRegisterInfo class.
11 //===----------------------------------------------------------------------===//
13 #ifndef LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H
14 #define LLVM_LIB_TARGET_XCORE_XCOREREGISTERINFO_H
16 #include "llvm/CodeGen/TargetRegisterInfo.h"
18 #define GET_REGINFO_HEADER
19 #include "XCoreGenRegisterInfo.inc"
21 namespace llvm {
23 class TargetInstrInfo;
25 struct XCoreRegisterInfo : public XCoreGenRegisterInfo {
26 public:
27 XCoreRegisterInfo();
29 /// Code Generation virtual methods...
31 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
33 BitVector getReservedRegs(const MachineFunction &MF) const override;
35 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
37 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
39 bool useFPForScavengingIndex(const MachineFunction &MF) const override;
41 void eliminateFrameIndex(MachineBasicBlock::iterator II,
42 int SPAdj, unsigned FIOperandNum,
43 RegScavenger *RS = nullptr) const override;
45 // Debug information queries.
46 Register getFrameRegister(const MachineFunction &MF) const override;
48 //! Return whether to emit frame moves
49 static bool needsFrameMoves(const MachineFunction &MF);
52 } // end namespace llvm
54 #endif