| blob | 0ae2c9e3ccfe933f4ded11593b3c7dc4c8254805 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+sse2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,SSE,X86-SSE
3 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX1,X86-AVX1
4 ; RUN: llc < %s -disable-peephole -mtriple=i386-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X86,AVX,X86-AVX,AVX512,X86-AVX512
5 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+sse2 -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,SSE,X64-SSE
6 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX1,X64-AVX1
7 ; RUN: llc < %s -disable-peephole -mtriple=x86_64-apple-darwin -mattr=+avx512f,+avx512bw,+avx512dq,+avx512vl -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,X64,AVX,X64-AVX,AVX512,X64-AVX512
9 define <2 x double> @test_x86_sse2_cmp_pd(<2 x double> %a0, <2 x double> %a1) {
10 ; SSE-LABEL: test_x86_sse2_cmp_pd:
11 ; SSE: ## %bb.0:
12 ; SSE-NEXT: cmpordpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xc2,0xc1,0x07]
13 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
14 ;
15 ; AVX-LABEL: test_x86_sse2_cmp_pd:
16 ; AVX: ## %bb.0:
17 ; AVX-NEXT: vcmpordpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xc2,0xc1,0x07]
18 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
19 %res = call <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
20 ret <2 x double> %res
21 }
22 declare <2 x double> @llvm.x86.sse2.cmp.pd(<2 x double>, <2 x double>, i8) nounwind readnone
25 define <2 x double> @test_x86_sse2_cmp_sd(<2 x double> %a0, <2 x double> %a1) {
26 ; SSE-LABEL: test_x86_sse2_cmp_sd:
27 ; SSE: ## %bb.0:
28 ; SSE-NEXT: cmpordsd %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0xc2,0xc1,0x07]
29 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
30 ;
31 ; AVX-LABEL: test_x86_sse2_cmp_sd:
32 ; AVX: ## %bb.0:
33 ; AVX-NEXT: vcmpordsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xc2,0xc1,0x07]
34 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
35 %res = call <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double> %a0, <2 x double> %a1, i8 7) ; <<2 x double>> [#uses=1]
36 ret <2 x double> %res
37 }
38 declare <2 x double> @llvm.x86.sse2.cmp.sd(<2 x double>, <2 x double>, i8) nounwind readnone
41 define i32 @test_x86_sse2_comieq_sd(<2 x double> %a0, <2 x double> %a1) {
42 ; SSE-LABEL: test_x86_sse2_comieq_sd:
43 ; SSE: ## %bb.0:
44 ; SSE-NEXT: comisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2f,0xc1]
45 ; SSE-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
46 ; SSE-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
47 ; SSE-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
48 ; SSE-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
49 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
50 ;
51 ; AVX1-LABEL: test_x86_sse2_comieq_sd:
52 ; AVX1: ## %bb.0:
53 ; AVX1-NEXT: vcomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2f,0xc1]
54 ; AVX1-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
55 ; AVX1-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
56 ; AVX1-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
57 ; AVX1-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
58 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
59 ;
60 ; AVX512-LABEL: test_x86_sse2_comieq_sd:
61 ; AVX512: ## %bb.0:
62 ; AVX512-NEXT: vcomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc1]
63 ; AVX512-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
64 ; AVX512-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
65 ; AVX512-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
66 ; AVX512-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
67 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
68 %res = call i32 @llvm.x86.sse2.comieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
69 ret i32 %res
70 }
71 declare i32 @llvm.x86.sse2.comieq.sd(<2 x double>, <2 x double>) nounwind readnone
74 define i32 @test_x86_sse2_comige_sd(<2 x double> %a0, <2 x double> %a1) {
75 ; SSE-LABEL: test_x86_sse2_comige_sd:
76 ; SSE: ## %bb.0:
77 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
78 ; SSE-NEXT: comisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2f,0xc1]
79 ; SSE-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
80 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
81 ;
82 ; AVX1-LABEL: test_x86_sse2_comige_sd:
83 ; AVX1: ## %bb.0:
84 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
85 ; AVX1-NEXT: vcomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2f,0xc1]
86 ; AVX1-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
87 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
88 ;
89 ; AVX512-LABEL: test_x86_sse2_comige_sd:
90 ; AVX512: ## %bb.0:
91 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
92 ; AVX512-NEXT: vcomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc1]
93 ; AVX512-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
94 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
95 %res = call i32 @llvm.x86.sse2.comige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
96 ret i32 %res
97 }
98 declare i32 @llvm.x86.sse2.comige.sd(<2 x double>, <2 x double>) nounwind readnone
101 define i32 @test_x86_sse2_comigt_sd(<2 x double> %a0, <2 x double> %a1) {
102 ; SSE-LABEL: test_x86_sse2_comigt_sd:
103 ; SSE: ## %bb.0:
104 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
105 ; SSE-NEXT: comisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2f,0xc1]
106 ; SSE-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
107 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
108 ;
109 ; AVX1-LABEL: test_x86_sse2_comigt_sd:
110 ; AVX1: ## %bb.0:
111 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
112 ; AVX1-NEXT: vcomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2f,0xc1]
113 ; AVX1-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
114 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
115 ;
116 ; AVX512-LABEL: test_x86_sse2_comigt_sd:
117 ; AVX512: ## %bb.0:
118 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
119 ; AVX512-NEXT: vcomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc1]
120 ; AVX512-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
121 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
122 %res = call i32 @llvm.x86.sse2.comigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
123 ret i32 %res
124 }
125 declare i32 @llvm.x86.sse2.comigt.sd(<2 x double>, <2 x double>) nounwind readnone
128 define i32 @test_x86_sse2_comile_sd(<2 x double> %a0, <2 x double> %a1) {
129 ; SSE-LABEL: test_x86_sse2_comile_sd:
130 ; SSE: ## %bb.0:
131 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
132 ; SSE-NEXT: comisd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x2f,0xc8]
133 ; SSE-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
134 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
135 ;
136 ; AVX1-LABEL: test_x86_sse2_comile_sd:
137 ; AVX1: ## %bb.0:
138 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
139 ; AVX1-NEXT: vcomisd %xmm0, %xmm1 ## encoding: [0xc5,0xf9,0x2f,0xc8]
140 ; AVX1-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
141 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
142 ;
143 ; AVX512-LABEL: test_x86_sse2_comile_sd:
144 ; AVX512: ## %bb.0:
145 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
146 ; AVX512-NEXT: vcomisd %xmm0, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc8]
147 ; AVX512-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
148 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
149 %res = call i32 @llvm.x86.sse2.comile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
150 ret i32 %res
151 }
152 declare i32 @llvm.x86.sse2.comile.sd(<2 x double>, <2 x double>) nounwind readnone
155 define i32 @test_x86_sse2_comilt_sd(<2 x double> %a0, <2 x double> %a1) {
156 ; SSE-LABEL: test_x86_sse2_comilt_sd:
157 ; SSE: ## %bb.0:
158 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
159 ; SSE-NEXT: comisd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x2f,0xc8]
160 ; SSE-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
161 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
162 ;
163 ; AVX1-LABEL: test_x86_sse2_comilt_sd:
164 ; AVX1: ## %bb.0:
165 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
166 ; AVX1-NEXT: vcomisd %xmm0, %xmm1 ## encoding: [0xc5,0xf9,0x2f,0xc8]
167 ; AVX1-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
168 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
169 ;
170 ; AVX512-LABEL: test_x86_sse2_comilt_sd:
171 ; AVX512: ## %bb.0:
172 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
173 ; AVX512-NEXT: vcomisd %xmm0, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc8]
174 ; AVX512-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
175 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
176 %res = call i32 @llvm.x86.sse2.comilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
177 ret i32 %res
178 }
179 declare i32 @llvm.x86.sse2.comilt.sd(<2 x double>, <2 x double>) nounwind readnone
182 define i32 @test_x86_sse2_comineq_sd(<2 x double> %a0, <2 x double> %a1) {
183 ; SSE-LABEL: test_x86_sse2_comineq_sd:
184 ; SSE: ## %bb.0:
185 ; SSE-NEXT: comisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2f,0xc1]
186 ; SSE-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
187 ; SSE-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
188 ; SSE-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
189 ; SSE-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
190 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
191 ;
192 ; AVX1-LABEL: test_x86_sse2_comineq_sd:
193 ; AVX1: ## %bb.0:
194 ; AVX1-NEXT: vcomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2f,0xc1]
195 ; AVX1-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
196 ; AVX1-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
197 ; AVX1-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
198 ; AVX1-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
199 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
200 ;
201 ; AVX512-LABEL: test_x86_sse2_comineq_sd:
202 ; AVX512: ## %bb.0:
203 ; AVX512-NEXT: vcomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2f,0xc1]
204 ; AVX512-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
205 ; AVX512-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
206 ; AVX512-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
207 ; AVX512-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
208 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
209 %res = call i32 @llvm.x86.sse2.comineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
210 ret i32 %res
211 }
212 declare i32 @llvm.x86.sse2.comineq.sd(<2 x double>, <2 x double>) nounwind readnone
215 define <4 x i32> @test_x86_sse2_cvtpd2dq(<2 x double> %a0) {
216 ; SSE-LABEL: test_x86_sse2_cvtpd2dq:
217 ; SSE: ## %bb.0:
218 ; SSE-NEXT: cvtpd2dq %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0xe6,0xc0]
219 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
220 ;
221 ; AVX1-LABEL: test_x86_sse2_cvtpd2dq:
222 ; AVX1: ## %bb.0:
223 ; AVX1-NEXT: vcvtpd2dq %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xe6,0xc0]
224 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
225 ;
226 ; AVX512-LABEL: test_x86_sse2_cvtpd2dq:
227 ; AVX512: ## %bb.0:
228 ; AVX512-NEXT: vcvtpd2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0xe6,0xc0]
229 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
230 %res = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
231 ret <4 x i32> %res
232 }
233 declare <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double>) nounwind readnone
236 define <2 x i64> @test_mm_cvtpd_epi32_zext(<2 x double> %a0) nounwind {
237 ; SSE-LABEL: test_mm_cvtpd_epi32_zext:
238 ; SSE: ## %bb.0:
239 ; SSE-NEXT: cvtpd2dq %xmm0, %xmm0 ## encoding: [0xf2,0x0f,0xe6,0xc0]
240 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
241 ;
242 ; AVX1-LABEL: test_mm_cvtpd_epi32_zext:
243 ; AVX1: ## %bb.0:
244 ; AVX1-NEXT: vcvtpd2dq %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0xe6,0xc0]
245 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
246 ;
247 ; AVX512-LABEL: test_mm_cvtpd_epi32_zext:
248 ; AVX512: ## %bb.0:
249 ; AVX512-NEXT: vcvtpd2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0xe6,0xc0]
250 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
251 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
252 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
253 %bc = bitcast <4 x i32> %res to <2 x i64>
254 ret <2 x i64> %bc
255 }
258 define <2 x i64> @test_mm_cvtpd_epi32_zext_load(<2 x double>* %p0) nounwind {
259 ; X86-SSE-LABEL: test_mm_cvtpd_epi32_zext_load:
260 ; X86-SSE: ## %bb.0:
261 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
262 ; X86-SSE-NEXT: cvtpd2dq (%eax), %xmm0 ## encoding: [0xf2,0x0f,0xe6,0x00]
263 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
264 ;
265 ; X86-AVX1-LABEL: test_mm_cvtpd_epi32_zext_load:
266 ; X86-AVX1: ## %bb.0:
267 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
268 ; X86-AVX1-NEXT: vcvtpd2dqx (%eax), %xmm0 ## encoding: [0xc5,0xfb,0xe6,0x00]
269 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
270 ;
271 ; X86-AVX512-LABEL: test_mm_cvtpd_epi32_zext_load:
272 ; X86-AVX512: ## %bb.0:
273 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
274 ; X86-AVX512-NEXT: vcvtpd2dqx (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0xe6,0x00]
275 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
276 ;
277 ; X64-SSE-LABEL: test_mm_cvtpd_epi32_zext_load:
278 ; X64-SSE: ## %bb.0:
279 ; X64-SSE-NEXT: cvtpd2dq (%rdi), %xmm0 ## encoding: [0xf2,0x0f,0xe6,0x07]
280 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
281 ;
282 ; X64-AVX1-LABEL: test_mm_cvtpd_epi32_zext_load:
283 ; X64-AVX1: ## %bb.0:
284 ; X64-AVX1-NEXT: vcvtpd2dqx (%rdi), %xmm0 ## encoding: [0xc5,0xfb,0xe6,0x07]
285 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
286 ;
287 ; X64-AVX512-LABEL: test_mm_cvtpd_epi32_zext_load:
288 ; X64-AVX512: ## %bb.0:
289 ; X64-AVX512-NEXT: vcvtpd2dqx (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0xe6,0x07]
290 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
291 %a0 = load <2 x double>, <2 x double>* %p0
292 %cvt = call <4 x i32> @llvm.x86.sse2.cvtpd2dq(<2 x double> %a0)
293 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
294 %bc = bitcast <4 x i32> %res to <2 x i64>
295 ret <2 x i64> %bc
296 }
299 define <4 x float> @test_x86_sse2_cvtpd2ps(<2 x double> %a0) {
300 ; SSE-LABEL: test_x86_sse2_cvtpd2ps:
301 ; SSE: ## %bb.0:
302 ; SSE-NEXT: cvtpd2ps %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x5a,0xc0]
303 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
304 ;
305 ; AVX1-LABEL: test_x86_sse2_cvtpd2ps:
306 ; AVX1: ## %bb.0:
307 ; AVX1-NEXT: vcvtpd2ps %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x5a,0xc0]
308 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
309 ;
310 ; AVX512-LABEL: test_x86_sse2_cvtpd2ps:
311 ; AVX512: ## %bb.0:
312 ; AVX512-NEXT: vcvtpd2ps %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5a,0xc0]
313 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
314 %res = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0) ; <<4 x float>> [#uses=1]
315 ret <4 x float> %res
316 }
317 declare <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double>) nounwind readnone
319 define <4 x float> @test_x86_sse2_cvtpd2ps_zext(<2 x double> %a0) nounwind {
320 ; SSE-LABEL: test_x86_sse2_cvtpd2ps_zext:
321 ; SSE: ## %bb.0:
322 ; SSE-NEXT: cvtpd2ps %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x5a,0xc0]
323 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
324 ;
325 ; AVX1-LABEL: test_x86_sse2_cvtpd2ps_zext:
326 ; AVX1: ## %bb.0:
327 ; AVX1-NEXT: vcvtpd2ps %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x5a,0xc0]
328 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
329 ;
330 ; AVX512-LABEL: test_x86_sse2_cvtpd2ps_zext:
331 ; AVX512: ## %bb.0:
332 ; AVX512-NEXT: vcvtpd2ps %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5a,0xc0]
333 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
334 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)
335 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
336 ret <4 x float> %res
337 }
339 define <4 x float> @test_x86_sse2_cvtpd2ps_zext_load(<2 x double>* %p0) nounwind {
340 ; X86-SSE-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
341 ; X86-SSE: ## %bb.0:
342 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
343 ; X86-SSE-NEXT: cvtpd2ps (%eax), %xmm0 ## encoding: [0x66,0x0f,0x5a,0x00]
344 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
345 ;
346 ; X86-AVX1-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
347 ; X86-AVX1: ## %bb.0:
348 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
349 ; X86-AVX1-NEXT: vcvtpd2psx (%eax), %xmm0 ## encoding: [0xc5,0xf9,0x5a,0x00]
350 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
351 ;
352 ; X86-AVX512-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
353 ; X86-AVX512: ## %bb.0:
354 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
355 ; X86-AVX512-NEXT: vcvtpd2psx (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5a,0x00]
356 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
357 ;
358 ; X64-SSE-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
359 ; X64-SSE: ## %bb.0:
360 ; X64-SSE-NEXT: cvtpd2ps (%rdi), %xmm0 ## encoding: [0x66,0x0f,0x5a,0x07]
361 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
362 ;
363 ; X64-AVX1-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
364 ; X64-AVX1: ## %bb.0:
365 ; X64-AVX1-NEXT: vcvtpd2psx (%rdi), %xmm0 ## encoding: [0xc5,0xf9,0x5a,0x07]
366 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
367 ;
368 ; X64-AVX512-LABEL: test_x86_sse2_cvtpd2ps_zext_load:
369 ; X64-AVX512: ## %bb.0:
370 ; X64-AVX512-NEXT: vcvtpd2psx (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5a,0x07]
371 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
372 %a0 = load <2 x double>, <2 x double>* %p0
373 %cvt = call <4 x float> @llvm.x86.sse2.cvtpd2ps(<2 x double> %a0)
374 %res = shufflevector <4 x float> %cvt, <4 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
375 ret <4 x float> %res
376 }
378 define <4 x i32> @test_x86_sse2_cvtps2dq(<4 x float> %a0) {
379 ; SSE-LABEL: test_x86_sse2_cvtps2dq:
380 ; SSE: ## %bb.0:
381 ; SSE-NEXT: cvtps2dq %xmm0, %xmm0 ## encoding: [0x66,0x0f,0x5b,0xc0]
382 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
383 ;
384 ; AVX1-LABEL: test_x86_sse2_cvtps2dq:
385 ; AVX1: ## %bb.0:
386 ; AVX1-NEXT: vcvtps2dq %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x5b,0xc0]
387 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
388 ;
389 ; AVX512-LABEL: test_x86_sse2_cvtps2dq:
390 ; AVX512: ## %bb.0:
391 ; AVX512-NEXT: vcvtps2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5b,0xc0]
392 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
393 %res = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
394 ret <4 x i32> %res
395 }
396 declare <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float>) nounwind readnone
399 define i32 @test_x86_sse2_cvtsd2si(<2 x double> %a0) {
400 ; SSE-LABEL: test_x86_sse2_cvtsd2si:
401 ; SSE: ## %bb.0:
402 ; SSE-NEXT: cvtsd2si %xmm0, %eax ## encoding: [0xf2,0x0f,0x2d,0xc0]
403 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
404 ;
405 ; AVX1-LABEL: test_x86_sse2_cvtsd2si:
406 ; AVX1: ## %bb.0:
407 ; AVX1-NEXT: vcvtsd2si %xmm0, %eax ## encoding: [0xc5,0xfb,0x2d,0xc0]
408 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
409 ;
410 ; AVX512-LABEL: test_x86_sse2_cvtsd2si:
411 ; AVX512: ## %bb.0:
412 ; AVX512-NEXT: vcvtsd2si %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x2d,0xc0]
413 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
414 %res = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %a0) ; <i32> [#uses=1]
415 ret i32 %res
416 }
417 declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone
420 define <4 x float> @test_x86_sse2_cvtsd2ss(<4 x float> %a0, <2 x double> %a1) {
421 ; SSE-LABEL: test_x86_sse2_cvtsd2ss:
422 ; SSE: ## %bb.0:
423 ; SSE-NEXT: cvtsd2ss %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x5a,0xc1]
424 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
425 ;
426 ; AVX1-LABEL: test_x86_sse2_cvtsd2ss:
427 ; AVX1: ## %bb.0:
428 ; AVX1-NEXT: vcvtsd2ss %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5a,0xc1]
429 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
430 ;
431 ; AVX512-LABEL: test_x86_sse2_cvtsd2ss:
432 ; AVX512: ## %bb.0:
433 ; AVX512-NEXT: vcvtsd2ss %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5a,0xc1]
434 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
435 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
436 ret <4 x float> %res
437 }
438 declare <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float>, <2 x double>) nounwind readnone
441 define <4 x float> @test_x86_sse2_cvtsd2ss_load(<4 x float> %a0, <2 x double>* %p1) {
442 ; X86-SSE-LABEL: test_x86_sse2_cvtsd2ss_load:
443 ; X86-SSE: ## %bb.0:
444 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
445 ; X86-SSE-NEXT: cvtsd2ss (%eax), %xmm0 ## encoding: [0xf2,0x0f,0x5a,0x00]
446 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
447 ;
448 ; X86-AVX1-LABEL: test_x86_sse2_cvtsd2ss_load:
449 ; X86-AVX1: ## %bb.0:
450 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
451 ; X86-AVX1-NEXT: vcvtsd2ss (%eax), %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5a,0x00]
452 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
453 ;
454 ; X86-AVX512-LABEL: test_x86_sse2_cvtsd2ss_load:
455 ; X86-AVX512: ## %bb.0:
456 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
457 ; X86-AVX512-NEXT: vcvtsd2ss (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5a,0x00]
458 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
459 ;
460 ; X64-SSE-LABEL: test_x86_sse2_cvtsd2ss_load:
461 ; X64-SSE: ## %bb.0:
462 ; X64-SSE-NEXT: cvtsd2ss (%rdi), %xmm0 ## encoding: [0xf2,0x0f,0x5a,0x07]
463 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
464 ;
465 ; X64-AVX1-LABEL: test_x86_sse2_cvtsd2ss_load:
466 ; X64-AVX1: ## %bb.0:
467 ; X64-AVX1-NEXT: vcvtsd2ss (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5a,0x07]
468 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
469 ;
470 ; X64-AVX512-LABEL: test_x86_sse2_cvtsd2ss_load:
471 ; X64-AVX512: ## %bb.0:
472 ; X64-AVX512-NEXT: vcvtsd2ss (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5a,0x07]
473 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
474 %a1 = load <2 x double>, <2 x double>* %p1
475 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
476 ret <4 x float> %res
477 }
480 define <4 x float> @test_x86_sse2_cvtsd2ss_load_optsize(<4 x float> %a0, <2 x double>* %p1) optsize {
481 ; X86-SSE-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
482 ; X86-SSE: ## %bb.0:
483 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
484 ; X86-SSE-NEXT: cvtsd2ss (%eax), %xmm0 ## encoding: [0xf2,0x0f,0x5a,0x00]
485 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
486 ;
487 ; X86-AVX1-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
488 ; X86-AVX1: ## %bb.0:
489 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
490 ; X86-AVX1-NEXT: vcvtsd2ss (%eax), %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5a,0x00]
491 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
492 ;
493 ; X86-AVX512-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
494 ; X86-AVX512: ## %bb.0:
495 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
496 ; X86-AVX512-NEXT: vcvtsd2ss (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5a,0x00]
497 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
498 ;
499 ; X64-SSE-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
500 ; X64-SSE: ## %bb.0:
501 ; X64-SSE-NEXT: cvtsd2ss (%rdi), %xmm0 ## encoding: [0xf2,0x0f,0x5a,0x07]
502 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
503 ;
504 ; X64-AVX1-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
505 ; X64-AVX1: ## %bb.0:
506 ; X64-AVX1-NEXT: vcvtsd2ss (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5a,0x07]
507 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
508 ;
509 ; X64-AVX512-LABEL: test_x86_sse2_cvtsd2ss_load_optsize:
510 ; X64-AVX512: ## %bb.0:
511 ; X64-AVX512-NEXT: vcvtsd2ss (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5a,0x07]
512 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
513 %a1 = load <2 x double>, <2 x double>* %p1
514 %res = call <4 x float> @llvm.x86.sse2.cvtsd2ss(<4 x float> %a0, <2 x double> %a1) ; <<4 x float>> [#uses=1]
515 ret <4 x float> %res
516 }
519 define <4 x i32> @test_x86_sse2_cvttpd2dq(<2 x double> %a0) {
520 ; SSE-LABEL: test_x86_sse2_cvttpd2dq:
521 ; SSE: ## %bb.0:
522 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0 ## encoding: [0x66,0x0f,0xe6,0xc0]
523 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
524 ;
525 ; AVX1-LABEL: test_x86_sse2_cvttpd2dq:
526 ; AVX1: ## %bb.0:
527 ; AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe6,0xc0]
528 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
529 ;
530 ; AVX512-LABEL: test_x86_sse2_cvttpd2dq:
531 ; AVX512: ## %bb.0:
532 ; AVX512-NEXT: vcvttpd2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe6,0xc0]
533 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
534 %res = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0) ; <<4 x i32>> [#uses=1]
535 ret <4 x i32> %res
536 }
537 declare <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double>) nounwind readnone
540 define <2 x i64> @test_mm_cvttpd_epi32_zext(<2 x double> %a0) nounwind {
541 ; SSE-LABEL: test_mm_cvttpd_epi32_zext:
542 ; SSE: ## %bb.0:
543 ; SSE-NEXT: cvttpd2dq %xmm0, %xmm0 ## encoding: [0x66,0x0f,0xe6,0xc0]
544 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
545 ;
546 ; AVX1-LABEL: test_mm_cvttpd_epi32_zext:
547 ; AVX1: ## %bb.0:
548 ; AVX1-NEXT: vcvttpd2dq %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe6,0xc0]
549 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
550 ;
551 ; AVX512-LABEL: test_mm_cvttpd_epi32_zext:
552 ; AVX512: ## %bb.0:
553 ; AVX512-NEXT: vcvttpd2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe6,0xc0]
554 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
555 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)
556 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
557 %bc = bitcast <4 x i32> %res to <2 x i64>
558 ret <2 x i64> %bc
559 }
562 define <2 x i64> @test_mm_cvttpd_epi32_zext_load(<2 x double>* %p0) nounwind {
563 ; X86-SSE-LABEL: test_mm_cvttpd_epi32_zext_load:
564 ; X86-SSE: ## %bb.0:
565 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
566 ; X86-SSE-NEXT: cvttpd2dq (%eax), %xmm0 ## encoding: [0x66,0x0f,0xe6,0x00]
567 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
568 ;
569 ; X86-AVX1-LABEL: test_mm_cvttpd_epi32_zext_load:
570 ; X86-AVX1: ## %bb.0:
571 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
572 ; X86-AVX1-NEXT: vcvttpd2dqx (%eax), %xmm0 ## encoding: [0xc5,0xf9,0xe6,0x00]
573 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
574 ;
575 ; X86-AVX512-LABEL: test_mm_cvttpd_epi32_zext_load:
576 ; X86-AVX512: ## %bb.0:
577 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
578 ; X86-AVX512-NEXT: vcvttpd2dqx (%eax), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe6,0x00]
579 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
580 ;
581 ; X64-SSE-LABEL: test_mm_cvttpd_epi32_zext_load:
582 ; X64-SSE: ## %bb.0:
583 ; X64-SSE-NEXT: cvttpd2dq (%rdi), %xmm0 ## encoding: [0x66,0x0f,0xe6,0x07]
584 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
585 ;
586 ; X64-AVX1-LABEL: test_mm_cvttpd_epi32_zext_load:
587 ; X64-AVX1: ## %bb.0:
588 ; X64-AVX1-NEXT: vcvttpd2dqx (%rdi), %xmm0 ## encoding: [0xc5,0xf9,0xe6,0x07]
589 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
590 ;
591 ; X64-AVX512-LABEL: test_mm_cvttpd_epi32_zext_load:
592 ; X64-AVX512: ## %bb.0:
593 ; X64-AVX512-NEXT: vcvttpd2dqx (%rdi), %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe6,0x07]
594 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
595 %a0 = load <2 x double>, <2 x double>* %p0
596 %cvt = call <4 x i32> @llvm.x86.sse2.cvttpd2dq(<2 x double> %a0)
597 %res = shufflevector <4 x i32> %cvt, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
598 %bc = bitcast <4 x i32> %res to <2 x i64>
599 ret <2 x i64> %bc
600 }
603 define <4 x i32> @test_x86_sse2_cvttps2dq(<4 x float> %a0) {
604 ; SSE-LABEL: test_x86_sse2_cvttps2dq:
605 ; SSE: ## %bb.0:
606 ; SSE-NEXT: cvttps2dq %xmm0, %xmm0 ## encoding: [0xf3,0x0f,0x5b,0xc0]
607 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
608 ;
609 ; AVX1-LABEL: test_x86_sse2_cvttps2dq:
610 ; AVX1: ## %bb.0:
611 ; AVX1-NEXT: vcvttps2dq %xmm0, %xmm0 ## encoding: [0xc5,0xfa,0x5b,0xc0]
612 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
613 ;
614 ; AVX512-LABEL: test_x86_sse2_cvttps2dq:
615 ; AVX512: ## %bb.0:
616 ; AVX512-NEXT: vcvttps2dq %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfa,0x5b,0xc0]
617 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
618 %res = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0) ; <<4 x i32>> [#uses=1]
619 ret <4 x i32> %res
620 }
621 declare <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float>) nounwind readnone
624 define i32 @test_x86_sse2_cvttsd2si(<2 x double> %a0) {
625 ; SSE-LABEL: test_x86_sse2_cvttsd2si:
626 ; SSE: ## %bb.0:
627 ; SSE-NEXT: cvttsd2si %xmm0, %eax ## encoding: [0xf2,0x0f,0x2c,0xc0]
628 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
629 ;
630 ; AVX1-LABEL: test_x86_sse2_cvttsd2si:
631 ; AVX1: ## %bb.0:
632 ; AVX1-NEXT: vcvttsd2si %xmm0, %eax ## encoding: [0xc5,0xfb,0x2c,0xc0]
633 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
634 ;
635 ; AVX512-LABEL: test_x86_sse2_cvttsd2si:
636 ; AVX512: ## %bb.0:
637 ; AVX512-NEXT: vcvttsd2si %xmm0, %eax ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x2c,0xc0]
638 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
639 %res = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %a0) ; <i32> [#uses=1]
640 ret i32 %res
641 }
642 declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone
645 define <2 x double> @test_x86_sse2_max_pd(<2 x double> %a0, <2 x double> %a1) {
646 ; SSE-LABEL: test_x86_sse2_max_pd:
647 ; SSE: ## %bb.0:
648 ; SSE-NEXT: maxpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x5f,0xc1]
649 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
650 ;
651 ; AVX1-LABEL: test_x86_sse2_max_pd:
652 ; AVX1: ## %bb.0:
653 ; AVX1-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x5f,0xc1]
654 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
655 ;
656 ; AVX512-LABEL: test_x86_sse2_max_pd:
657 ; AVX512: ## %bb.0:
658 ; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5f,0xc1]
659 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
660 %res = call <2 x double> @llvm.x86.sse2.max.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
661 ret <2 x double> %res
662 }
663 declare <2 x double> @llvm.x86.sse2.max.pd(<2 x double>, <2 x double>) nounwind readnone
666 define <2 x double> @test_x86_sse2_max_sd(<2 x double> %a0, <2 x double> %a1) {
667 ; SSE-LABEL: test_x86_sse2_max_sd:
668 ; SSE: ## %bb.0:
669 ; SSE-NEXT: maxsd %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x5f,0xc1]
670 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
671 ;
672 ; AVX1-LABEL: test_x86_sse2_max_sd:
673 ; AVX1: ## %bb.0:
674 ; AVX1-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5f,0xc1]
675 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
676 ;
677 ; AVX512-LABEL: test_x86_sse2_max_sd:
678 ; AVX512: ## %bb.0:
679 ; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5f,0xc1]
680 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
681 %res = call <2 x double> @llvm.x86.sse2.max.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
682 ret <2 x double> %res
683 }
684 declare <2 x double> @llvm.x86.sse2.max.sd(<2 x double>, <2 x double>) nounwind readnone
687 define <2 x double> @test_x86_sse2_min_pd(<2 x double> %a0, <2 x double> %a1) {
688 ; SSE-LABEL: test_x86_sse2_min_pd:
689 ; SSE: ## %bb.0:
690 ; SSE-NEXT: minpd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x5d,0xc1]
691 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
692 ;
693 ; AVX1-LABEL: test_x86_sse2_min_pd:
694 ; AVX1: ## %bb.0:
695 ; AVX1-NEXT: vminpd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x5d,0xc1]
696 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
697 ;
698 ; AVX512-LABEL: test_x86_sse2_min_pd:
699 ; AVX512: ## %bb.0:
700 ; AVX512-NEXT: vminpd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x5d,0xc1]
701 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
702 %res = call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
703 ret <2 x double> %res
704 }
705 declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone
708 define <2 x double> @test_x86_sse2_min_sd(<2 x double> %a0, <2 x double> %a1) {
709 ; SSE-LABEL: test_x86_sse2_min_sd:
710 ; SSE: ## %bb.0:
711 ; SSE-NEXT: minsd %xmm1, %xmm0 ## encoding: [0xf2,0x0f,0x5d,0xc1]
712 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
713 ;
714 ; AVX1-LABEL: test_x86_sse2_min_sd:
715 ; AVX1: ## %bb.0:
716 ; AVX1-NEXT: vminsd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xfb,0x5d,0xc1]
717 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
718 ;
719 ; AVX512-LABEL: test_x86_sse2_min_sd:
720 ; AVX512: ## %bb.0:
721 ; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xfb,0x5d,0xc1]
722 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
723 %res = call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %a0, <2 x double> %a1) ; <<2 x double>> [#uses=1]
724 ret <2 x double> %res
725 }
726 declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone
729 define i32 @test_x86_sse2_movmsk_pd(<2 x double> %a0) {
730 ; SSE-LABEL: test_x86_sse2_movmsk_pd:
731 ; SSE: ## %bb.0:
732 ; SSE-NEXT: movmskpd %xmm0, %eax ## encoding: [0x66,0x0f,0x50,0xc0]
733 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
734 ;
735 ; AVX-LABEL: test_x86_sse2_movmsk_pd:
736 ; AVX: ## %bb.0:
737 ; AVX-NEXT: vmovmskpd %xmm0, %eax ## encoding: [0xc5,0xf9,0x50,0xc0]
738 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
739 %res = call i32 @llvm.x86.sse2.movmsk.pd(<2 x double> %a0) ; <i32> [#uses=1]
740 ret i32 %res
741 }
742 declare i32 @llvm.x86.sse2.movmsk.pd(<2 x double>) nounwind readnone
745 define <8 x i16> @test_x86_sse2_packssdw_128(<4 x i32> %a0, <4 x i32> %a1) {
746 ; SSE-LABEL: test_x86_sse2_packssdw_128:
747 ; SSE: ## %bb.0:
748 ; SSE-NEXT: packssdw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x6b,0xc1]
749 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
750 ;
751 ; AVX1-LABEL: test_x86_sse2_packssdw_128:
752 ; AVX1: ## %bb.0:
753 ; AVX1-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x6b,0xc1]
754 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
755 ;
756 ; AVX512-LABEL: test_x86_sse2_packssdw_128:
757 ; AVX512: ## %bb.0:
758 ; AVX512-NEXT: vpackssdw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x6b,0xc1]
759 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
760 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> %a0, <4 x i32> %a1) ; <<8 x i16>> [#uses=1]
761 ret <8 x i16> %res
762 }
763 declare <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32>, <4 x i32>) nounwind readnone
766 define <8 x i16> @test_x86_sse2_packssdw_128_fold() {
767 ; X86-SSE-LABEL: test_x86_sse2_packssdw_128_fold:
768 ; X86-SSE: ## %bb.0:
769 ; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
770 ; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
771 ; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI30_0, kind: FK_Data_4
772 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
773 ;
774 ; X86-AVX1-LABEL: test_x86_sse2_packssdw_128_fold:
775 ; X86-AVX1: ## %bb.0:
776 ; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
777 ; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
778 ; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI30_0, kind: FK_Data_4
779 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
780 ;
781 ; X86-AVX512-LABEL: test_x86_sse2_packssdw_128_fold:
782 ; X86-AVX512: ## %bb.0:
783 ; X86-AVX512-NEXT: vmovaps LCPI30_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
784 ; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
785 ; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI30_0, kind: FK_Data_4
786 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
787 ;
788 ; X64-SSE-LABEL: test_x86_sse2_packssdw_128_fold:
789 ; X64-SSE: ## %bb.0:
790 ; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
791 ; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
792 ; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI30_0-4, kind: reloc_riprel_4byte
793 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
794 ;
795 ; X64-AVX1-LABEL: test_x86_sse2_packssdw_128_fold:
796 ; X64-AVX1: ## %bb.0:
797 ; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,0,0,0,32767,32767,65535,32768]
798 ; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
799 ; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI30_0-4, kind: reloc_riprel_4byte
800 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
801 ;
802 ; X64-AVX512-LABEL: test_x86_sse2_packssdw_128_fold:
803 ; X64-AVX512: ## %bb.0:
804 ; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,0,0,0,32767,32767,65535,32768]
805 ; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
806 ; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI30_0-4, kind: reloc_riprel_4byte
807 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
808 %res = call <8 x i16> @llvm.x86.sse2.packssdw.128(<4 x i32> zeroinitializer, <4 x i32> <i32 65535, i32 65536, i32 -1, i32 -131072>)
809 ret <8 x i16> %res
810 }
813 define <16 x i8> @test_x86_sse2_packsswb_128(<8 x i16> %a0, <8 x i16> %a1) {
814 ; SSE-LABEL: test_x86_sse2_packsswb_128:
815 ; SSE: ## %bb.0:
816 ; SSE-NEXT: packsswb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x63,0xc1]
817 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
818 ;
819 ; AVX1-LABEL: test_x86_sse2_packsswb_128:
820 ; AVX1: ## %bb.0:
821 ; AVX1-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x63,0xc1]
822 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
823 ;
824 ; AVX512-LABEL: test_x86_sse2_packsswb_128:
825 ; AVX512: ## %bb.0:
826 ; AVX512-NEXT: vpacksswb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x63,0xc1]
827 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
828 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
829 ret <16 x i8> %res
830 }
831 declare <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16>, <8 x i16>) nounwind readnone
834 define <16 x i8> @test_x86_sse2_packsswb_128_fold() {
835 ; X86-SSE-LABEL: test_x86_sse2_packsswb_128_fold:
836 ; X86-SSE: ## %bb.0:
837 ; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
838 ; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
839 ; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI32_0, kind: FK_Data_4
840 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
841 ;
842 ; X86-AVX1-LABEL: test_x86_sse2_packsswb_128_fold:
843 ; X86-AVX1: ## %bb.0:
844 ; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
845 ; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
846 ; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4
847 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
848 ;
849 ; X86-AVX512-LABEL: test_x86_sse2_packsswb_128_fold:
850 ; X86-AVX512: ## %bb.0:
851 ; X86-AVX512-NEXT: vmovaps LCPI32_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
852 ; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
853 ; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI32_0, kind: FK_Data_4
854 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
855 ;
856 ; X64-SSE-LABEL: test_x86_sse2_packsswb_128_fold:
857 ; X64-SSE: ## %bb.0:
858 ; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
859 ; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
860 ; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI32_0-4, kind: reloc_riprel_4byte
861 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
862 ;
863 ; X64-AVX1-LABEL: test_x86_sse2_packsswb_128_fold:
864 ; X64-AVX1: ## %bb.0:
865 ; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
866 ; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
867 ; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI32_0-4, kind: reloc_riprel_4byte
868 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
869 ;
870 ; X64-AVX512-LABEL: test_x86_sse2_packsswb_128_fold:
871 ; X64-AVX512: ## %bb.0:
872 ; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,127,127,255,255,128,128,128,0,0,0,0,0,0,0,0]
873 ; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
874 ; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI32_0-4, kind: reloc_riprel_4byte
875 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
876 %res = call <16 x i8> @llvm.x86.sse2.packsswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)
877 ret <16 x i8> %res
878 }
881 define <16 x i8> @test_x86_sse2_packuswb_128(<8 x i16> %a0, <8 x i16> %a1) {
882 ; SSE-LABEL: test_x86_sse2_packuswb_128:
883 ; SSE: ## %bb.0:
884 ; SSE-NEXT: packuswb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x67,0xc1]
885 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
886 ;
887 ; AVX1-LABEL: test_x86_sse2_packuswb_128:
888 ; AVX1: ## %bb.0:
889 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x67,0xc1]
890 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
891 ;
892 ; AVX512-LABEL: test_x86_sse2_packuswb_128:
893 ; AVX512: ## %bb.0:
894 ; AVX512-NEXT: vpackuswb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x67,0xc1]
895 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
896 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> %a0, <8 x i16> %a1) ; <<16 x i8>> [#uses=1]
897 ret <16 x i8> %res
898 }
899 declare <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16>, <8 x i16>) nounwind readnone
902 define <16 x i8> @test_x86_sse2_packuswb_128_fold() {
903 ; X86-SSE-LABEL: test_x86_sse2_packuswb_128_fold:
904 ; X86-SSE: ## %bb.0:
905 ; X86-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
906 ; X86-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
907 ; X86-SSE-NEXT: ## fixup A - offset: 3, value: LCPI34_0, kind: FK_Data_4
908 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
909 ;
910 ; X86-AVX1-LABEL: test_x86_sse2_packuswb_128_fold:
911 ; X86-AVX1: ## %bb.0:
912 ; X86-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
913 ; X86-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
914 ; X86-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4
915 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
916 ;
917 ; X86-AVX512-LABEL: test_x86_sse2_packuswb_128_fold:
918 ; X86-AVX512: ## %bb.0:
919 ; X86-AVX512-NEXT: vmovaps LCPI34_0, %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
920 ; X86-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
921 ; X86-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI34_0, kind: FK_Data_4
922 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
923 ;
924 ; X64-SSE-LABEL: test_x86_sse2_packuswb_128_fold:
925 ; X64-SSE: ## %bb.0:
926 ; X64-SSE-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
927 ; X64-SSE-NEXT: ## encoding: [0x0f,0x28,0x05,A,A,A,A]
928 ; X64-SSE-NEXT: ## fixup A - offset: 3, value: LCPI34_0-4, kind: reloc_riprel_4byte
929 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
930 ;
931 ; X64-AVX1-LABEL: test_x86_sse2_packuswb_128_fold:
932 ; X64-AVX1: ## %bb.0:
933 ; X64-AVX1-NEXT: vmovaps {{.*#+}} xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
934 ; X64-AVX1-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
935 ; X64-AVX1-NEXT: ## fixup A - offset: 4, value: LCPI34_0-4, kind: reloc_riprel_4byte
936 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
937 ;
938 ; X64-AVX512-LABEL: test_x86_sse2_packuswb_128_fold:
939 ; X64-AVX512: ## %bb.0:
940 ; X64-AVX512-NEXT: vmovaps {{.*}}(%rip), %xmm0 ## EVEX TO VEX Compression xmm0 = [0,255,255,0,0,0,0,0,0,0,0,0,0,0,0,0]
941 ; X64-AVX512-NEXT: ## encoding: [0xc5,0xf8,0x28,0x05,A,A,A,A]
942 ; X64-AVX512-NEXT: ## fixup A - offset: 4, value: LCPI34_0-4, kind: reloc_riprel_4byte
943 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
944 %res = call <16 x i8> @llvm.x86.sse2.packuswb.128(<8 x i16> <i16 0, i16 255, i16 256, i16 65535, i16 -1, i16 -255, i16 -256, i16 -32678>, <8 x i16> zeroinitializer)
945 ret <16 x i8> %res
946 }
949 define <16 x i8> @test_x86_sse2_pavg_b(<16 x i8> %a0, <16 x i8> %a1) {
950 ; SSE-LABEL: test_x86_sse2_pavg_b:
951 ; SSE: ## %bb.0:
952 ; SSE-NEXT: pavgb %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe0,0xc1]
953 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
954 ;
955 ; AVX1-LABEL: test_x86_sse2_pavg_b:
956 ; AVX1: ## %bb.0:
957 ; AVX1-NEXT: vpavgb %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe0,0xc1]
958 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
959 ;
960 ; AVX512-LABEL: test_x86_sse2_pavg_b:
961 ; AVX512: ## %bb.0:
962 ; AVX512-NEXT: vpavgb %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe0,0xc1]
963 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
964 %res = call <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
965 ret <16 x i8> %res
966 }
967 declare <16 x i8> @llvm.x86.sse2.pavg.b(<16 x i8>, <16 x i8>) nounwind readnone
970 define <8 x i16> @test_x86_sse2_pavg_w(<8 x i16> %a0, <8 x i16> %a1) {
971 ; SSE-LABEL: test_x86_sse2_pavg_w:
972 ; SSE: ## %bb.0:
973 ; SSE-NEXT: pavgw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe3,0xc1]
974 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
975 ;
976 ; AVX1-LABEL: test_x86_sse2_pavg_w:
977 ; AVX1: ## %bb.0:
978 ; AVX1-NEXT: vpavgw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe3,0xc1]
979 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
980 ;
981 ; AVX512-LABEL: test_x86_sse2_pavg_w:
982 ; AVX512: ## %bb.0:
983 ; AVX512-NEXT: vpavgw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe3,0xc1]
984 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
985 %res = call <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
986 ret <8 x i16> %res
987 }
988 declare <8 x i16> @llvm.x86.sse2.pavg.w(<8 x i16>, <8 x i16>) nounwind readnone
991 define <4 x i32> @test_x86_sse2_pmadd_wd(<8 x i16> %a0, <8 x i16> %a1) {
992 ; SSE-LABEL: test_x86_sse2_pmadd_wd:
993 ; SSE: ## %bb.0:
994 ; SSE-NEXT: pmaddwd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf5,0xc1]
995 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
996 ;
997 ; AVX1-LABEL: test_x86_sse2_pmadd_wd:
998 ; AVX1: ## %bb.0:
999 ; AVX1-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf5,0xc1]
1000 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1001 ;
1002 ; AVX512-LABEL: test_x86_sse2_pmadd_wd:
1003 ; AVX512: ## %bb.0:
1004 ; AVX512-NEXT: vpmaddwd %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf5,0xc1]
1005 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1006 %res = call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a0, <8 x i16> %a1) ; <<4 x i32>> [#uses=1]
1007 ret <4 x i32> %res
1008 }
1009 declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
1012 define <8 x i16> @test_x86_sse2_pmaxs_w(<8 x i16> %a0, <8 x i16> %a1) {
1013 ; SSE-LABEL: test_x86_sse2_pmaxs_w:
1014 ; SSE: ## %bb.0:
1015 ; SSE-NEXT: pmaxsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xee,0xc1]
1016 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1017 ;
1018 ; AVX1-LABEL: test_x86_sse2_pmaxs_w:
1019 ; AVX1: ## %bb.0:
1020 ; AVX1-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xee,0xc1]
1021 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1022 ;
1023 ; AVX512-LABEL: test_x86_sse2_pmaxs_w:
1024 ; AVX512: ## %bb.0:
1025 ; AVX512-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xee,0xc1]
1026 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1027 %res = call <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1028 ret <8 x i16> %res
1029 }
1030 declare <8 x i16> @llvm.x86.sse2.pmaxs.w(<8 x i16>, <8 x i16>) nounwind readnone
1033 define <16 x i8> @test_x86_sse2_pmaxu_b(<16 x i8> %a0, <16 x i8> %a1) {
1034 ; SSE-LABEL: test_x86_sse2_pmaxu_b:
1035 ; SSE: ## %bb.0:
1036 ; SSE-NEXT: pmaxub %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xde,0xc1]
1037 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1038 ;
1039 ; AVX1-LABEL: test_x86_sse2_pmaxu_b:
1040 ; AVX1: ## %bb.0:
1041 ; AVX1-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xde,0xc1]
1042 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1043 ;
1044 ; AVX512-LABEL: test_x86_sse2_pmaxu_b:
1045 ; AVX512: ## %bb.0:
1046 ; AVX512-NEXT: vpmaxub %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xde,0xc1]
1047 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1048 %res = call <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
1049 ret <16 x i8> %res
1050 }
1051 declare <16 x i8> @llvm.x86.sse2.pmaxu.b(<16 x i8>, <16 x i8>) nounwind readnone
1054 define <8 x i16> @test_x86_sse2_pmins_w(<8 x i16> %a0, <8 x i16> %a1) {
1055 ; SSE-LABEL: test_x86_sse2_pmins_w:
1056 ; SSE: ## %bb.0:
1057 ; SSE-NEXT: pminsw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xea,0xc1]
1058 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1059 ;
1060 ; AVX1-LABEL: test_x86_sse2_pmins_w:
1061 ; AVX1: ## %bb.0:
1062 ; AVX1-NEXT: vpminsw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xea,0xc1]
1063 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1064 ;
1065 ; AVX512-LABEL: test_x86_sse2_pmins_w:
1066 ; AVX512: ## %bb.0:
1067 ; AVX512-NEXT: vpminsw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xea,0xc1]
1068 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1069 %res = call <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1070 ret <8 x i16> %res
1071 }
1072 declare <8 x i16> @llvm.x86.sse2.pmins.w(<8 x i16>, <8 x i16>) nounwind readnone
1075 define <16 x i8> @test_x86_sse2_pminu_b(<16 x i8> %a0, <16 x i8> %a1) {
1076 ; SSE-LABEL: test_x86_sse2_pminu_b:
1077 ; SSE: ## %bb.0:
1078 ; SSE-NEXT: pminub %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xda,0xc1]
1079 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1080 ;
1081 ; AVX1-LABEL: test_x86_sse2_pminu_b:
1082 ; AVX1: ## %bb.0:
1083 ; AVX1-NEXT: vpminub %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xda,0xc1]
1084 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1085 ;
1086 ; AVX512-LABEL: test_x86_sse2_pminu_b:
1087 ; AVX512: ## %bb.0:
1088 ; AVX512-NEXT: vpminub %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xda,0xc1]
1089 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1090 %res = call <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8> %a0, <16 x i8> %a1) ; <<16 x i8>> [#uses=1]
1091 ret <16 x i8> %res
1092 }
1093 declare <16 x i8> @llvm.x86.sse2.pminu.b(<16 x i8>, <16 x i8>) nounwind readnone
1096 define i32 @test_x86_sse2_pmovmskb_128(<16 x i8> %a0) {
1097 ; SSE-LABEL: test_x86_sse2_pmovmskb_128:
1098 ; SSE: ## %bb.0:
1099 ; SSE-NEXT: pmovmskb %xmm0, %eax ## encoding: [0x66,0x0f,0xd7,0xc0]
1100 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1101 ;
1102 ; AVX-LABEL: test_x86_sse2_pmovmskb_128:
1103 ; AVX: ## %bb.0:
1104 ; AVX-NEXT: vpmovmskb %xmm0, %eax ## encoding: [0xc5,0xf9,0xd7,0xc0]
1105 ; AVX-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1106 %res = call i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8> %a0) ; <i32> [#uses=1]
1107 ret i32 %res
1108 }
1109 declare i32 @llvm.x86.sse2.pmovmskb.128(<16 x i8>) nounwind readnone
1112 define <8 x i16> @test_x86_sse2_pmulh_w(<8 x i16> %a0, <8 x i16> %a1) {
1113 ; SSE-LABEL: test_x86_sse2_pmulh_w:
1114 ; SSE: ## %bb.0:
1115 ; SSE-NEXT: pmulhw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe5,0xc1]
1116 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1117 ;
1118 ; AVX1-LABEL: test_x86_sse2_pmulh_w:
1119 ; AVX1: ## %bb.0:
1120 ; AVX1-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe5,0xc1]
1121 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1122 ;
1123 ; AVX512-LABEL: test_x86_sse2_pmulh_w:
1124 ; AVX512: ## %bb.0:
1125 ; AVX512-NEXT: vpmulhw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe5,0xc1]
1126 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1127 %res = call <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1128 ret <8 x i16> %res
1129 }
1130 declare <8 x i16> @llvm.x86.sse2.pmulh.w(<8 x i16>, <8 x i16>) nounwind readnone
1133 define <8 x i16> @test_x86_sse2_pmulhu_w(<8 x i16> %a0, <8 x i16> %a1) {
1134 ; SSE-LABEL: test_x86_sse2_pmulhu_w:
1135 ; SSE: ## %bb.0:
1136 ; SSE-NEXT: pmulhuw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe4,0xc1]
1137 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1138 ;
1139 ; AVX1-LABEL: test_x86_sse2_pmulhu_w:
1140 ; AVX1: ## %bb.0:
1141 ; AVX1-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe4,0xc1]
1142 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1143 ;
1144 ; AVX512-LABEL: test_x86_sse2_pmulhu_w:
1145 ; AVX512: ## %bb.0:
1146 ; AVX512-NEXT: vpmulhuw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe4,0xc1]
1147 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1148 %res = call <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1149 ret <8 x i16> %res
1150 }
1151 declare <8 x i16> @llvm.x86.sse2.pmulhu.w(<8 x i16>, <8 x i16>) nounwind readnone
1154 define <2 x i64> @test_x86_sse2_psad_bw(<16 x i8> %a0, <16 x i8> %a1) {
1155 ; SSE-LABEL: test_x86_sse2_psad_bw:
1156 ; SSE: ## %bb.0:
1157 ; SSE-NEXT: psadbw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf6,0xc1]
1158 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1159 ;
1160 ; AVX1-LABEL: test_x86_sse2_psad_bw:
1161 ; AVX1: ## %bb.0:
1162 ; AVX1-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf6,0xc1]
1163 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1164 ;
1165 ; AVX512-LABEL: test_x86_sse2_psad_bw:
1166 ; AVX512: ## %bb.0:
1167 ; AVX512-NEXT: vpsadbw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf6,0xc1]
1168 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1169 %res = call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a0, <16 x i8> %a1) ; <<2 x i64>> [#uses=1]
1170 ret <2 x i64> %res
1171 }
1172 declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
1175 define <4 x i32> @test_x86_sse2_psll_d(<4 x i32> %a0, <4 x i32> %a1) {
1176 ; SSE-LABEL: test_x86_sse2_psll_d:
1177 ; SSE: ## %bb.0:
1178 ; SSE-NEXT: pslld %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf2,0xc1]
1179 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1180 ;
1181 ; AVX1-LABEL: test_x86_sse2_psll_d:
1182 ; AVX1: ## %bb.0:
1183 ; AVX1-NEXT: vpslld %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf2,0xc1]
1184 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1185 ;
1186 ; AVX512-LABEL: test_x86_sse2_psll_d:
1187 ; AVX512: ## %bb.0:
1188 ; AVX512-NEXT: vpslld %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf2,0xc1]
1189 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1190 %res = call <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1191 ret <4 x i32> %res
1192 }
1193 declare <4 x i32> @llvm.x86.sse2.psll.d(<4 x i32>, <4 x i32>) nounwind readnone
1196 define <2 x i64> @test_x86_sse2_psll_q(<2 x i64> %a0, <2 x i64> %a1) {
1197 ; SSE-LABEL: test_x86_sse2_psll_q:
1198 ; SSE: ## %bb.0:
1199 ; SSE-NEXT: psllq %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf3,0xc1]
1200 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1201 ;
1202 ; AVX1-LABEL: test_x86_sse2_psll_q:
1203 ; AVX1: ## %bb.0:
1204 ; AVX1-NEXT: vpsllq %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf3,0xc1]
1205 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1206 ;
1207 ; AVX512-LABEL: test_x86_sse2_psll_q:
1208 ; AVX512: ## %bb.0:
1209 ; AVX512-NEXT: vpsllq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf3,0xc1]
1210 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1211 %res = call <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
1212 ret <2 x i64> %res
1213 }
1214 declare <2 x i64> @llvm.x86.sse2.psll.q(<2 x i64>, <2 x i64>) nounwind readnone
1217 define <8 x i16> @test_x86_sse2_psll_w(<8 x i16> %a0, <8 x i16> %a1) {
1218 ; SSE-LABEL: test_x86_sse2_psll_w:
1219 ; SSE: ## %bb.0:
1220 ; SSE-NEXT: psllw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xf1,0xc1]
1221 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1222 ;
1223 ; AVX1-LABEL: test_x86_sse2_psll_w:
1224 ; AVX1: ## %bb.0:
1225 ; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xf1,0xc1]
1226 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1227 ;
1228 ; AVX512-LABEL: test_x86_sse2_psll_w:
1229 ; AVX512: ## %bb.0:
1230 ; AVX512-NEXT: vpsllw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xf1,0xc1]
1231 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1232 %res = call <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1233 ret <8 x i16> %res
1234 }
1235 declare <8 x i16> @llvm.x86.sse2.psll.w(<8 x i16>, <8 x i16>) nounwind readnone
1238 define <4 x i32> @test_x86_sse2_pslli_d(<4 x i32> %a0) {
1239 ; SSE-LABEL: test_x86_sse2_pslli_d:
1240 ; SSE: ## %bb.0:
1241 ; SSE-NEXT: pslld $7, %xmm0 ## encoding: [0x66,0x0f,0x72,0xf0,0x07]
1242 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1243 ;
1244 ; AVX1-LABEL: test_x86_sse2_pslli_d:
1245 ; AVX1: ## %bb.0:
1246 ; AVX1-NEXT: vpslld $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x72,0xf0,0x07]
1247 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1248 ;
1249 ; AVX512-LABEL: test_x86_sse2_pslli_d:
1250 ; AVX512: ## %bb.0:
1251 ; AVX512-NEXT: vpslld $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x72,0xf0,0x07]
1252 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1253 %res = call <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
1254 ret <4 x i32> %res
1255 }
1256 declare <4 x i32> @llvm.x86.sse2.pslli.d(<4 x i32>, i32) nounwind readnone
1259 define <2 x i64> @test_x86_sse2_pslli_q(<2 x i64> %a0) {
1260 ; SSE-LABEL: test_x86_sse2_pslli_q:
1261 ; SSE: ## %bb.0:
1262 ; SSE-NEXT: psllq $7, %xmm0 ## encoding: [0x66,0x0f,0x73,0xf0,0x07]
1263 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1264 ;
1265 ; AVX1-LABEL: test_x86_sse2_pslli_q:
1266 ; AVX1: ## %bb.0:
1267 ; AVX1-NEXT: vpsllq $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x73,0xf0,0x07]
1268 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1269 ;
1270 ; AVX512-LABEL: test_x86_sse2_pslli_q:
1271 ; AVX512: ## %bb.0:
1272 ; AVX512-NEXT: vpsllq $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x73,0xf0,0x07]
1273 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1274 %res = call <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
1275 ret <2 x i64> %res
1276 }
1277 declare <2 x i64> @llvm.x86.sse2.pslli.q(<2 x i64>, i32) nounwind readnone
1280 define <8 x i16> @test_x86_sse2_pslli_w(<8 x i16> %a0) {
1281 ; SSE-LABEL: test_x86_sse2_pslli_w:
1282 ; SSE: ## %bb.0:
1283 ; SSE-NEXT: psllw $7, %xmm0 ## encoding: [0x66,0x0f,0x71,0xf0,0x07]
1284 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1285 ;
1286 ; AVX1-LABEL: test_x86_sse2_pslli_w:
1287 ; AVX1: ## %bb.0:
1288 ; AVX1-NEXT: vpsllw $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x71,0xf0,0x07]
1289 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1290 ;
1291 ; AVX512-LABEL: test_x86_sse2_pslli_w:
1292 ; AVX512: ## %bb.0:
1293 ; AVX512-NEXT: vpsllw $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x71,0xf0,0x07]
1294 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1295 %res = call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
1296 ret <8 x i16> %res
1297 }
1298 declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) nounwind readnone
1301 define <4 x i32> @test_x86_sse2_psra_d(<4 x i32> %a0, <4 x i32> %a1) {
1302 ; SSE-LABEL: test_x86_sse2_psra_d:
1303 ; SSE: ## %bb.0:
1304 ; SSE-NEXT: psrad %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe2,0xc1]
1305 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1306 ;
1307 ; AVX1-LABEL: test_x86_sse2_psra_d:
1308 ; AVX1: ## %bb.0:
1309 ; AVX1-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe2,0xc1]
1310 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1311 ;
1312 ; AVX512-LABEL: test_x86_sse2_psra_d:
1313 ; AVX512: ## %bb.0:
1314 ; AVX512-NEXT: vpsrad %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe2,0xc1]
1315 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1316 %res = call <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1317 ret <4 x i32> %res
1318 }
1319 declare <4 x i32> @llvm.x86.sse2.psra.d(<4 x i32>, <4 x i32>) nounwind readnone
1322 define <8 x i16> @test_x86_sse2_psra_w(<8 x i16> %a0, <8 x i16> %a1) {
1323 ; SSE-LABEL: test_x86_sse2_psra_w:
1324 ; SSE: ## %bb.0:
1325 ; SSE-NEXT: psraw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xe1,0xc1]
1326 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1327 ;
1328 ; AVX1-LABEL: test_x86_sse2_psra_w:
1329 ; AVX1: ## %bb.0:
1330 ; AVX1-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xe1,0xc1]
1331 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1332 ;
1333 ; AVX512-LABEL: test_x86_sse2_psra_w:
1334 ; AVX512: ## %bb.0:
1335 ; AVX512-NEXT: vpsraw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xe1,0xc1]
1336 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1337 %res = call <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1338 ret <8 x i16> %res
1339 }
1340 declare <8 x i16> @llvm.x86.sse2.psra.w(<8 x i16>, <8 x i16>) nounwind readnone
1343 define <4 x i32> @test_x86_sse2_psrai_d(<4 x i32> %a0) {
1344 ; SSE-LABEL: test_x86_sse2_psrai_d:
1345 ; SSE: ## %bb.0:
1346 ; SSE-NEXT: psrad $7, %xmm0 ## encoding: [0x66,0x0f,0x72,0xe0,0x07]
1347 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1348 ;
1349 ; AVX1-LABEL: test_x86_sse2_psrai_d:
1350 ; AVX1: ## %bb.0:
1351 ; AVX1-NEXT: vpsrad $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x72,0xe0,0x07]
1352 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1353 ;
1354 ; AVX512-LABEL: test_x86_sse2_psrai_d:
1355 ; AVX512: ## %bb.0:
1356 ; AVX512-NEXT: vpsrad $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x72,0xe0,0x07]
1357 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1358 %res = call <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
1359 ret <4 x i32> %res
1360 }
1361 declare <4 x i32> @llvm.x86.sse2.psrai.d(<4 x i32>, i32) nounwind readnone
1364 define <8 x i16> @test_x86_sse2_psrai_w(<8 x i16> %a0) {
1365 ; SSE-LABEL: test_x86_sse2_psrai_w:
1366 ; SSE: ## %bb.0:
1367 ; SSE-NEXT: psraw $7, %xmm0 ## encoding: [0x66,0x0f,0x71,0xe0,0x07]
1368 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1369 ;
1370 ; AVX1-LABEL: test_x86_sse2_psrai_w:
1371 ; AVX1: ## %bb.0:
1372 ; AVX1-NEXT: vpsraw $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x71,0xe0,0x07]
1373 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1374 ;
1375 ; AVX512-LABEL: test_x86_sse2_psrai_w:
1376 ; AVX512: ## %bb.0:
1377 ; AVX512-NEXT: vpsraw $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x71,0xe0,0x07]
1378 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1379 %res = call <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
1380 ret <8 x i16> %res
1381 }
1382 declare <8 x i16> @llvm.x86.sse2.psrai.w(<8 x i16>, i32) nounwind readnone
1385 define <4 x i32> @test_x86_sse2_psrl_d(<4 x i32> %a0, <4 x i32> %a1) {
1386 ; SSE-LABEL: test_x86_sse2_psrl_d:
1387 ; SSE: ## %bb.0:
1388 ; SSE-NEXT: psrld %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xd2,0xc1]
1389 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1390 ;
1391 ; AVX1-LABEL: test_x86_sse2_psrl_d:
1392 ; AVX1: ## %bb.0:
1393 ; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd2,0xc1]
1394 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1395 ;
1396 ; AVX512-LABEL: test_x86_sse2_psrl_d:
1397 ; AVX512: ## %bb.0:
1398 ; AVX512-NEXT: vpsrld %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd2,0xc1]
1399 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1400 %res = call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %a0, <4 x i32> %a1) ; <<4 x i32>> [#uses=1]
1401 ret <4 x i32> %res
1402 }
1403 declare <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32>, <4 x i32>) nounwind readnone
1406 define <2 x i64> @test_x86_sse2_psrl_q(<2 x i64> %a0, <2 x i64> %a1) {
1407 ; SSE-LABEL: test_x86_sse2_psrl_q:
1408 ; SSE: ## %bb.0:
1409 ; SSE-NEXT: psrlq %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xd3,0xc1]
1410 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1411 ;
1412 ; AVX1-LABEL: test_x86_sse2_psrl_q:
1413 ; AVX1: ## %bb.0:
1414 ; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd3,0xc1]
1415 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1416 ;
1417 ; AVX512-LABEL: test_x86_sse2_psrl_q:
1418 ; AVX512: ## %bb.0:
1419 ; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd3,0xc1]
1420 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1421 %res = call <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64> %a0, <2 x i64> %a1) ; <<2 x i64>> [#uses=1]
1422 ret <2 x i64> %res
1423 }
1424 declare <2 x i64> @llvm.x86.sse2.psrl.q(<2 x i64>, <2 x i64>) nounwind readnone
1427 define <8 x i16> @test_x86_sse2_psrl_w(<8 x i16> %a0, <8 x i16> %a1) {
1428 ; SSE-LABEL: test_x86_sse2_psrl_w:
1429 ; SSE: ## %bb.0:
1430 ; SSE-NEXT: psrlw %xmm1, %xmm0 ## encoding: [0x66,0x0f,0xd1,0xc1]
1431 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1432 ;
1433 ; AVX1-LABEL: test_x86_sse2_psrl_w:
1434 ; AVX1: ## %bb.0:
1435 ; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd1,0xc1]
1436 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1437 ;
1438 ; AVX512-LABEL: test_x86_sse2_psrl_w:
1439 ; AVX512: ## %bb.0:
1440 ; AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0xc1]
1441 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1442 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1443 ret <8 x i16> %res
1444 }
1445 declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) nounwind readnone
1448 define <8 x i16> @test_x86_sse2_psrl_w_load(<8 x i16> %a0, <8 x i16>* %p) {
1449 ; X86-SSE-LABEL: test_x86_sse2_psrl_w_load:
1450 ; X86-SSE: ## %bb.0:
1451 ; X86-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
1452 ; X86-SSE-NEXT: psrlw (%eax), %xmm0 ## encoding: [0x66,0x0f,0xd1,0x00]
1453 ; X86-SSE-NEXT: retl ## encoding: [0xc3]
1454 ;
1455 ; X86-AVX1-LABEL: test_x86_sse2_psrl_w_load:
1456 ; X86-AVX1: ## %bb.0:
1457 ; X86-AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
1458 ; X86-AVX1-NEXT: vpsrlw (%eax), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd1,0x00]
1459 ; X86-AVX1-NEXT: retl ## encoding: [0xc3]
1460 ;
1461 ; X86-AVX512-LABEL: test_x86_sse2_psrl_w_load:
1462 ; X86-AVX512: ## %bb.0:
1463 ; X86-AVX512-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
1464 ; X86-AVX512-NEXT: vpsrlw (%eax), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0x00]
1465 ; X86-AVX512-NEXT: retl ## encoding: [0xc3]
1466 ;
1467 ; X64-SSE-LABEL: test_x86_sse2_psrl_w_load:
1468 ; X64-SSE: ## %bb.0:
1469 ; X64-SSE-NEXT: psrlw (%rdi), %xmm0 ## encoding: [0x66,0x0f,0xd1,0x07]
1470 ; X64-SSE-NEXT: retq ## encoding: [0xc3]
1471 ;
1472 ; X64-AVX1-LABEL: test_x86_sse2_psrl_w_load:
1473 ; X64-AVX1: ## %bb.0:
1474 ; X64-AVX1-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0xd1,0x07]
1475 ; X64-AVX1-NEXT: retq ## encoding: [0xc3]
1476 ;
1477 ; X64-AVX512-LABEL: test_x86_sse2_psrl_w_load:
1478 ; X64-AVX512: ## %bb.0:
1479 ; X64-AVX512-NEXT: vpsrlw (%rdi), %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0xd1,0x07]
1480 ; X64-AVX512-NEXT: retq ## encoding: [0xc3]
1481 %a1 = load <8 x i16>, <8 x i16>* %p
1482 %res = call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %a0, <8 x i16> %a1) ; <<8 x i16>> [#uses=1]
1483 ret <8 x i16> %res
1484 }
1487 define <4 x i32> @test_x86_sse2_psrli_d(<4 x i32> %a0) {
1488 ; SSE-LABEL: test_x86_sse2_psrli_d:
1489 ; SSE: ## %bb.0:
1490 ; SSE-NEXT: psrld $7, %xmm0 ## encoding: [0x66,0x0f,0x72,0xd0,0x07]
1491 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1492 ;
1493 ; AVX1-LABEL: test_x86_sse2_psrli_d:
1494 ; AVX1: ## %bb.0:
1495 ; AVX1-NEXT: vpsrld $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x72,0xd0,0x07]
1496 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1497 ;
1498 ; AVX512-LABEL: test_x86_sse2_psrli_d:
1499 ; AVX512: ## %bb.0:
1500 ; AVX512-NEXT: vpsrld $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x72,0xd0,0x07]
1501 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1502 %res = call <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32> %a0, i32 7) ; <<4 x i32>> [#uses=1]
1503 ret <4 x i32> %res
1504 }
1505 declare <4 x i32> @llvm.x86.sse2.psrli.d(<4 x i32>, i32) nounwind readnone
1508 define <2 x i64> @test_x86_sse2_psrli_q(<2 x i64> %a0) {
1509 ; SSE-LABEL: test_x86_sse2_psrli_q:
1510 ; SSE: ## %bb.0:
1511 ; SSE-NEXT: psrlq $7, %xmm0 ## encoding: [0x66,0x0f,0x73,0xd0,0x07]
1512 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1513 ;
1514 ; AVX1-LABEL: test_x86_sse2_psrli_q:
1515 ; AVX1: ## %bb.0:
1516 ; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x73,0xd0,0x07]
1517 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1518 ;
1519 ; AVX512-LABEL: test_x86_sse2_psrli_q:
1520 ; AVX512: ## %bb.0:
1521 ; AVX512-NEXT: vpsrlq $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x73,0xd0,0x07]
1522 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1523 %res = call <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64> %a0, i32 7) ; <<2 x i64>> [#uses=1]
1524 ret <2 x i64> %res
1525 }
1526 declare <2 x i64> @llvm.x86.sse2.psrli.q(<2 x i64>, i32) nounwind readnone
1529 define <8 x i16> @test_x86_sse2_psrli_w(<8 x i16> %a0) {
1530 ; SSE-LABEL: test_x86_sse2_psrli_w:
1531 ; SSE: ## %bb.0:
1532 ; SSE-NEXT: psrlw $7, %xmm0 ## encoding: [0x66,0x0f,0x71,0xd0,0x07]
1533 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1534 ;
1535 ; AVX1-LABEL: test_x86_sse2_psrli_w:
1536 ; AVX1: ## %bb.0:
1537 ; AVX1-NEXT: vpsrlw $7, %xmm0, %xmm0 ## encoding: [0xc5,0xf9,0x71,0xd0,0x07]
1538 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1539 ;
1540 ; AVX512-LABEL: test_x86_sse2_psrli_w:
1541 ; AVX512: ## %bb.0:
1542 ; AVX512-NEXT: vpsrlw $7, %xmm0, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x71,0xd0,0x07]
1543 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1544 %res = call <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16> %a0, i32 7) ; <<8 x i16>> [#uses=1]
1545 ret <8 x i16> %res
1546 }
1547 declare <8 x i16> @llvm.x86.sse2.psrli.w(<8 x i16>, i32) nounwind readnone
1550 define i32 @test_x86_sse2_ucomieq_sd(<2 x double> %a0, <2 x double> %a1) {
1551 ; SSE-LABEL: test_x86_sse2_ucomieq_sd:
1552 ; SSE: ## %bb.0:
1553 ; SSE-NEXT: ucomisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2e,0xc1]
1554 ; SSE-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
1555 ; SSE-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
1556 ; SSE-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
1557 ; SSE-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1558 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1559 ;
1560 ; AVX1-LABEL: test_x86_sse2_ucomieq_sd:
1561 ; AVX1: ## %bb.0:
1562 ; AVX1-NEXT: vucomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2e,0xc1]
1563 ; AVX1-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
1564 ; AVX1-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
1565 ; AVX1-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
1566 ; AVX1-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1567 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1568 ;
1569 ; AVX512-LABEL: test_x86_sse2_ucomieq_sd:
1570 ; AVX512: ## %bb.0:
1571 ; AVX512-NEXT: vucomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc1]
1572 ; AVX512-NEXT: setnp %al ## encoding: [0x0f,0x9b,0xc0]
1573 ; AVX512-NEXT: sete %cl ## encoding: [0x0f,0x94,0xc1]
1574 ; AVX512-NEXT: andb %al, %cl ## encoding: [0x20,0xc1]
1575 ; AVX512-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1576 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1577 %res = call i32 @llvm.x86.sse2.ucomieq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1578 ret i32 %res
1579 }
1580 declare i32 @llvm.x86.sse2.ucomieq.sd(<2 x double>, <2 x double>) nounwind readnone
1583 define i32 @test_x86_sse2_ucomige_sd(<2 x double> %a0, <2 x double> %a1) {
1584 ; SSE-LABEL: test_x86_sse2_ucomige_sd:
1585 ; SSE: ## %bb.0:
1586 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1587 ; SSE-NEXT: ucomisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2e,0xc1]
1588 ; SSE-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1589 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1590 ;
1591 ; AVX1-LABEL: test_x86_sse2_ucomige_sd:
1592 ; AVX1: ## %bb.0:
1593 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1594 ; AVX1-NEXT: vucomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2e,0xc1]
1595 ; AVX1-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1596 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1597 ;
1598 ; AVX512-LABEL: test_x86_sse2_ucomige_sd:
1599 ; AVX512: ## %bb.0:
1600 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1601 ; AVX512-NEXT: vucomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc1]
1602 ; AVX512-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1603 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1604 %res = call i32 @llvm.x86.sse2.ucomige.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1605 ret i32 %res
1606 }
1607 declare i32 @llvm.x86.sse2.ucomige.sd(<2 x double>, <2 x double>) nounwind readnone
1610 define i32 @test_x86_sse2_ucomigt_sd(<2 x double> %a0, <2 x double> %a1) {
1611 ; SSE-LABEL: test_x86_sse2_ucomigt_sd:
1612 ; SSE: ## %bb.0:
1613 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1614 ; SSE-NEXT: ucomisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2e,0xc1]
1615 ; SSE-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1616 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1617 ;
1618 ; AVX1-LABEL: test_x86_sse2_ucomigt_sd:
1619 ; AVX1: ## %bb.0:
1620 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1621 ; AVX1-NEXT: vucomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2e,0xc1]
1622 ; AVX1-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1623 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1624 ;
1625 ; AVX512-LABEL: test_x86_sse2_ucomigt_sd:
1626 ; AVX512: ## %bb.0:
1627 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1628 ; AVX512-NEXT: vucomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc1]
1629 ; AVX512-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1630 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1631 %res = call i32 @llvm.x86.sse2.ucomigt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1632 ret i32 %res
1633 }
1634 declare i32 @llvm.x86.sse2.ucomigt.sd(<2 x double>, <2 x double>) nounwind readnone
1637 define i32 @test_x86_sse2_ucomile_sd(<2 x double> %a0, <2 x double> %a1) {
1638 ; SSE-LABEL: test_x86_sse2_ucomile_sd:
1639 ; SSE: ## %bb.0:
1640 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1641 ; SSE-NEXT: ucomisd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x2e,0xc8]
1642 ; SSE-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1643 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1644 ;
1645 ; AVX1-LABEL: test_x86_sse2_ucomile_sd:
1646 ; AVX1: ## %bb.0:
1647 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1648 ; AVX1-NEXT: vucomisd %xmm0, %xmm1 ## encoding: [0xc5,0xf9,0x2e,0xc8]
1649 ; AVX1-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1650 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1651 ;
1652 ; AVX512-LABEL: test_x86_sse2_ucomile_sd:
1653 ; AVX512: ## %bb.0:
1654 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1655 ; AVX512-NEXT: vucomisd %xmm0, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc8]
1656 ; AVX512-NEXT: setae %al ## encoding: [0x0f,0x93,0xc0]
1657 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1658 %res = call i32 @llvm.x86.sse2.ucomile.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1659 ret i32 %res
1660 }
1661 declare i32 @llvm.x86.sse2.ucomile.sd(<2 x double>, <2 x double>) nounwind readnone
1664 define i32 @test_x86_sse2_ucomilt_sd(<2 x double> %a0, <2 x double> %a1) {
1665 ; SSE-LABEL: test_x86_sse2_ucomilt_sd:
1666 ; SSE: ## %bb.0:
1667 ; SSE-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1668 ; SSE-NEXT: ucomisd %xmm0, %xmm1 ## encoding: [0x66,0x0f,0x2e,0xc8]
1669 ; SSE-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1670 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1671 ;
1672 ; AVX1-LABEL: test_x86_sse2_ucomilt_sd:
1673 ; AVX1: ## %bb.0:
1674 ; AVX1-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1675 ; AVX1-NEXT: vucomisd %xmm0, %xmm1 ## encoding: [0xc5,0xf9,0x2e,0xc8]
1676 ; AVX1-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1677 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1678 ;
1679 ; AVX512-LABEL: test_x86_sse2_ucomilt_sd:
1680 ; AVX512: ## %bb.0:
1681 ; AVX512-NEXT: xorl %eax, %eax ## encoding: [0x31,0xc0]
1682 ; AVX512-NEXT: vucomisd %xmm0, %xmm1 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc8]
1683 ; AVX512-NEXT: seta %al ## encoding: [0x0f,0x97,0xc0]
1684 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1685 %res = call i32 @llvm.x86.sse2.ucomilt.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1686 ret i32 %res
1687 }
1688 declare i32 @llvm.x86.sse2.ucomilt.sd(<2 x double>, <2 x double>) nounwind readnone
1691 define i32 @test_x86_sse2_ucomineq_sd(<2 x double> %a0, <2 x double> %a1) {
1692 ; SSE-LABEL: test_x86_sse2_ucomineq_sd:
1693 ; SSE: ## %bb.0:
1694 ; SSE-NEXT: ucomisd %xmm1, %xmm0 ## encoding: [0x66,0x0f,0x2e,0xc1]
1695 ; SSE-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
1696 ; SSE-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
1697 ; SSE-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
1698 ; SSE-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1699 ; SSE-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1700 ;
1701 ; AVX1-LABEL: test_x86_sse2_ucomineq_sd:
1702 ; AVX1: ## %bb.0:
1703 ; AVX1-NEXT: vucomisd %xmm1, %xmm0 ## encoding: [0xc5,0xf9,0x2e,0xc1]
1704 ; AVX1-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
1705 ; AVX1-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
1706 ; AVX1-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
1707 ; AVX1-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1708 ; AVX1-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1709 ;
1710 ; AVX512-LABEL: test_x86_sse2_ucomineq_sd:
1711 ; AVX512: ## %bb.0:
1712 ; AVX512-NEXT: vucomisd %xmm1, %xmm0 ## EVEX TO VEX Compression encoding: [0xc5,0xf9,0x2e,0xc1]
1713 ; AVX512-NEXT: setp %al ## encoding: [0x0f,0x9a,0xc0]
1714 ; AVX512-NEXT: setne %cl ## encoding: [0x0f,0x95,0xc1]
1715 ; AVX512-NEXT: orb %al, %cl ## encoding: [0x08,0xc1]
1716 ; AVX512-NEXT: movzbl %cl, %eax ## encoding: [0x0f,0xb6,0xc1]
1717 ; AVX512-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1718 %res = call i32 @llvm.x86.sse2.ucomineq.sd(<2 x double> %a0, <2 x double> %a1) ; <i32> [#uses=1]
1719 ret i32 %res
1720 }
1721 declare i32 @llvm.x86.sse2.ucomineq.sd(<2 x double>, <2 x double>) nounwind readnone
1723 define void @test_x86_sse2_pause() {
1724 ; CHECK-LABEL: test_x86_sse2_pause:
1725 ; CHECK: ## %bb.0:
1726 ; CHECK-NEXT: pause ## encoding: [0xf3,0x90]
1727 ; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1728 tail call void @llvm.x86.sse2.pause()
1729 ret void
1730 }
1731 declare void @llvm.x86.sse2.pause() nounwind
1733 define void @lfence() nounwind {
1734 ; CHECK-LABEL: lfence:
1735 ; CHECK: ## %bb.0:
1736 ; CHECK-NEXT: lfence ## encoding: [0x0f,0xae,0xe8]
1737 ; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1738 tail call void @llvm.x86.sse2.lfence()
1739 ret void
1740 }
1741 declare void @llvm.x86.sse2.lfence() nounwind
1743 define void @mfence() nounwind {
1744 ; CHECK-LABEL: mfence:
1745 ; CHECK: ## %bb.0:
1746 ; CHECK-NEXT: mfence ## encoding: [0x0f,0xae,0xf0]
1747 ; CHECK-NEXT: ret{{[l|q]}} ## encoding: [0xc3]
1748 tail call void @llvm.x86.sse2.mfence()
1749 ret void
1750 }
1751 declare void @llvm.x86.sse2.mfence() nounwind
1753 define void @clflush(i8* %p) nounwind {
1754 ; X86-LABEL: clflush:
1755 ; X86: ## %bb.0:
1756 ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ## encoding: [0x8b,0x44,0x24,0x04]
1757 ; X86-NEXT: clflush (%eax) ## encoding: [0x0f,0xae,0x38]
1758 ; X86-NEXT: retl ## encoding: [0xc3]
1759 ;
1760 ; X64-LABEL: clflush:
1761 ; X64: ## %bb.0:
1762 ; X64-NEXT: clflush (%rdi) ## encoding: [0x0f,0xae,0x3f]
1763 ; X64-NEXT: retq ## encoding: [0xc3]
1764 tail call void @llvm.x86.sse2.clflush(i8* %p)
1765 ret void
1766 }
1767 declare void @llvm.x86.sse2.clflush(i8*) nounwind