| blob | 21a011abab0be17bf2b4f1596f51d5f16159db9a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41
4 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1
5 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2
6 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX1
7 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop,+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=XOP --check-prefix=XOPAVX2
8 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512DQ
9 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=ALL --check-prefix=AVX512 --check-prefix=AVX512BW
10 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512DQVL
11 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefix=ALL --check-prefix=AVX512VL --check-prefix=AVX512BWVL
12 ;
13 ; Just one 32-bit run to make sure we do reasonable things for i64 shifts.
14 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=ALL --check-prefix=X32-SSE --check-prefix=X32-SSE2
16 ;
17 ; Variable Shifts
18 ;
20 define <2 x i64> @var_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
21 ; SSE2-LABEL: var_shift_v2i64:
22 ; SSE2: # %bb.0:
23 ; SSE2-NEXT: movdqa %xmm0, %xmm2
24 ; SSE2-NEXT: psrlq %xmm1, %xmm2
25 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
26 ; SSE2-NEXT: psrlq %xmm1, %xmm0
27 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
28 ; SSE2-NEXT: retq
29 ;
30 ; SSE41-LABEL: var_shift_v2i64:
31 ; SSE41: # %bb.0:
32 ; SSE41-NEXT: movdqa %xmm0, %xmm2
33 ; SSE41-NEXT: psrlq %xmm1, %xmm2
34 ; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
35 ; SSE41-NEXT: psrlq %xmm1, %xmm0
36 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
37 ; SSE41-NEXT: retq
38 ;
39 ; AVX1-LABEL: var_shift_v2i64:
40 ; AVX1: # %bb.0:
41 ; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm2
42 ; AVX1-NEXT: vpshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
43 ; AVX1-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
44 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3],xmm0[4,5,6,7]
45 ; AVX1-NEXT: retq
46 ;
47 ; AVX2-LABEL: var_shift_v2i64:
48 ; AVX2: # %bb.0:
49 ; AVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
50 ; AVX2-NEXT: retq
51 ;
52 ; XOPAVX1-LABEL: var_shift_v2i64:
53 ; XOPAVX1: # %bb.0:
54 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
55 ; XOPAVX1-NEXT: vpsubq %xmm1, %xmm2, %xmm1
56 ; XOPAVX1-NEXT: vpshlq %xmm1, %xmm0, %xmm0
57 ; XOPAVX1-NEXT: retq
58 ;
59 ; XOPAVX2-LABEL: var_shift_v2i64:
60 ; XOPAVX2: # %bb.0:
61 ; XOPAVX2-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
62 ; XOPAVX2-NEXT: retq
63 ;
64 ; AVX512-LABEL: var_shift_v2i64:
65 ; AVX512: # %bb.0:
66 ; AVX512-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
67 ; AVX512-NEXT: retq
68 ;
69 ; AVX512VL-LABEL: var_shift_v2i64:
70 ; AVX512VL: # %bb.0:
71 ; AVX512VL-NEXT: vpsrlvq %xmm1, %xmm0, %xmm0
72 ; AVX512VL-NEXT: retq
73 ;
74 ; X32-SSE-LABEL: var_shift_v2i64:
75 ; X32-SSE: # %bb.0:
76 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
77 ; X32-SSE-NEXT: psrlq %xmm1, %xmm2
78 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
79 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
80 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]
81 ; X32-SSE-NEXT: retl
82 %shift = lshr <2 x i64> %a, %b
83 ret <2 x i64> %shift
84 }
86 define <4 x i32> @var_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
87 ; SSE2-LABEL: var_shift_v4i32:
88 ; SSE2: # %bb.0:
89 ; SSE2-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
90 ; SSE2-NEXT: movdqa %xmm0, %xmm3
91 ; SSE2-NEXT: psrld %xmm2, %xmm3
92 ; SSE2-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]
93 ; SSE2-NEXT: movdqa %xmm0, %xmm2
94 ; SSE2-NEXT: psrld %xmm4, %xmm2
95 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
96 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
97 ; SSE2-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
98 ; SSE2-NEXT: movdqa %xmm0, %xmm4
99 ; SSE2-NEXT: psrld %xmm3, %xmm4
100 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
101 ; SSE2-NEXT: psrld %xmm1, %xmm0
102 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
103 ; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]
104 ; SSE2-NEXT: movaps %xmm2, %xmm0
105 ; SSE2-NEXT: retq
106 ;
107 ; SSE41-LABEL: var_shift_v4i32:
108 ; SSE41: # %bb.0:
109 ; SSE41-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
110 ; SSE41-NEXT: movdqa %xmm0, %xmm3
111 ; SSE41-NEXT: psrld %xmm2, %xmm3
112 ; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
113 ; SSE41-NEXT: pshuflw {{.*#+}} xmm4 = xmm2[2,3,3,3,4,5,6,7]
114 ; SSE41-NEXT: movdqa %xmm0, %xmm5
115 ; SSE41-NEXT: psrld %xmm4, %xmm5
116 ; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm3[0,1,2,3],xmm5[4,5,6,7]
117 ; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
118 ; SSE41-NEXT: movdqa %xmm0, %xmm3
119 ; SSE41-NEXT: psrld %xmm1, %xmm3
120 ; SSE41-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,1,1,1,4,5,6,7]
121 ; SSE41-NEXT: psrld %xmm1, %xmm0
122 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7]
123 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm5[2,3],xmm0[4,5],xmm5[6,7]
124 ; SSE41-NEXT: retq
125 ;
126 ; AVX1-LABEL: var_shift_v4i32:
127 ; AVX1: # %bb.0:
128 ; AVX1-NEXT: vpsrldq {{.*#+}} xmm2 = xmm1[12,13,14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
129 ; AVX1-NEXT: vpsrld %xmm2, %xmm0, %xmm2
130 ; AVX1-NEXT: vpsrlq $32, %xmm1, %xmm3
131 ; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
132 ; AVX1-NEXT: vpblendw {{.*#+}} xmm2 = xmm3[0,1,2,3],xmm2[4,5,6,7]
133 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3
134 ; AVX1-NEXT: vpunpckhdq {{.*#+}} xmm3 = xmm1[2],xmm3[2],xmm1[3],xmm3[3]
135 ; AVX1-NEXT: vpsrld %xmm3, %xmm0, %xmm3
136 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
137 ; AVX1-NEXT: vpsrld %xmm1, %xmm0, %xmm0
138 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7]
139 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
140 ; AVX1-NEXT: retq
141 ;
142 ; AVX2-LABEL: var_shift_v4i32:
143 ; AVX2: # %bb.0:
144 ; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
145 ; AVX2-NEXT: retq
146 ;
147 ; XOPAVX1-LABEL: var_shift_v4i32:
148 ; XOPAVX1: # %bb.0:
149 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
150 ; XOPAVX1-NEXT: vpsubd %xmm1, %xmm2, %xmm1
151 ; XOPAVX1-NEXT: vpshld %xmm1, %xmm0, %xmm0
152 ; XOPAVX1-NEXT: retq
153 ;
154 ; XOPAVX2-LABEL: var_shift_v4i32:
155 ; XOPAVX2: # %bb.0:
156 ; XOPAVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
157 ; XOPAVX2-NEXT: retq
158 ;
159 ; AVX512-LABEL: var_shift_v4i32:
160 ; AVX512: # %bb.0:
161 ; AVX512-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
162 ; AVX512-NEXT: retq
163 ;
164 ; AVX512VL-LABEL: var_shift_v4i32:
165 ; AVX512VL: # %bb.0:
166 ; AVX512VL-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
167 ; AVX512VL-NEXT: retq
168 ;
169 ; X32-SSE-LABEL: var_shift_v4i32:
170 ; X32-SSE: # %bb.0:
171 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm2 = xmm1[2,3,3,3,4,5,6,7]
172 ; X32-SSE-NEXT: movdqa %xmm0, %xmm3
173 ; X32-SSE-NEXT: psrld %xmm2, %xmm3
174 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm4 = xmm1[0,1,1,1,4,5,6,7]
175 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
176 ; X32-SSE-NEXT: psrld %xmm4, %xmm2
177 ; X32-SSE-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
178 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,0,1]
179 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm3 = xmm1[2,3,3,3,4,5,6,7]
180 ; X32-SSE-NEXT: movdqa %xmm0, %xmm4
181 ; X32-SSE-NEXT: psrld %xmm3, %xmm4
182 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[0,1,1,1,4,5,6,7]
183 ; X32-SSE-NEXT: psrld %xmm1, %xmm0
184 ; X32-SSE-NEXT: punpckhqdq {{.*#+}} xmm0 = xmm0[1],xmm4[1]
185 ; X32-SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,3],xmm0[0,3]
186 ; X32-SSE-NEXT: movaps %xmm2, %xmm0
187 ; X32-SSE-NEXT: retl
188 %shift = lshr <4 x i32> %a, %b
189 ret <4 x i32> %shift
190 }
192 define <8 x i16> @var_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
193 ; SSE2-LABEL: var_shift_v8i16:
194 ; SSE2: # %bb.0:
195 ; SSE2-NEXT: psllw $12, %xmm1
196 ; SSE2-NEXT: movdqa %xmm1, %xmm2
197 ; SSE2-NEXT: psraw $15, %xmm2
198 ; SSE2-NEXT: movdqa %xmm2, %xmm3
199 ; SSE2-NEXT: pandn %xmm0, %xmm3
200 ; SSE2-NEXT: psrlw $8, %xmm0
201 ; SSE2-NEXT: pand %xmm2, %xmm0
202 ; SSE2-NEXT: por %xmm3, %xmm0
203 ; SSE2-NEXT: paddw %xmm1, %xmm1
204 ; SSE2-NEXT: movdqa %xmm1, %xmm2
205 ; SSE2-NEXT: psraw $15, %xmm2
206 ; SSE2-NEXT: movdqa %xmm2, %xmm3
207 ; SSE2-NEXT: pandn %xmm0, %xmm3
208 ; SSE2-NEXT: psrlw $4, %xmm0
209 ; SSE2-NEXT: pand %xmm2, %xmm0
210 ; SSE2-NEXT: por %xmm3, %xmm0
211 ; SSE2-NEXT: paddw %xmm1, %xmm1
212 ; SSE2-NEXT: movdqa %xmm1, %xmm2
213 ; SSE2-NEXT: psraw $15, %xmm2
214 ; SSE2-NEXT: movdqa %xmm2, %xmm3
215 ; SSE2-NEXT: pandn %xmm0, %xmm3
216 ; SSE2-NEXT: psrlw $2, %xmm0
217 ; SSE2-NEXT: pand %xmm2, %xmm0
218 ; SSE2-NEXT: por %xmm3, %xmm0
219 ; SSE2-NEXT: paddw %xmm1, %xmm1
220 ; SSE2-NEXT: psraw $15, %xmm1
221 ; SSE2-NEXT: movdqa %xmm1, %xmm2
222 ; SSE2-NEXT: pandn %xmm0, %xmm2
223 ; SSE2-NEXT: psrlw $1, %xmm0
224 ; SSE2-NEXT: pand %xmm1, %xmm0
225 ; SSE2-NEXT: por %xmm2, %xmm0
226 ; SSE2-NEXT: retq
227 ;
228 ; SSE41-LABEL: var_shift_v8i16:
229 ; SSE41: # %bb.0:
230 ; SSE41-NEXT: movdqa %xmm1, %xmm2
231 ; SSE41-NEXT: movdqa %xmm0, %xmm1
232 ; SSE41-NEXT: movdqa %xmm2, %xmm0
233 ; SSE41-NEXT: psllw $12, %xmm0
234 ; SSE41-NEXT: psllw $4, %xmm2
235 ; SSE41-NEXT: por %xmm0, %xmm2
236 ; SSE41-NEXT: movdqa %xmm2, %xmm3
237 ; SSE41-NEXT: paddw %xmm2, %xmm3
238 ; SSE41-NEXT: movdqa %xmm1, %xmm4
239 ; SSE41-NEXT: psrlw $8, %xmm4
240 ; SSE41-NEXT: movdqa %xmm2, %xmm0
241 ; SSE41-NEXT: pblendvb %xmm0, %xmm4, %xmm1
242 ; SSE41-NEXT: movdqa %xmm1, %xmm2
243 ; SSE41-NEXT: psrlw $4, %xmm2
244 ; SSE41-NEXT: movdqa %xmm3, %xmm0
245 ; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
246 ; SSE41-NEXT: movdqa %xmm1, %xmm2
247 ; SSE41-NEXT: psrlw $2, %xmm2
248 ; SSE41-NEXT: paddw %xmm3, %xmm3
249 ; SSE41-NEXT: movdqa %xmm3, %xmm0
250 ; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
251 ; SSE41-NEXT: movdqa %xmm1, %xmm2
252 ; SSE41-NEXT: psrlw $1, %xmm2
253 ; SSE41-NEXT: paddw %xmm3, %xmm3
254 ; SSE41-NEXT: movdqa %xmm3, %xmm0
255 ; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm1
256 ; SSE41-NEXT: movdqa %xmm1, %xmm0
257 ; SSE41-NEXT: retq
258 ;
259 ; AVX1-LABEL: var_shift_v8i16:
260 ; AVX1: # %bb.0:
261 ; AVX1-NEXT: vpsllw $12, %xmm1, %xmm2
262 ; AVX1-NEXT: vpsllw $4, %xmm1, %xmm1
263 ; AVX1-NEXT: vpor %xmm2, %xmm1, %xmm1
264 ; AVX1-NEXT: vpaddw %xmm1, %xmm1, %xmm2
265 ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm3
266 ; AVX1-NEXT: vpblendvb %xmm1, %xmm3, %xmm0, %xmm0
267 ; AVX1-NEXT: vpsrlw $4, %xmm0, %xmm1
268 ; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
269 ; AVX1-NEXT: vpsrlw $2, %xmm0, %xmm1
270 ; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
271 ; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
272 ; AVX1-NEXT: vpsrlw $1, %xmm0, %xmm1
273 ; AVX1-NEXT: vpaddw %xmm2, %xmm2, %xmm2
274 ; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0
275 ; AVX1-NEXT: retq
276 ;
277 ; AVX2-LABEL: var_shift_v8i16:
278 ; AVX2: # %bb.0:
279 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
280 ; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
281 ; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
282 ; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15,16,17,20,21,24,25,28,29,24,25,28,29,28,29,30,31]
283 ; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
284 ; AVX2-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
285 ; AVX2-NEXT: vzeroupper
286 ; AVX2-NEXT: retq
287 ;
288 ; XOP-LABEL: var_shift_v8i16:
289 ; XOP: # %bb.0:
290 ; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
291 ; XOP-NEXT: vpsubw %xmm1, %xmm2, %xmm1
292 ; XOP-NEXT: vpshlw %xmm1, %xmm0, %xmm0
293 ; XOP-NEXT: retq
294 ;
295 ; AVX512DQ-LABEL: var_shift_v8i16:
296 ; AVX512DQ: # %bb.0:
297 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
298 ; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
299 ; AVX512DQ-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
300 ; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0
301 ; AVX512DQ-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
302 ; AVX512DQ-NEXT: vzeroupper
303 ; AVX512DQ-NEXT: retq
304 ;
305 ; AVX512BW-LABEL: var_shift_v8i16:
306 ; AVX512BW: # %bb.0:
307 ; AVX512BW-NEXT: # kill: def $xmm1 killed $xmm1 def $zmm1
308 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
309 ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
310 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
311 ; AVX512BW-NEXT: vzeroupper
312 ; AVX512BW-NEXT: retq
313 ;
314 ; AVX512DQVL-LABEL: var_shift_v8i16:
315 ; AVX512DQVL: # %bb.0:
316 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
317 ; AVX512DQVL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
318 ; AVX512DQVL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
319 ; AVX512DQVL-NEXT: vpmovdw %ymm0, %xmm0
320 ; AVX512DQVL-NEXT: vzeroupper
321 ; AVX512DQVL-NEXT: retq
322 ;
323 ; AVX512BWVL-LABEL: var_shift_v8i16:
324 ; AVX512BWVL: # %bb.0:
325 ; AVX512BWVL-NEXT: vpsrlvw %xmm1, %xmm0, %xmm0
326 ; AVX512BWVL-NEXT: retq
327 ;
328 ; X32-SSE-LABEL: var_shift_v8i16:
329 ; X32-SSE: # %bb.0:
330 ; X32-SSE-NEXT: psllw $12, %xmm1
331 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
332 ; X32-SSE-NEXT: psraw $15, %xmm2
333 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
334 ; X32-SSE-NEXT: pandn %xmm0, %xmm3
335 ; X32-SSE-NEXT: psrlw $8, %xmm0
336 ; X32-SSE-NEXT: pand %xmm2, %xmm0
337 ; X32-SSE-NEXT: por %xmm3, %xmm0
338 ; X32-SSE-NEXT: paddw %xmm1, %xmm1
339 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
340 ; X32-SSE-NEXT: psraw $15, %xmm2
341 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
342 ; X32-SSE-NEXT: pandn %xmm0, %xmm3
343 ; X32-SSE-NEXT: psrlw $4, %xmm0
344 ; X32-SSE-NEXT: pand %xmm2, %xmm0
345 ; X32-SSE-NEXT: por %xmm3, %xmm0
346 ; X32-SSE-NEXT: paddw %xmm1, %xmm1
347 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
348 ; X32-SSE-NEXT: psraw $15, %xmm2
349 ; X32-SSE-NEXT: movdqa %xmm2, %xmm3
350 ; X32-SSE-NEXT: pandn %xmm0, %xmm3
351 ; X32-SSE-NEXT: psrlw $2, %xmm0
352 ; X32-SSE-NEXT: pand %xmm2, %xmm0
353 ; X32-SSE-NEXT: por %xmm3, %xmm0
354 ; X32-SSE-NEXT: paddw %xmm1, %xmm1
355 ; X32-SSE-NEXT: psraw $15, %xmm1
356 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
357 ; X32-SSE-NEXT: pandn %xmm0, %xmm2
358 ; X32-SSE-NEXT: psrlw $1, %xmm0
359 ; X32-SSE-NEXT: pand %xmm1, %xmm0
360 ; X32-SSE-NEXT: por %xmm2, %xmm0
361 ; X32-SSE-NEXT: retl
362 %shift = lshr <8 x i16> %a, %b
363 ret <8 x i16> %shift
364 }
366 define <16 x i8> @var_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
367 ; SSE2-LABEL: var_shift_v16i8:
368 ; SSE2: # %bb.0:
369 ; SSE2-NEXT: psllw $5, %xmm1
370 ; SSE2-NEXT: pxor %xmm2, %xmm2
371 ; SSE2-NEXT: pxor %xmm3, %xmm3
372 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm3
373 ; SSE2-NEXT: movdqa %xmm3, %xmm4
374 ; SSE2-NEXT: pandn %xmm0, %xmm4
375 ; SSE2-NEXT: psrlw $4, %xmm0
376 ; SSE2-NEXT: pand %xmm3, %xmm0
377 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
378 ; SSE2-NEXT: por %xmm4, %xmm0
379 ; SSE2-NEXT: paddb %xmm1, %xmm1
380 ; SSE2-NEXT: pxor %xmm3, %xmm3
381 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm3
382 ; SSE2-NEXT: movdqa %xmm3, %xmm4
383 ; SSE2-NEXT: pandn %xmm0, %xmm4
384 ; SSE2-NEXT: psrlw $2, %xmm0
385 ; SSE2-NEXT: pand %xmm3, %xmm0
386 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
387 ; SSE2-NEXT: por %xmm4, %xmm0
388 ; SSE2-NEXT: paddb %xmm1, %xmm1
389 ; SSE2-NEXT: pcmpgtb %xmm1, %xmm2
390 ; SSE2-NEXT: movdqa %xmm2, %xmm1
391 ; SSE2-NEXT: pandn %xmm0, %xmm1
392 ; SSE2-NEXT: psrlw $1, %xmm0
393 ; SSE2-NEXT: pand %xmm2, %xmm0
394 ; SSE2-NEXT: pand {{.*}}(%rip), %xmm0
395 ; SSE2-NEXT: por %xmm1, %xmm0
396 ; SSE2-NEXT: retq
397 ;
398 ; SSE41-LABEL: var_shift_v16i8:
399 ; SSE41: # %bb.0:
400 ; SSE41-NEXT: movdqa %xmm0, %xmm2
401 ; SSE41-NEXT: psllw $5, %xmm1
402 ; SSE41-NEXT: movdqa %xmm0, %xmm3
403 ; SSE41-NEXT: psrlw $4, %xmm3
404 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm3
405 ; SSE41-NEXT: movdqa %xmm1, %xmm0
406 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
407 ; SSE41-NEXT: movdqa %xmm2, %xmm3
408 ; SSE41-NEXT: psrlw $2, %xmm3
409 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm3
410 ; SSE41-NEXT: paddb %xmm1, %xmm1
411 ; SSE41-NEXT: movdqa %xmm1, %xmm0
412 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
413 ; SSE41-NEXT: movdqa %xmm2, %xmm3
414 ; SSE41-NEXT: psrlw $1, %xmm3
415 ; SSE41-NEXT: pand {{.*}}(%rip), %xmm3
416 ; SSE41-NEXT: paddb %xmm1, %xmm1
417 ; SSE41-NEXT: movdqa %xmm1, %xmm0
418 ; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm2
419 ; SSE41-NEXT: movdqa %xmm2, %xmm0
420 ; SSE41-NEXT: retq
421 ;
422 ; AVX-LABEL: var_shift_v16i8:
423 ; AVX: # %bb.0:
424 ; AVX-NEXT: vpsllw $5, %xmm1, %xmm1
425 ; AVX-NEXT: vpsrlw $4, %xmm0, %xmm2
426 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
427 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
428 ; AVX-NEXT: vpsrlw $2, %xmm0, %xmm2
429 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
430 ; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1
431 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
432 ; AVX-NEXT: vpsrlw $1, %xmm0, %xmm2
433 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm2, %xmm2
434 ; AVX-NEXT: vpaddb %xmm1, %xmm1, %xmm1
435 ; AVX-NEXT: vpblendvb %xmm1, %xmm2, %xmm0, %xmm0
436 ; AVX-NEXT: retq
437 ;
438 ; XOP-LABEL: var_shift_v16i8:
439 ; XOP: # %bb.0:
440 ; XOP-NEXT: vpxor %xmm2, %xmm2, %xmm2
441 ; XOP-NEXT: vpsubb %xmm1, %xmm2, %xmm1
442 ; XOP-NEXT: vpshlb %xmm1, %xmm0, %xmm0
443 ; XOP-NEXT: retq
444 ;
445 ; AVX512DQ-LABEL: var_shift_v16i8:
446 ; AVX512DQ: # %bb.0:
447 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
448 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
449 ; AVX512DQ-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
450 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
451 ; AVX512DQ-NEXT: vzeroupper
452 ; AVX512DQ-NEXT: retq
453 ;
454 ; AVX512BW-LABEL: var_shift_v16i8:
455 ; AVX512BW: # %bb.0:
456 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
457 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
458 ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
459 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
460 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
461 ; AVX512BW-NEXT: vzeroupper
462 ; AVX512BW-NEXT: retq
463 ;
464 ; AVX512DQVL-LABEL: var_shift_v16i8:
465 ; AVX512DQVL: # %bb.0:
466 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
467 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
468 ; AVX512DQVL-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
469 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
470 ; AVX512DQVL-NEXT: vzeroupper
471 ; AVX512DQVL-NEXT: retq
472 ;
473 ; AVX512BWVL-LABEL: var_shift_v16i8:
474 ; AVX512BWVL: # %bb.0:
475 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
476 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
477 ; AVX512BWVL-NEXT: vpsrlvw %ymm1, %ymm0, %ymm0
478 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
479 ; AVX512BWVL-NEXT: vzeroupper
480 ; AVX512BWVL-NEXT: retq
481 ;
482 ; X32-SSE-LABEL: var_shift_v16i8:
483 ; X32-SSE: # %bb.0:
484 ; X32-SSE-NEXT: psllw $5, %xmm1
485 ; X32-SSE-NEXT: pxor %xmm2, %xmm2
486 ; X32-SSE-NEXT: pxor %xmm3, %xmm3
487 ; X32-SSE-NEXT: pcmpgtb %xmm1, %xmm3
488 ; X32-SSE-NEXT: movdqa %xmm3, %xmm4
489 ; X32-SSE-NEXT: pandn %xmm0, %xmm4
490 ; X32-SSE-NEXT: psrlw $4, %xmm0
491 ; X32-SSE-NEXT: pand %xmm3, %xmm0
492 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
493 ; X32-SSE-NEXT: por %xmm4, %xmm0
494 ; X32-SSE-NEXT: paddb %xmm1, %xmm1
495 ; X32-SSE-NEXT: pxor %xmm3, %xmm3
496 ; X32-SSE-NEXT: pcmpgtb %xmm1, %xmm3
497 ; X32-SSE-NEXT: movdqa %xmm3, %xmm4
498 ; X32-SSE-NEXT: pandn %xmm0, %xmm4
499 ; X32-SSE-NEXT: psrlw $2, %xmm0
500 ; X32-SSE-NEXT: pand %xmm3, %xmm0
501 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
502 ; X32-SSE-NEXT: por %xmm4, %xmm0
503 ; X32-SSE-NEXT: paddb %xmm1, %xmm1
504 ; X32-SSE-NEXT: pcmpgtb %xmm1, %xmm2
505 ; X32-SSE-NEXT: movdqa %xmm2, %xmm1
506 ; X32-SSE-NEXT: pandn %xmm0, %xmm1
507 ; X32-SSE-NEXT: psrlw $1, %xmm0
508 ; X32-SSE-NEXT: pand %xmm2, %xmm0
509 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
510 ; X32-SSE-NEXT: por %xmm1, %xmm0
511 ; X32-SSE-NEXT: retl
512 %shift = lshr <16 x i8> %a, %b
513 ret <16 x i8> %shift
514 }
516 ;
517 ; Uniform Variable Shifts
518 ;
520 define <2 x i64> @splatvar_shift_v2i64(<2 x i64> %a, <2 x i64> %b) nounwind {
521 ; SSE-LABEL: splatvar_shift_v2i64:
522 ; SSE: # %bb.0:
523 ; SSE-NEXT: psrlq %xmm1, %xmm0
524 ; SSE-NEXT: retq
525 ;
526 ; AVX-LABEL: splatvar_shift_v2i64:
527 ; AVX: # %bb.0:
528 ; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
529 ; AVX-NEXT: retq
530 ;
531 ; XOP-LABEL: splatvar_shift_v2i64:
532 ; XOP: # %bb.0:
533 ; XOP-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
534 ; XOP-NEXT: retq
535 ;
536 ; AVX512-LABEL: splatvar_shift_v2i64:
537 ; AVX512: # %bb.0:
538 ; AVX512-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
539 ; AVX512-NEXT: retq
540 ;
541 ; AVX512VL-LABEL: splatvar_shift_v2i64:
542 ; AVX512VL: # %bb.0:
543 ; AVX512VL-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
544 ; AVX512VL-NEXT: retq
545 ;
546 ; X32-SSE-LABEL: splatvar_shift_v2i64:
547 ; X32-SSE: # %bb.0:
548 ; X32-SSE-NEXT: psrlq %xmm1, %xmm0
549 ; X32-SSE-NEXT: retl
550 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
551 %shift = lshr <2 x i64> %a, %splat
552 ret <2 x i64> %shift
553 }
555 define <4 x i32> @splatvar_shift_v4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
556 ; SSE2-LABEL: splatvar_shift_v4i32:
557 ; SSE2: # %bb.0:
558 ; SSE2-NEXT: xorps %xmm2, %xmm2
559 ; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
560 ; SSE2-NEXT: psrld %xmm2, %xmm0
561 ; SSE2-NEXT: retq
562 ;
563 ; SSE41-LABEL: splatvar_shift_v4i32:
564 ; SSE41: # %bb.0:
565 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
566 ; SSE41-NEXT: psrld %xmm1, %xmm0
567 ; SSE41-NEXT: retq
568 ;
569 ; AVX-LABEL: splatvar_shift_v4i32:
570 ; AVX: # %bb.0:
571 ; AVX-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
572 ; AVX-NEXT: vpsrld %xmm1, %xmm0, %xmm0
573 ; AVX-NEXT: retq
574 ;
575 ; XOP-LABEL: splatvar_shift_v4i32:
576 ; XOP: # %bb.0:
577 ; XOP-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
578 ; XOP-NEXT: vpsrld %xmm1, %xmm0, %xmm0
579 ; XOP-NEXT: retq
580 ;
581 ; AVX512-LABEL: splatvar_shift_v4i32:
582 ; AVX512: # %bb.0:
583 ; AVX512-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
584 ; AVX512-NEXT: vpsrld %xmm1, %xmm0, %xmm0
585 ; AVX512-NEXT: retq
586 ;
587 ; AVX512VL-LABEL: splatvar_shift_v4i32:
588 ; AVX512VL: # %bb.0:
589 ; AVX512VL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
590 ; AVX512VL-NEXT: vpsrld %xmm1, %xmm0, %xmm0
591 ; AVX512VL-NEXT: retq
592 ;
593 ; X32-SSE-LABEL: splatvar_shift_v4i32:
594 ; X32-SSE: # %bb.0:
595 ; X32-SSE-NEXT: xorps %xmm2, %xmm2
596 ; X32-SSE-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3]
597 ; X32-SSE-NEXT: psrld %xmm2, %xmm0
598 ; X32-SSE-NEXT: retl
599 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
600 %shift = lshr <4 x i32> %a, %splat
601 ret <4 x i32> %shift
602 }
604 define <8 x i16> @splatvar_shift_v8i16(<8 x i16> %a, <8 x i16> %b) nounwind {
605 ; SSE2-LABEL: splatvar_shift_v8i16:
606 ; SSE2: # %bb.0:
607 ; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
608 ; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
609 ; SSE2-NEXT: psrlw %xmm1, %xmm0
610 ; SSE2-NEXT: retq
611 ;
612 ; SSE41-LABEL: splatvar_shift_v8i16:
613 ; SSE41: # %bb.0:
614 ; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
615 ; SSE41-NEXT: psrlw %xmm1, %xmm0
616 ; SSE41-NEXT: retq
617 ;
618 ; AVX-LABEL: splatvar_shift_v8i16:
619 ; AVX: # %bb.0:
620 ; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
621 ; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
622 ; AVX-NEXT: retq
623 ;
624 ; XOP-LABEL: splatvar_shift_v8i16:
625 ; XOP: # %bb.0:
626 ; XOP-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
627 ; XOP-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
628 ; XOP-NEXT: retq
629 ;
630 ; AVX512-LABEL: splatvar_shift_v8i16:
631 ; AVX512: # %bb.0:
632 ; AVX512-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
633 ; AVX512-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
634 ; AVX512-NEXT: retq
635 ;
636 ; AVX512VL-LABEL: splatvar_shift_v8i16:
637 ; AVX512VL: # %bb.0:
638 ; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
639 ; AVX512VL-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
640 ; AVX512VL-NEXT: retq
641 ;
642 ; X32-SSE-LABEL: splatvar_shift_v8i16:
643 ; X32-SSE: # %bb.0:
644 ; X32-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
645 ; X32-SSE-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
646 ; X32-SSE-NEXT: psrlw %xmm1, %xmm0
647 ; X32-SSE-NEXT: retl
648 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer
649 %shift = lshr <8 x i16> %a, %splat
650 ret <8 x i16> %shift
651 }
653 define <16 x i8> @splatvar_shift_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
654 ; SSE2-LABEL: splatvar_shift_v16i8:
655 ; SSE2: # %bb.0:
656 ; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
657 ; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
658 ; SSE2-NEXT: psrlw %xmm1, %xmm0
659 ; SSE2-NEXT: pcmpeqd %xmm2, %xmm2
660 ; SSE2-NEXT: psrlw %xmm1, %xmm2
661 ; SSE2-NEXT: psrlw $8, %xmm2
662 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
663 ; SSE2-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,2,3,4,5,6,7]
664 ; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
665 ; SSE2-NEXT: pand %xmm1, %xmm0
666 ; SSE2-NEXT: retq
667 ;
668 ; SSE41-LABEL: splatvar_shift_v16i8:
669 ; SSE41: # %bb.0:
670 ; SSE41-NEXT: pmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
671 ; SSE41-NEXT: psrlw %xmm1, %xmm0
672 ; SSE41-NEXT: pcmpeqd %xmm2, %xmm2
673 ; SSE41-NEXT: psrlw %xmm1, %xmm2
674 ; SSE41-NEXT: pshufb {{.*#+}} xmm2 = xmm2[1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
675 ; SSE41-NEXT: pand %xmm2, %xmm0
676 ; SSE41-NEXT: retq
677 ;
678 ; AVX1-LABEL: splatvar_shift_v16i8:
679 ; AVX1: # %bb.0:
680 ; AVX1-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
681 ; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
682 ; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
683 ; AVX1-NEXT: vpsrlw %xmm1, %xmm2, %xmm1
684 ; AVX1-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
685 ; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0
686 ; AVX1-NEXT: retq
687 ;
688 ; AVX2-LABEL: splatvar_shift_v16i8:
689 ; AVX2: # %bb.0:
690 ; AVX2-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero
691 ; AVX2-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
692 ; AVX2-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2
693 ; AVX2-NEXT: vpsrlw %xmm1, %xmm2, %xmm1
694 ; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1
695 ; AVX2-NEXT: vpbroadcastb %xmm1, %xmm1
696 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
697 ; AVX2-NEXT: retq
698 ;
699 ; XOPAVX1-LABEL: splatvar_shift_v16i8:
700 ; XOPAVX1: # %bb.0:
701 ; XOPAVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
702 ; XOPAVX1-NEXT: vpshufb %xmm2, %xmm1, %xmm1
703 ; XOPAVX1-NEXT: vpsubb %xmm1, %xmm2, %xmm1
704 ; XOPAVX1-NEXT: vpshlb %xmm1, %xmm0, %xmm0
705 ; XOPAVX1-NEXT: retq
706 ;
707 ; XOPAVX2-LABEL: splatvar_shift_v16i8:
708 ; XOPAVX2: # %bb.0:
709 ; XOPAVX2-NEXT: vpbroadcastb %xmm1, %xmm1
710 ; XOPAVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
711 ; XOPAVX2-NEXT: vpsubb %xmm1, %xmm2, %xmm1
712 ; XOPAVX2-NEXT: vpshlb %xmm1, %xmm0, %xmm0
713 ; XOPAVX2-NEXT: retq
714 ;
715 ; AVX512DQ-LABEL: splatvar_shift_v16i8:
716 ; AVX512DQ: # %bb.0:
717 ; AVX512DQ-NEXT: vpbroadcastb %xmm1, %xmm1
718 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
719 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
720 ; AVX512DQ-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
721 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
722 ; AVX512DQ-NEXT: vzeroupper
723 ; AVX512DQ-NEXT: retq
724 ;
725 ; AVX512BW-LABEL: splatvar_shift_v16i8:
726 ; AVX512BW: # %bb.0:
727 ; AVX512BW-NEXT: vpbroadcastb %xmm1, %xmm1
728 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
729 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
730 ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
731 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
732 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
733 ; AVX512BW-NEXT: vzeroupper
734 ; AVX512BW-NEXT: retq
735 ;
736 ; AVX512DQVL-LABEL: splatvar_shift_v16i8:
737 ; AVX512DQVL: # %bb.0:
738 ; AVX512DQVL-NEXT: vpbroadcastb %xmm1, %xmm1
739 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
740 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
741 ; AVX512DQVL-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
742 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
743 ; AVX512DQVL-NEXT: vzeroupper
744 ; AVX512DQVL-NEXT: retq
745 ;
746 ; AVX512BWVL-LABEL: splatvar_shift_v16i8:
747 ; AVX512BWVL: # %bb.0:
748 ; AVX512BWVL-NEXT: vpbroadcastb %xmm1, %xmm1
749 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
750 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
751 ; AVX512BWVL-NEXT: vpsrlvw %ymm1, %ymm0, %ymm0
752 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
753 ; AVX512BWVL-NEXT: vzeroupper
754 ; AVX512BWVL-NEXT: retq
755 ;
756 ; X32-SSE-LABEL: splatvar_shift_v16i8:
757 ; X32-SSE: # %bb.0:
758 ; X32-SSE-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0]
759 ; X32-SSE-NEXT: psrldq {{.*#+}} xmm1 = xmm1[15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
760 ; X32-SSE-NEXT: psrlw %xmm1, %xmm0
761 ; X32-SSE-NEXT: pcmpeqd %xmm2, %xmm2
762 ; X32-SSE-NEXT: psrlw %xmm1, %xmm2
763 ; X32-SSE-NEXT: psrlw $8, %xmm2
764 ; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
765 ; X32-SSE-NEXT: pshuflw {{.*#+}} xmm1 = xmm2[0,0,2,3,4,5,6,7]
766 ; X32-SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
767 ; X32-SSE-NEXT: pand %xmm1, %xmm0
768 ; X32-SSE-NEXT: retl
769 %splat = shufflevector <16 x i8> %b, <16 x i8> undef, <16 x i32> zeroinitializer
770 %shift = lshr <16 x i8> %a, %splat
771 ret <16 x i8> %shift
772 }
774 ;
775 ; Constant Shifts
776 ;
778 define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind {
779 ; SSE2-LABEL: constant_shift_v2i64:
780 ; SSE2: # %bb.0:
781 ; SSE2-NEXT: movdqa %xmm0, %xmm1
782 ; SSE2-NEXT: psrlq $1, %xmm1
783 ; SSE2-NEXT: psrlq $7, %xmm0
784 ; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
785 ; SSE2-NEXT: retq
786 ;
787 ; SSE41-LABEL: constant_shift_v2i64:
788 ; SSE41: # %bb.0:
789 ; SSE41-NEXT: movdqa %xmm0, %xmm1
790 ; SSE41-NEXT: psrlq $7, %xmm1
791 ; SSE41-NEXT: psrlq $1, %xmm0
792 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
793 ; SSE41-NEXT: retq
794 ;
795 ; AVX1-LABEL: constant_shift_v2i64:
796 ; AVX1: # %bb.0:
797 ; AVX1-NEXT: vpsrlq $7, %xmm0, %xmm1
798 ; AVX1-NEXT: vpsrlq $1, %xmm0, %xmm0
799 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
800 ; AVX1-NEXT: retq
801 ;
802 ; AVX2-LABEL: constant_shift_v2i64:
803 ; AVX2: # %bb.0:
804 ; AVX2-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
805 ; AVX2-NEXT: retq
806 ;
807 ; XOPAVX1-LABEL: constant_shift_v2i64:
808 ; XOPAVX1: # %bb.0:
809 ; XOPAVX1-NEXT: vpshlq {{.*}}(%rip), %xmm0, %xmm0
810 ; XOPAVX1-NEXT: retq
811 ;
812 ; XOPAVX2-LABEL: constant_shift_v2i64:
813 ; XOPAVX2: # %bb.0:
814 ; XOPAVX2-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
815 ; XOPAVX2-NEXT: retq
816 ;
817 ; AVX512-LABEL: constant_shift_v2i64:
818 ; AVX512: # %bb.0:
819 ; AVX512-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
820 ; AVX512-NEXT: retq
821 ;
822 ; AVX512VL-LABEL: constant_shift_v2i64:
823 ; AVX512VL: # %bb.0:
824 ; AVX512VL-NEXT: vpsrlvq {{.*}}(%rip), %xmm0, %xmm0
825 ; AVX512VL-NEXT: retq
826 ;
827 ; X32-SSE-LABEL: constant_shift_v2i64:
828 ; X32-SSE: # %bb.0:
829 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
830 ; X32-SSE-NEXT: psrlq $1, %xmm1
831 ; X32-SSE-NEXT: psrlq $7, %xmm0
832 ; X32-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1]
833 ; X32-SSE-NEXT: retl
834 %shift = lshr <2 x i64> %a, <i64 1, i64 7>
835 ret <2 x i64> %shift
836 }
838 define <4 x i32> @constant_shift_v4i32(<4 x i32> %a) nounwind {
839 ; SSE2-LABEL: constant_shift_v4i32:
840 ; SSE2: # %bb.0:
841 ; SSE2-NEXT: movdqa %xmm0, %xmm1
842 ; SSE2-NEXT: psrld $7, %xmm1
843 ; SSE2-NEXT: movdqa %xmm0, %xmm2
844 ; SSE2-NEXT: psrld $6, %xmm2
845 ; SSE2-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]
846 ; SSE2-NEXT: movdqa %xmm0, %xmm1
847 ; SSE2-NEXT: psrld $5, %xmm1
848 ; SSE2-NEXT: psrld $4, %xmm0
849 ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
850 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3]
851 ; SSE2-NEXT: retq
852 ;
853 ; SSE41-LABEL: constant_shift_v4i32:
854 ; SSE41: # %bb.0:
855 ; SSE41-NEXT: movdqa %xmm0, %xmm1
856 ; SSE41-NEXT: psrld $7, %xmm1
857 ; SSE41-NEXT: movdqa %xmm0, %xmm2
858 ; SSE41-NEXT: psrld $5, %xmm2
859 ; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm2[0,1,2,3],xmm1[4,5,6,7]
860 ; SSE41-NEXT: movdqa %xmm0, %xmm1
861 ; SSE41-NEXT: psrld $6, %xmm1
862 ; SSE41-NEXT: psrld $4, %xmm0
863 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm1[4,5,6,7]
864 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3],xmm0[4,5],xmm2[6,7]
865 ; SSE41-NEXT: retq
866 ;
867 ; AVX1-LABEL: constant_shift_v4i32:
868 ; AVX1: # %bb.0:
869 ; AVX1-NEXT: vpsrld $7, %xmm0, %xmm1
870 ; AVX1-NEXT: vpsrld $5, %xmm0, %xmm2
871 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm2[0,1,2,3],xmm1[4,5,6,7]
872 ; AVX1-NEXT: vpsrld $6, %xmm0, %xmm2
873 ; AVX1-NEXT: vpsrld $4, %xmm0, %xmm0
874 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7]
875 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
876 ; AVX1-NEXT: retq
877 ;
878 ; AVX2-LABEL: constant_shift_v4i32:
879 ; AVX2: # %bb.0:
880 ; AVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
881 ; AVX2-NEXT: retq
882 ;
883 ; XOPAVX1-LABEL: constant_shift_v4i32:
884 ; XOPAVX1: # %bb.0:
885 ; XOPAVX1-NEXT: vpshld {{.*}}(%rip), %xmm0, %xmm0
886 ; XOPAVX1-NEXT: retq
887 ;
888 ; XOPAVX2-LABEL: constant_shift_v4i32:
889 ; XOPAVX2: # %bb.0:
890 ; XOPAVX2-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
891 ; XOPAVX2-NEXT: retq
892 ;
893 ; AVX512-LABEL: constant_shift_v4i32:
894 ; AVX512: # %bb.0:
895 ; AVX512-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
896 ; AVX512-NEXT: retq
897 ;
898 ; AVX512VL-LABEL: constant_shift_v4i32:
899 ; AVX512VL: # %bb.0:
900 ; AVX512VL-NEXT: vpsrlvd {{.*}}(%rip), %xmm0, %xmm0
901 ; AVX512VL-NEXT: retq
902 ;
903 ; X32-SSE-LABEL: constant_shift_v4i32:
904 ; X32-SSE: # %bb.0:
905 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
906 ; X32-SSE-NEXT: psrld $7, %xmm1
907 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
908 ; X32-SSE-NEXT: psrld $6, %xmm2
909 ; X32-SSE-NEXT: punpckhqdq {{.*#+}} xmm2 = xmm2[1],xmm1[1]
910 ; X32-SSE-NEXT: movdqa %xmm0, %xmm1
911 ; X32-SSE-NEXT: psrld $5, %xmm1
912 ; X32-SSE-NEXT: psrld $4, %xmm0
913 ; X32-SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
914 ; X32-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3],xmm2[0,3]
915 ; X32-SSE-NEXT: retl
916 %shift = lshr <4 x i32> %a, <i32 4, i32 5, i32 6, i32 7>
917 ret <4 x i32> %shift
918 }
920 define <8 x i16> @constant_shift_v8i16(<8 x i16> %a) nounwind {
921 ; SSE2-LABEL: constant_shift_v8i16:
922 ; SSE2: # %bb.0:
923 ; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
924 ; SSE2-NEXT: movdqa %xmm1, %xmm2
925 ; SSE2-NEXT: pandn %xmm0, %xmm2
926 ; SSE2-NEXT: pmulhuw {{.*}}(%rip), %xmm0
927 ; SSE2-NEXT: pand %xmm1, %xmm0
928 ; SSE2-NEXT: por %xmm2, %xmm0
929 ; SSE2-NEXT: retq
930 ;
931 ; SSE41-LABEL: constant_shift_v8i16:
932 ; SSE41: # %bb.0:
933 ; SSE41-NEXT: movdqa {{.*#+}} xmm1 = <u,32768,16384,8192,4096,2048,1024,512>
934 ; SSE41-NEXT: pmulhuw %xmm0, %xmm1
935 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
936 ; SSE41-NEXT: retq
937 ;
938 ; AVX-LABEL: constant_shift_v8i16:
939 ; AVX: # %bb.0:
940 ; AVX-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
941 ; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
942 ; AVX-NEXT: retq
943 ;
944 ; XOP-LABEL: constant_shift_v8i16:
945 ; XOP: # %bb.0:
946 ; XOP-NEXT: vpshlw {{.*}}(%rip), %xmm0, %xmm0
947 ; XOP-NEXT: retq
948 ;
949 ; AVX512DQ-LABEL: constant_shift_v8i16:
950 ; AVX512DQ: # %bb.0:
951 ; AVX512DQ-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
952 ; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
953 ; AVX512DQ-NEXT: retq
954 ;
955 ; AVX512BW-LABEL: constant_shift_v8i16:
956 ; AVX512BW: # %bb.0:
957 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
958 ; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm1 = [0,1,2,3,4,5,6,7]
959 ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
960 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
961 ; AVX512BW-NEXT: vzeroupper
962 ; AVX512BW-NEXT: retq
963 ;
964 ; AVX512DQVL-LABEL: constant_shift_v8i16:
965 ; AVX512DQVL: # %bb.0:
966 ; AVX512DQVL-NEXT: vpmulhuw {{.*}}(%rip), %xmm0, %xmm1
967 ; AVX512DQVL-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3,4,5,6,7]
968 ; AVX512DQVL-NEXT: retq
969 ;
970 ; AVX512BWVL-LABEL: constant_shift_v8i16:
971 ; AVX512BWVL: # %bb.0:
972 ; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %xmm0, %xmm0
973 ; AVX512BWVL-NEXT: retq
974 ;
975 ; X32-SSE-LABEL: constant_shift_v8i16:
976 ; X32-SSE: # %bb.0:
977 ; X32-SSE-NEXT: movdqa {{.*#+}} xmm1 = [0,65535,65535,65535,65535,65535,65535,65535]
978 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
979 ; X32-SSE-NEXT: pandn %xmm0, %xmm2
980 ; X32-SSE-NEXT: pmulhuw {{\.LCPI.*}}, %xmm0
981 ; X32-SSE-NEXT: pand %xmm1, %xmm0
982 ; X32-SSE-NEXT: por %xmm2, %xmm0
983 ; X32-SSE-NEXT: retl
984 %shift = lshr <8 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>
985 ret <8 x i16> %shift
986 }
988 define <16 x i8> @constant_shift_v16i8(<16 x i8> %a) nounwind {
989 ; SSE2-LABEL: constant_shift_v16i8:
990 ; SSE2: # %bb.0:
991 ; SSE2-NEXT: pxor %xmm1, %xmm1
992 ; SSE2-NEXT: movdqa %xmm0, %xmm2
993 ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
994 ; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm2
995 ; SSE2-NEXT: psrlw $8, %xmm2
996 ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
997 ; SSE2-NEXT: pmullw {{.*}}(%rip), %xmm0
998 ; SSE2-NEXT: psrlw $8, %xmm0
999 ; SSE2-NEXT: packuswb %xmm2, %xmm0
1000 ; SSE2-NEXT: retq
1001 ;
1002 ; SSE41-LABEL: constant_shift_v16i8:
1003 ; SSE41: # %bb.0:
1004 ; SSE41-NEXT: pxor %xmm2, %xmm2
1005 ; SSE41-NEXT: pmovzxbw {{.*#+}} xmm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
1006 ; SSE41-NEXT: punpckhbw {{.*#+}} xmm0 = xmm0[8],xmm2[8],xmm0[9],xmm2[9],xmm0[10],xmm2[10],xmm0[11],xmm2[11],xmm0[12],xmm2[12],xmm0[13],xmm2[13],xmm0[14],xmm2[14],xmm0[15],xmm2[15]
1007 ; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm0
1008 ; SSE41-NEXT: psrlw $8, %xmm0
1009 ; SSE41-NEXT: pmullw {{.*}}(%rip), %xmm1
1010 ; SSE41-NEXT: psrlw $8, %xmm1
1011 ; SSE41-NEXT: packuswb %xmm0, %xmm1
1012 ; SSE41-NEXT: movdqa %xmm1, %xmm0
1013 ; SSE41-NEXT: retq
1014 ;
1015 ; AVX1-LABEL: constant_shift_v16i8:
1016 ; AVX1: # %bb.0:
1017 ; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1
1018 ; AVX1-NEXT: vpunpckhbw {{.*#+}} xmm1 = xmm0[8],xmm1[8],xmm0[9],xmm1[9],xmm0[10],xmm1[10],xmm0[11],xmm1[11],xmm0[12],xmm1[12],xmm0[13],xmm1[13],xmm0[14],xmm1[14],xmm0[15],xmm1[15]
1019 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm1, %xmm1
1020 ; AVX1-NEXT: vpsrlw $8, %xmm1, %xmm1
1021 ; AVX1-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
1022 ; AVX1-NEXT: vpmullw {{.*}}(%rip), %xmm0, %xmm0
1023 ; AVX1-NEXT: vpsrlw $8, %xmm0, %xmm0
1024 ; AVX1-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1025 ; AVX1-NEXT: retq
1026 ;
1027 ; AVX2-LABEL: constant_shift_v16i8:
1028 ; AVX2: # %bb.0:
1029 ; AVX2-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1030 ; AVX2-NEXT: vpmullw {{.*}}(%rip), %ymm0, %ymm0
1031 ; AVX2-NEXT: vpsrlw $8, %ymm0, %ymm0
1032 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1
1033 ; AVX2-NEXT: vpackuswb %xmm1, %xmm0, %xmm0
1034 ; AVX2-NEXT: vzeroupper
1035 ; AVX2-NEXT: retq
1036 ;
1037 ; XOP-LABEL: constant_shift_v16i8:
1038 ; XOP: # %bb.0:
1039 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
1040 ; XOP-NEXT: retq
1041 ;
1042 ; AVX512DQ-LABEL: constant_shift_v16i8:
1043 ; AVX512DQ: # %bb.0:
1044 ; AVX512DQ-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
1045 ; AVX512DQ-NEXT: vpsrlvd {{.*}}(%rip), %zmm0, %zmm0
1046 ; AVX512DQ-NEXT: vpmovdb %zmm0, %xmm0
1047 ; AVX512DQ-NEXT: vzeroupper
1048 ; AVX512DQ-NEXT: retq
1049 ;
1050 ; AVX512BW-LABEL: constant_shift_v16i8:
1051 ; AVX512BW: # %bb.0:
1052 ; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm1 = [0,1,2,3,4,5,6,7,7,6,5,4,3,2,1,0]
1053 ; AVX512BW-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1054 ; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
1055 ; AVX512BW-NEXT: vpmovwb %zmm0, %ymm0
1056 ; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
1057 ; AVX512BW-NEXT: vzeroupper
1058 ; AVX512BW-NEXT: retq
1059 ;
1060 ; AVX512DQVL-LABEL: constant_shift_v16i8:
1061 ; AVX512DQVL: # %bb.0:
1062 ; AVX512DQVL-NEXT: vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
1063 ; AVX512DQVL-NEXT: vpsrlvd {{.*}}(%rip), %zmm0, %zmm0
1064 ; AVX512DQVL-NEXT: vpmovdb %zmm0, %xmm0
1065 ; AVX512DQVL-NEXT: vzeroupper
1066 ; AVX512DQVL-NEXT: retq
1067 ;
1068 ; AVX512BWVL-LABEL: constant_shift_v16i8:
1069 ; AVX512BWVL: # %bb.0:
1070 ; AVX512BWVL-NEXT: vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
1071 ; AVX512BWVL-NEXT: vpsrlvw {{.*}}(%rip), %ymm0, %ymm0
1072 ; AVX512BWVL-NEXT: vpmovwb %ymm0, %xmm0
1073 ; AVX512BWVL-NEXT: vzeroupper
1074 ; AVX512BWVL-NEXT: retq
1075 ;
1076 ; X32-SSE-LABEL: constant_shift_v16i8:
1077 ; X32-SSE: # %bb.0:
1078 ; X32-SSE-NEXT: pxor %xmm1, %xmm1
1079 ; X32-SSE-NEXT: movdqa %xmm0, %xmm2
1080 ; X32-SSE-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm1[8],xmm2[9],xmm1[9],xmm2[10],xmm1[10],xmm2[11],xmm1[11],xmm2[12],xmm1[12],xmm2[13],xmm1[13],xmm2[14],xmm1[14],xmm2[15],xmm1[15]
1081 ; X32-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm2
1082 ; X32-SSE-NEXT: psrlw $8, %xmm2
1083 ; X32-SSE-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]
1084 ; X32-SSE-NEXT: pmullw {{\.LCPI.*}}, %xmm0
1085 ; X32-SSE-NEXT: psrlw $8, %xmm0
1086 ; X32-SSE-NEXT: packuswb %xmm2, %xmm0
1087 ; X32-SSE-NEXT: retl
1088 %shift = lshr <16 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
1089 ret <16 x i8> %shift
1090 }
1092 ;
1093 ; Uniform Constant Shifts
1094 ;
1096 define <2 x i64> @splatconstant_shift_v2i64(<2 x i64> %a) nounwind {
1097 ; SSE-LABEL: splatconstant_shift_v2i64:
1098 ; SSE: # %bb.0:
1099 ; SSE-NEXT: psrlq $7, %xmm0
1100 ; SSE-NEXT: retq
1101 ;
1102 ; AVX-LABEL: splatconstant_shift_v2i64:
1103 ; AVX: # %bb.0:
1104 ; AVX-NEXT: vpsrlq $7, %xmm0, %xmm0
1105 ; AVX-NEXT: retq
1106 ;
1107 ; XOP-LABEL: splatconstant_shift_v2i64:
1108 ; XOP: # %bb.0:
1109 ; XOP-NEXT: vpsrlq $7, %xmm0, %xmm0
1110 ; XOP-NEXT: retq
1111 ;
1112 ; AVX512-LABEL: splatconstant_shift_v2i64:
1113 ; AVX512: # %bb.0:
1114 ; AVX512-NEXT: vpsrlq $7, %xmm0, %xmm0
1115 ; AVX512-NEXT: retq
1116 ;
1117 ; AVX512VL-LABEL: splatconstant_shift_v2i64:
1118 ; AVX512VL: # %bb.0:
1119 ; AVX512VL-NEXT: vpsrlq $7, %xmm0, %xmm0
1120 ; AVX512VL-NEXT: retq
1121 ;
1122 ; X32-SSE-LABEL: splatconstant_shift_v2i64:
1123 ; X32-SSE: # %bb.0:
1124 ; X32-SSE-NEXT: psrlq $7, %xmm0
1125 ; X32-SSE-NEXT: retl
1126 %shift = lshr <2 x i64> %a, <i64 7, i64 7>
1127 ret <2 x i64> %shift
1128 }
1130 define <4 x i32> @splatconstant_shift_v4i32(<4 x i32> %a) nounwind {
1131 ; SSE-LABEL: splatconstant_shift_v4i32:
1132 ; SSE: # %bb.0:
1133 ; SSE-NEXT: psrld $5, %xmm0
1134 ; SSE-NEXT: retq
1135 ;
1136 ; AVX-LABEL: splatconstant_shift_v4i32:
1137 ; AVX: # %bb.0:
1138 ; AVX-NEXT: vpsrld $5, %xmm0, %xmm0
1139 ; AVX-NEXT: retq
1140 ;
1141 ; XOP-LABEL: splatconstant_shift_v4i32:
1142 ; XOP: # %bb.0:
1143 ; XOP-NEXT: vpsrld $5, %xmm0, %xmm0
1144 ; XOP-NEXT: retq
1145 ;
1146 ; AVX512-LABEL: splatconstant_shift_v4i32:
1147 ; AVX512: # %bb.0:
1148 ; AVX512-NEXT: vpsrld $5, %xmm0, %xmm0
1149 ; AVX512-NEXT: retq
1150 ;
1151 ; AVX512VL-LABEL: splatconstant_shift_v4i32:
1152 ; AVX512VL: # %bb.0:
1153 ; AVX512VL-NEXT: vpsrld $5, %xmm0, %xmm0
1154 ; AVX512VL-NEXT: retq
1155 ;
1156 ; X32-SSE-LABEL: splatconstant_shift_v4i32:
1157 ; X32-SSE: # %bb.0:
1158 ; X32-SSE-NEXT: psrld $5, %xmm0
1159 ; X32-SSE-NEXT: retl
1160 %shift = lshr <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
1161 ret <4 x i32> %shift
1162 }
1164 define <8 x i16> @splatconstant_shift_v8i16(<8 x i16> %a) nounwind {
1165 ; SSE-LABEL: splatconstant_shift_v8i16:
1166 ; SSE: # %bb.0:
1167 ; SSE-NEXT: psrlw $3, %xmm0
1168 ; SSE-NEXT: retq
1169 ;
1170 ; AVX-LABEL: splatconstant_shift_v8i16:
1171 ; AVX: # %bb.0:
1172 ; AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
1173 ; AVX-NEXT: retq
1174 ;
1175 ; XOP-LABEL: splatconstant_shift_v8i16:
1176 ; XOP: # %bb.0:
1177 ; XOP-NEXT: vpsrlw $3, %xmm0, %xmm0
1178 ; XOP-NEXT: retq
1179 ;
1180 ; AVX512-LABEL: splatconstant_shift_v8i16:
1181 ; AVX512: # %bb.0:
1182 ; AVX512-NEXT: vpsrlw $3, %xmm0, %xmm0
1183 ; AVX512-NEXT: retq
1184 ;
1185 ; AVX512VL-LABEL: splatconstant_shift_v8i16:
1186 ; AVX512VL: # %bb.0:
1187 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
1188 ; AVX512VL-NEXT: retq
1189 ;
1190 ; X32-SSE-LABEL: splatconstant_shift_v8i16:
1191 ; X32-SSE: # %bb.0:
1192 ; X32-SSE-NEXT: psrlw $3, %xmm0
1193 ; X32-SSE-NEXT: retl
1194 %shift = lshr <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
1195 ret <8 x i16> %shift
1196 }
1198 define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
1199 ; SSE-LABEL: splatconstant_shift_v16i8:
1200 ; SSE: # %bb.0:
1201 ; SSE-NEXT: psrlw $3, %xmm0
1202 ; SSE-NEXT: pand {{.*}}(%rip), %xmm0
1203 ; SSE-NEXT: retq
1204 ;
1205 ; AVX-LABEL: splatconstant_shift_v16i8:
1206 ; AVX: # %bb.0:
1207 ; AVX-NEXT: vpsrlw $3, %xmm0, %xmm0
1208 ; AVX-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
1209 ; AVX-NEXT: retq
1210 ;
1211 ; XOP-LABEL: splatconstant_shift_v16i8:
1212 ; XOP: # %bb.0:
1213 ; XOP-NEXT: vpshlb {{.*}}(%rip), %xmm0, %xmm0
1214 ; XOP-NEXT: retq
1215 ;
1216 ; AVX512-LABEL: splatconstant_shift_v16i8:
1217 ; AVX512: # %bb.0:
1218 ; AVX512-NEXT: vpsrlw $3, %xmm0, %xmm0
1219 ; AVX512-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
1220 ; AVX512-NEXT: retq
1221 ;
1222 ; AVX512VL-LABEL: splatconstant_shift_v16i8:
1223 ; AVX512VL: # %bb.0:
1224 ; AVX512VL-NEXT: vpsrlw $3, %xmm0, %xmm0
1225 ; AVX512VL-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0
1226 ; AVX512VL-NEXT: retq
1227 ;
1228 ; X32-SSE-LABEL: splatconstant_shift_v16i8:
1229 ; X32-SSE: # %bb.0:
1230 ; X32-SSE-NEXT: psrlw $3, %xmm0
1231 ; X32-SSE-NEXT: pand {{\.LCPI.*}}, %xmm0
1232 ; X32-SSE-NEXT: retl
1233 %shift = lshr <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
1234 ret <16 x i8> %shift
1235 }
1237 define <4 x i32> @vector_variable_shift_right(<4 x i1> %cond, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) nounwind {
1238 ; SSE2-LABEL: vector_variable_shift_right:
1239 ; SSE2: # %bb.0:
1240 ; SSE2-NEXT: xorps %xmm4, %xmm4
1241 ; SSE2-NEXT: xorps %xmm5, %xmm5
1242 ; SSE2-NEXT: movss {{.*#+}} xmm5 = xmm2[0],xmm5[1,2,3]
1243 ; SSE2-NEXT: movss {{.*#+}} xmm4 = xmm1[0],xmm4[1,2,3]
1244 ; SSE2-NEXT: pslld $31, %xmm0
1245 ; SSE2-NEXT: psrad $31, %xmm0
1246 ; SSE2-NEXT: movdqa %xmm3, %xmm1
1247 ; SSE2-NEXT: psrld %xmm4, %xmm1
1248 ; SSE2-NEXT: psrld %xmm5, %xmm3
1249 ; SSE2-NEXT: pand %xmm0, %xmm1
1250 ; SSE2-NEXT: pandn %xmm3, %xmm0
1251 ; SSE2-NEXT: por %xmm1, %xmm0
1252 ; SSE2-NEXT: retq
1253 ;
1254 ; SSE41-LABEL: vector_variable_shift_right:
1255 ; SSE41: # %bb.0:
1256 ; SSE41-NEXT: pslld $31, %xmm0
1257 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
1258 ; SSE41-NEXT: pmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
1259 ; SSE41-NEXT: movdqa %xmm3, %xmm4
1260 ; SSE41-NEXT: psrld %xmm1, %xmm4
1261 ; SSE41-NEXT: psrld %xmm2, %xmm3
1262 ; SSE41-NEXT: blendvps %xmm0, %xmm4, %xmm3
1263 ; SSE41-NEXT: movaps %xmm3, %xmm0
1264 ; SSE41-NEXT: retq
1265 ;
1266 ; AVX1-LABEL: vector_variable_shift_right:
1267 ; AVX1: # %bb.0:
1268 ; AVX1-NEXT: vpslld $31, %xmm0, %xmm0
1269 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm2 = xmm2[0],zero,xmm2[1],zero
1270 ; AVX1-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero
1271 ; AVX1-NEXT: vpsrld %xmm1, %xmm3, %xmm1
1272 ; AVX1-NEXT: vpsrld %xmm2, %xmm3, %xmm2
1273 ; AVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
1274 ; AVX1-NEXT: retq
1275 ;
1276 ; AVX2-LABEL: vector_variable_shift_right:
1277 ; AVX2: # %bb.0:
1278 ; AVX2-NEXT: vpslld $31, %xmm0, %xmm0
1279 ; AVX2-NEXT: vbroadcastss %xmm1, %xmm1
1280 ; AVX2-NEXT: vbroadcastss %xmm2, %xmm2
1281 ; AVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
1282 ; AVX2-NEXT: vpsrlvd %xmm0, %xmm3, %xmm0
1283 ; AVX2-NEXT: retq
1284 ;
1285 ; XOPAVX1-LABEL: vector_variable_shift_right:
1286 ; XOPAVX1: # %bb.0:
1287 ; XOPAVX1-NEXT: vpslld $31, %xmm0, %xmm0
1288 ; XOPAVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm1[0,0,0,0]
1289 ; XOPAVX1-NEXT: vpermilps {{.*#+}} xmm2 = xmm2[0,0,0,0]
1290 ; XOPAVX1-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
1291 ; XOPAVX1-NEXT: vxorps %xmm1, %xmm1, %xmm1
1292 ; XOPAVX1-NEXT: vpsubd %xmm0, %xmm1, %xmm0
1293 ; XOPAVX1-NEXT: vpshld %xmm0, %xmm3, %xmm0
1294 ; XOPAVX1-NEXT: retq
1295 ;
1296 ; XOPAVX2-LABEL: vector_variable_shift_right:
1297 ; XOPAVX2: # %bb.0:
1298 ; XOPAVX2-NEXT: vpslld $31, %xmm0, %xmm0
1299 ; XOPAVX2-NEXT: vbroadcastss %xmm1, %xmm1
1300 ; XOPAVX2-NEXT: vbroadcastss %xmm2, %xmm2
1301 ; XOPAVX2-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
1302 ; XOPAVX2-NEXT: vpsrlvd %xmm0, %xmm3, %xmm0
1303 ; XOPAVX2-NEXT: retq
1304 ;
1305 ; AVX512DQ-LABEL: vector_variable_shift_right:
1306 ; AVX512DQ: # %bb.0:
1307 ; AVX512DQ-NEXT: vpslld $31, %xmm0, %xmm0
1308 ; AVX512DQ-NEXT: vpmovd2m %zmm0, %k1
1309 ; AVX512DQ-NEXT: vpbroadcastd %xmm1, %xmm0
1310 ; AVX512DQ-NEXT: vpbroadcastd %xmm2, %xmm1
1311 ; AVX512DQ-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
1312 ; AVX512DQ-NEXT: vpsrlvd %xmm1, %xmm3, %xmm0
1313 ; AVX512DQ-NEXT: vzeroupper
1314 ; AVX512DQ-NEXT: retq
1315 ;
1316 ; AVX512BW-LABEL: vector_variable_shift_right:
1317 ; AVX512BW: # %bb.0:
1318 ; AVX512BW-NEXT: vpslld $31, %xmm0, %xmm0
1319 ; AVX512BW-NEXT: vptestmd %zmm0, %zmm0, %k1
1320 ; AVX512BW-NEXT: vpbroadcastd %xmm1, %xmm0
1321 ; AVX512BW-NEXT: vpbroadcastd %xmm2, %xmm1
1322 ; AVX512BW-NEXT: vmovdqa32 %zmm0, %zmm1 {%k1}
1323 ; AVX512BW-NEXT: vpsrlvd %xmm1, %xmm3, %xmm0
1324 ; AVX512BW-NEXT: vzeroupper
1325 ; AVX512BW-NEXT: retq
1326 ;
1327 ; AVX512DQVL-LABEL: vector_variable_shift_right:
1328 ; AVX512DQVL: # %bb.0:
1329 ; AVX512DQVL-NEXT: vpslld $31, %xmm0, %xmm0
1330 ; AVX512DQVL-NEXT: vpmovd2m %xmm0, %k1
1331 ; AVX512DQVL-NEXT: vpbroadcastd %xmm2, %xmm0
1332 ; AVX512DQVL-NEXT: vpbroadcastd %xmm1, %xmm0 {%k1}
1333 ; AVX512DQVL-NEXT: vpsrlvd %xmm0, %xmm3, %xmm0
1334 ; AVX512DQVL-NEXT: retq
1335 ;
1336 ; AVX512BWVL-LABEL: vector_variable_shift_right:
1337 ; AVX512BWVL: # %bb.0:
1338 ; AVX512BWVL-NEXT: vpslld $31, %xmm0, %xmm0
1339 ; AVX512BWVL-NEXT: vptestmd %xmm0, %xmm0, %k1
1340 ; AVX512BWVL-NEXT: vpbroadcastd %xmm2, %xmm0
1341 ; AVX512BWVL-NEXT: vpbroadcastd %xmm1, %xmm0 {%k1}
1342 ; AVX512BWVL-NEXT: vpsrlvd %xmm0, %xmm3, %xmm0
1343 ; AVX512BWVL-NEXT: retq
1344 ;
1345 ; X32-SSE-LABEL: vector_variable_shift_right:
1346 ; X32-SSE: # %bb.0:
1347 ; X32-SSE-NEXT: pushl %ebp
1348 ; X32-SSE-NEXT: movl %esp, %ebp
1349 ; X32-SSE-NEXT: andl $-16, %esp
1350 ; X32-SSE-NEXT: subl $16, %esp
1351 ; X32-SSE-NEXT: xorps %xmm3, %xmm3
1352 ; X32-SSE-NEXT: xorps %xmm4, %xmm4
1353 ; X32-SSE-NEXT: movss {{.*#+}} xmm4 = xmm2[0],xmm4[1,2,3]
1354 ; X32-SSE-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]
1355 ; X32-SSE-NEXT: pslld $31, %xmm0
1356 ; X32-SSE-NEXT: psrad $31, %xmm0
1357 ; X32-SSE-NEXT: movdqa 8(%ebp), %xmm1
1358 ; X32-SSE-NEXT: movdqa %xmm1, %xmm2
1359 ; X32-SSE-NEXT: psrld %xmm3, %xmm2
1360 ; X32-SSE-NEXT: psrld %xmm4, %xmm1
1361 ; X32-SSE-NEXT: pand %xmm0, %xmm2
1362 ; X32-SSE-NEXT: pandn %xmm1, %xmm0
1363 ; X32-SSE-NEXT: por %xmm2, %xmm0
1364 ; X32-SSE-NEXT: movl %ebp, %esp
1365 ; X32-SSE-NEXT: popl %ebp
1366 ; X32-SSE-NEXT: retl
1367 %splat1 = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> zeroinitializer
1368 %splat2 = shufflevector <4 x i32> %y, <4 x i32> undef, <4 x i32> zeroinitializer
1369 %sel = select <4 x i1> %cond, <4 x i32> %splat1, <4 x i32> %splat2
1370 %sh = lshr <4 x i32> %z, %sel
1371 ret <4 x i32> %sh
1372 }