lib/Target/Mips/MipsOptionRecord.h

   1 //===- MipsOptionRecord.h - Abstraction for storing information -*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // MipsOptionRecord - Abstraction for storing arbitrary information in
  11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
  12 // specific ELF sections like .Mips.options. Specific records should subclass
  13 // MipsOptionRecord and provide an implementation to EmitMipsOptionRecord which
  14 // basically just dumps the information into an ELF section. More information
  15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
  16 // specification.
  17 //
  18 //===----------------------------------------------------------------------===//
  19
  20 #ifndef LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
  21 #define LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H
  22
  23 #include "MCTargetDesc/MipsMCTargetDesc.h"
  24 #include "llvm/MC/MCContext.h"
  25 #include "llvm/MC/MCRegisterInfo.h"
  26 #include <cstdint>
  27
  28 namespace llvm {
  29
  30 class MipsELFStreamer;
  31
  32 class MipsOptionRecord {
  33 public:
  34   virtual ~MipsOptionRecord() = default;
  35
  36   virtual void EmitMipsOptionRecord() = 0;
  37 };
  38
  39 class MipsRegInfoRecord : public MipsOptionRecord {
  40 public:
  41   MipsRegInfoRecord(MipsELFStreamer *S, MCContext &Context)
  42       : Streamer(S), Context(Context) {
  43     ri_gprmask = 0;
  44     ri_cprmask[0] = ri_cprmask[1] = ri_cprmask[2] = ri_cprmask[3] = 0;
  45     ri_gp_value = 0;
  46
  47     const MCRegisterInfo *TRI = Context.getRegisterInfo();
  48     GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
  49     GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
  50     FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
  51     FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
  52     AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
  53     MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
  54     COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID));
  55     COP2RegClass = &(TRI->getRegClass(Mips::COP2RegClassID));
  56     COP3RegClass = &(TRI->getRegClass(Mips::COP3RegClassID));
  57   }
  58
  59   ~MipsRegInfoRecord() override = default;
  60
  61   void EmitMipsOptionRecord() override;
  62   void SetPhysRegUsed(unsigned Reg, const MCRegisterInfo *MCRegInfo);
  63
  64 private:
  65   MipsELFStreamer *Streamer;
  66   MCContext &Context;
  67   const MCRegisterClass *GPR32RegClass;
  68   const MCRegisterClass *GPR64RegClass;
  69   const MCRegisterClass *FGR32RegClass;
  70   const MCRegisterClass *FGR64RegClass;
  71   const MCRegisterClass *AFGR64RegClass;
  72   const MCRegisterClass *MSA128BRegClass;
  73   const MCRegisterClass *COP0RegClass;
  74   const MCRegisterClass *COP2RegClass;
  75   const MCRegisterClass *COP3RegClass;
  76   uint32_t ri_gprmask;
  77   uint32_t ri_cprmask[4];
  78   int64_t ri_gp_value;
  79 };
  80
  81 } // end namespace llvm
  82
  83 #endif // LLVM_LIB_TARGET_MIPS_MIPSOPTIONRECORD_H