lib/Target/Nios2/Nios2InstrInfo.cpp

   1 //===-- Nios2InstrInfo.cpp - Nios2 Instruction Information ----------------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Nios2 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "Nios2InstrInfo.h"
  15 #include "Nios2TargetMachine.h"
  16 #include "llvm/CodeGen/MachineInstrBuilder.h"
  17
  18 using namespace llvm;
  19
  20 #define GET_INSTRINFO_CTOR_DTOR
  21 #include "Nios2GenInstrInfo.inc"
  22
  23 // Pin the vtable to this file.
  24 void Nios2InstrInfo::anchor() {}
  25
  26 Nios2InstrInfo::Nios2InstrInfo(Nios2Subtarget &ST)
  27     : Nios2GenInstrInfo(), RI(ST), Subtarget(ST) {}
  28
  29 /// Expand Pseudo instructions into real backend instructions
  30 bool Nios2InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
  31   MachineBasicBlock &MBB = *MI.getParent();
  32
  33   switch (MI.getDesc().getOpcode()) {
  34   default:
  35     return false;
  36   case Nios2::RetRA:
  37     BuildMI(MBB, MI, MI.getDebugLoc(), get(Nios2::RET_R1)).addReg(Nios2::RA);
  38     break;
  39   }
  40
  41   MBB.erase(MI);
  42   return true;
  43 }
  44
  45 void Nios2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
  46                                  MachineBasicBlock::iterator I,
  47                                  const DebugLoc &DL, unsigned DestReg,
  48                                  unsigned SrcReg, bool KillSrc) const {
  49   unsigned opc = Subtarget.hasNios2r2() ? Nios2::ADD_R2 : Nios2::ADD_R1;
  50   BuildMI(MBB, I, DL, get(opc))
  51     .addReg(DestReg, RegState::Define)
  52     .addReg(Nios2::ZERO)
  53     .addReg(SrcReg, getKillRegState(KillSrc));
  54 }