[PowerPC] Fix CR Bit spill pseudo expansion
[llvm-core.git] / test / CodeGen / X86 / clzero-schedule.ll
blob692c261c6e24e72fa559b62889ac9a9cd5683280
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clzero | FileCheck %s --check-prefix=GENERIC
3 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=znver1 | FileCheck %s --check-prefix=ZNVER1
5 define void @test_clzero(i8* %p) {
6 ; GENERIC-LABEL: test_clzero:
7 ; GENERIC:       # %bb.0:
8 ; GENERIC-NEXT:    leaq (%rdi), %rax # sched: [1:0.50]
9 ; GENERIC-NEXT:    clzero # sched: [100:0.33]
10 ; GENERIC-NEXT:    retq # sched: [1:1.00]
12 ; ZNVER1-LABEL: test_clzero:
13 ; ZNVER1:       # %bb.0:
14 ; ZNVER1-NEXT:    leaq (%rdi), %rax # sched: [1:0.25]
15 ; ZNVER1-NEXT:    clzero # sched: [100:0.25]
16 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
17   tail call void @llvm.x86.clzero(i8* %p)
18   ret void
20 declare void @llvm.x86.clzero(i8*)