1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=x86_64-- -mattr=avx512vl | FileCheck %s
4 define <2 x i64> @undef_tval() {
5 ; CHECK-LABEL: undef_tval:
7 ; CHECK-NEXT: vmovaps {{.*#+}} xmm0 = [1,1,1,1,1,1,1,1]
9 %1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> undef, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3
10 %2 = bitcast <8 x i16> %1 to <2 x i64>
14 define <2 x i64> @foo(<8 x i64> %x) {
17 ; CHECK-NEXT: vmovdqa {{.*#+}} xmm1 = [1,1,1,1,1,1,1,1]
18 ; CHECK-NEXT: movb $1, %al
19 ; CHECK-NEXT: kmovw %eax, %k1
20 ; CHECK-NEXT: vpmovqw %zmm0, %xmm1 {%k1}
21 ; CHECK-NEXT: vmovdqa %xmm1, %xmm0
22 ; CHECK-NEXT: vzeroupper
24 %1 = tail call <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64> %x, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i8 1) #3
25 %2 = bitcast <8 x i16> %1 to <2 x i64>
29 define <4 x i64> @goo(<16 x i32> %x) {
32 ; CHECK-NEXT: vmovdqa {{.*#+}} ymm1 = [1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1]
33 ; CHECK-NEXT: movw $1, %ax
34 ; CHECK-NEXT: kmovw %eax, %k1
35 ; CHECK-NEXT: vpmovdw %zmm0, %ymm1 {%k1}
36 ; CHECK-NEXT: vmovdqa %ymm1, %ymm0
38 %1 = tail call <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32> %x, <16 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>, i16 1) #3
39 %2 = bitcast <16 x i16> %1 to <4 x i64>
44 declare <8 x i16> @llvm.x86.avx512.mask.pmov.qw.512(<8 x i64>, <8 x i16>, i8)
45 declare <16 x i16> @llvm.x86.avx512.mask.pmov.dw.512(<16 x i32>, <16 x i16>, i16)