| blob | f72d036288d045fb7a2309552efad1c6cfc8f232 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
3 ; RUN: llc < %s -mcpu=generic -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=CHECK32
5 declare i4 @llvm.uadd.sat.i4 (i4, i4)
6 declare i32 @llvm.uadd.sat.i32 (i32, i32)
7 declare i64 @llvm.uadd.sat.i64 (i64, i64)
8 declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>)
10 define i32 @func(i32 %x, i32 %y) {
11 ; CHECK-LABEL: func:
12 ; CHECK: # %bb.0:
13 ; CHECK-NEXT: addl %esi, %edi
14 ; CHECK-NEXT: movl $-1, %eax
15 ; CHECK-NEXT: cmovael %edi, %eax
16 ; CHECK-NEXT: retq
17 ;
18 ; CHECK32-LABEL: func:
19 ; CHECK32: # %bb.0:
20 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
21 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
22 ; CHECK32-NEXT: movl $-1, %eax
23 ; CHECK32-NEXT: cmovael %ecx, %eax
24 ; CHECK32-NEXT: retl
25 %tmp = call i32 @llvm.uadd.sat.i32(i32 %x, i32 %y);
26 ret i32 %tmp;
27 }
29 define i64 @func2(i64 %x, i64 %y) {
30 ; CHECK-LABEL: func2:
31 ; CHECK: # %bb.0:
32 ; CHECK-NEXT: addq %rsi, %rdi
33 ; CHECK-NEXT: movq $-1, %rax
34 ; CHECK-NEXT: cmovaeq %rdi, %rax
35 ; CHECK-NEXT: retq
36 ;
37 ; CHECK32-LABEL: func2:
38 ; CHECK32: # %bb.0:
39 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
40 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
41 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %eax
42 ; CHECK32-NEXT: adcl {{[0-9]+}}(%esp), %edx
43 ; CHECK32-NEXT: movl $-1, %ecx
44 ; CHECK32-NEXT: cmovbl %ecx, %edx
45 ; CHECK32-NEXT: cmovbl %ecx, %eax
46 ; CHECK32-NEXT: retl
47 %tmp = call i64 @llvm.uadd.sat.i64(i64 %x, i64 %y);
48 ret i64 %tmp;
49 }
51 define i4 @func3(i4 %x, i4 %y) {
52 ; CHECK-LABEL: func3:
53 ; CHECK: # %bb.0:
54 ; CHECK-NEXT: shlb $4, %sil
55 ; CHECK-NEXT: shlb $4, %dil
56 ; CHECK-NEXT: addb %sil, %dil
57 ; CHECK-NEXT: movb $-1, %al
58 ; CHECK-NEXT: jb .LBB2_2
59 ; CHECK-NEXT: # %bb.1:
60 ; CHECK-NEXT: movl %edi, %eax
61 ; CHECK-NEXT: .LBB2_2:
62 ; CHECK-NEXT: shrb $4, %al
63 ; CHECK-NEXT: retq
64 ;
65 ; CHECK32-LABEL: func3:
66 ; CHECK32: # %bb.0:
67 ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %cl
68 ; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
69 ; CHECK32-NEXT: shlb $4, %al
70 ; CHECK32-NEXT: shlb $4, %cl
71 ; CHECK32-NEXT: addb %al, %cl
72 ; CHECK32-NEXT: movb $-1, %al
73 ; CHECK32-NEXT: jb .LBB2_2
74 ; CHECK32-NEXT: # %bb.1:
75 ; CHECK32-NEXT: movl %ecx, %eax
76 ; CHECK32-NEXT: .LBB2_2:
77 ; CHECK32-NEXT: shrb $4, %al
78 ; CHECK32-NEXT: retl
79 %tmp = call i4 @llvm.uadd.sat.i4(i4 %x, i4 %y);
80 ret i4 %tmp;
81 }
83 define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) {
84 ; CHECK-LABEL: vec:
85 ; CHECK: # %bb.0:
86 ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[3,1,2,3]
87 ; CHECK-NEXT: movd %xmm2, %eax
88 ; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[3,1,2,3]
89 ; CHECK-NEXT: movd %xmm2, %ecx
90 ; CHECK-NEXT: addl %eax, %ecx
91 ; CHECK-NEXT: movl $-1, %eax
92 ; CHECK-NEXT: cmovbl %eax, %ecx
93 ; CHECK-NEXT: movd %ecx, %xmm2
94 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm1[2,3,0,1]
95 ; CHECK-NEXT: movd %xmm3, %ecx
96 ; CHECK-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,3,0,1]
97 ; CHECK-NEXT: movd %xmm3, %edx
98 ; CHECK-NEXT: addl %ecx, %edx
99 ; CHECK-NEXT: cmovbl %eax, %edx
100 ; CHECK-NEXT: movd %edx, %xmm3
101 ; CHECK-NEXT: punpckldq {{.*#+}} xmm3 = xmm3[0],xmm2[0],xmm3[1],xmm2[1]
102 ; CHECK-NEXT: movd %xmm1, %ecx
103 ; CHECK-NEXT: movd %xmm0, %edx
104 ; CHECK-NEXT: addl %ecx, %edx
105 ; CHECK-NEXT: cmovbl %eax, %edx
106 ; CHECK-NEXT: movd %edx, %xmm2
107 ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,2,3]
108 ; CHECK-NEXT: movd %xmm1, %ecx
109 ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,2,3]
110 ; CHECK-NEXT: movd %xmm0, %edx
111 ; CHECK-NEXT: addl %ecx, %edx
112 ; CHECK-NEXT: cmovbl %eax, %edx
113 ; CHECK-NEXT: movd %edx, %xmm0
114 ; CHECK-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1]
115 ; CHECK-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm3[0]
116 ; CHECK-NEXT: movdqa %xmm2, %xmm0
117 ; CHECK-NEXT: retq
118 ;
119 ; CHECK32-LABEL: vec:
120 ; CHECK32: # %bb.0:
121 ; CHECK32-NEXT: pushl %ebx
122 ; CHECK32-NEXT: .cfi_def_cfa_offset 8
123 ; CHECK32-NEXT: pushl %edi
124 ; CHECK32-NEXT: .cfi_def_cfa_offset 12
125 ; CHECK32-NEXT: pushl %esi
126 ; CHECK32-NEXT: .cfi_def_cfa_offset 16
127 ; CHECK32-NEXT: .cfi_offset %esi, -16
128 ; CHECK32-NEXT: .cfi_offset %edi, -12
129 ; CHECK32-NEXT: .cfi_offset %ebx, -8
130 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
131 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
132 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
133 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
134 ; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
135 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edi
136 ; CHECK32-NEXT: movl $-1, %ebx
137 ; CHECK32-NEXT: cmovbl %ebx, %edi
138 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %esi
139 ; CHECK32-NEXT: cmovbl %ebx, %esi
140 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edx
141 ; CHECK32-NEXT: cmovbl %ebx, %edx
142 ; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %ecx
143 ; CHECK32-NEXT: cmovbl %ebx, %ecx
144 ; CHECK32-NEXT: movl %ecx, 12(%eax)
145 ; CHECK32-NEXT: movl %edx, 8(%eax)
146 ; CHECK32-NEXT: movl %esi, 4(%eax)
147 ; CHECK32-NEXT: movl %edi, (%eax)
148 ; CHECK32-NEXT: popl %esi
149 ; CHECK32-NEXT: .cfi_def_cfa_offset 12
150 ; CHECK32-NEXT: popl %edi
151 ; CHECK32-NEXT: .cfi_def_cfa_offset 8
152 ; CHECK32-NEXT: popl %ebx
153 ; CHECK32-NEXT: .cfi_def_cfa_offset 4
154 ; CHECK32-NEXT: retl $4
155 %tmp = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
156 ret <4 x i32> %tmp;
157 }