| blob | 664793bba2776207e836fd5a2fb192d3177fdaba |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
4 declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
5 declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
6 declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
7 declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
8 declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>)
9 declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
10 declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>)
11 declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
13 declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
14 declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
15 declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
16 declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
17 declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>)
18 declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
19 declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>)
21 declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>)
22 declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>)
24 declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
25 declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
26 declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
27 declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
28 declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
29 declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
30 declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
32 declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
33 declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
36 define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
37 ; CHECK-LABEL: v16i8:
38 ; CHECK: // %bb.0:
39 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
40 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
41 ; CHECK-NEXT: movi v3.16b, #127
42 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
43 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
44 ; CHECK-NEXT: mvn v5.16b, v4.16b
45 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
46 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
47 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
48 ; CHECK-NEXT: ret
49 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
50 ret <16 x i8> %z
51 }
53 define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
54 ; CHECK-LABEL: v32i8:
55 ; CHECK: // %bb.0:
56 ; CHECK-NEXT: sub v4.16b, v0.16b, v2.16b
57 ; CHECK-NEXT: cmlt v7.16b, v4.16b, #0
58 ; CHECK-NEXT: movi v6.16b, #127
59 ; CHECK-NEXT: mvn v16.16b, v7.16b
60 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
61 ; CHECK-NEXT: sub v7.16b, v1.16b, v3.16b
62 ; CHECK-NEXT: cmgt v2.16b, v2.16b, #0
63 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v4.16b
64 ; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
65 ; CHECK-NEXT: movi v5.16b, #127
66 ; CHECK-NEXT: cmgt v3.16b, v3.16b, #0
67 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v7.16b
68 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
69 ; CHECK-NEXT: mvn v2.16b, v16.16b
70 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
71 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
72 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
73 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
74 ; CHECK-NEXT: ret
75 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
76 ret <32 x i8> %z
77 }
79 define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
80 ; CHECK-LABEL: v64i8:
81 ; CHECK: // %bb.0:
82 ; CHECK-NEXT: sub v16.16b, v0.16b, v4.16b
83 ; CHECK-NEXT: cmlt v24.16b, v16.16b, #0
84 ; CHECK-NEXT: movi v18.16b, #127
85 ; CHECK-NEXT: sub v19.16b, v1.16b, v5.16b
86 ; CHECK-NEXT: mvn v25.16b, v24.16b
87 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
88 ; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
89 ; CHECK-NEXT: movi v20.16b, #127
90 ; CHECK-NEXT: sub v21.16b, v2.16b, v6.16b
91 ; CHECK-NEXT: mvn v25.16b, v24.16b
92 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
93 ; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
94 ; CHECK-NEXT: cmgt v4.16b, v4.16b, #0
95 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v16.16b
96 ; CHECK-NEXT: movi v22.16b, #127
97 ; CHECK-NEXT: sub v23.16b, v3.16b, v7.16b
98 ; CHECK-NEXT: mvn v25.16b, v24.16b
99 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
100 ; CHECK-NEXT: cmgt v4.16b, v5.16b, #0
101 ; CHECK-NEXT: cmgt v1.16b, v1.16b, v19.16b
102 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
103 ; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
104 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
105 ; CHECK-NEXT: cmgt v4.16b, v6.16b, #0
106 ; CHECK-NEXT: cmgt v2.16b, v2.16b, v21.16b
107 ; CHECK-NEXT: movi v17.16b, #127
108 ; CHECK-NEXT: mvn v25.16b, v24.16b
109 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
110 ; CHECK-NEXT: cmgt v4.16b, v7.16b, #0
111 ; CHECK-NEXT: cmgt v3.16b, v3.16b, v23.16b
112 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
113 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
114 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
115 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
116 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
117 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
118 ; CHECK-NEXT: ret
119 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
120 ret <64 x i8> %z
121 }
123 define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
124 ; CHECK-LABEL: v8i16:
125 ; CHECK: // %bb.0:
126 ; CHECK-NEXT: sub v2.8h, v0.8h, v1.8h
127 ; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
128 ; CHECK-NEXT: mvni v3.8h, #128, lsl #8
129 ; CHECK-NEXT: cmgt v1.8h, v1.8h, #0
130 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h
131 ; CHECK-NEXT: mvn v5.16b, v4.16b
132 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
133 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
134 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
135 ; CHECK-NEXT: ret
136 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
137 ret <8 x i16> %z
138 }
140 define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
141 ; CHECK-LABEL: v16i16:
142 ; CHECK: // %bb.0:
143 ; CHECK-NEXT: sub v4.8h, v0.8h, v2.8h
144 ; CHECK-NEXT: cmlt v7.8h, v4.8h, #0
145 ; CHECK-NEXT: mvni v6.8h, #128, lsl #8
146 ; CHECK-NEXT: mvn v16.16b, v7.16b
147 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
148 ; CHECK-NEXT: sub v7.8h, v1.8h, v3.8h
149 ; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
150 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v4.8h
151 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
152 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
153 ; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
154 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v7.8h
155 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
156 ; CHECK-NEXT: mvn v2.16b, v16.16b
157 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
158 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
159 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
160 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
161 ; CHECK-NEXT: ret
162 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
163 ret <16 x i16> %z
164 }
166 define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
167 ; CHECK-LABEL: v32i16:
168 ; CHECK: // %bb.0:
169 ; CHECK-NEXT: sub v16.8h, v0.8h, v4.8h
170 ; CHECK-NEXT: cmlt v24.8h, v16.8h, #0
171 ; CHECK-NEXT: mvni v18.8h, #128, lsl #8
172 ; CHECK-NEXT: sub v19.8h, v1.8h, v5.8h
173 ; CHECK-NEXT: mvn v25.16b, v24.16b
174 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
175 ; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
176 ; CHECK-NEXT: mvni v20.8h, #128, lsl #8
177 ; CHECK-NEXT: sub v21.8h, v2.8h, v6.8h
178 ; CHECK-NEXT: mvn v25.16b, v24.16b
179 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
180 ; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
181 ; CHECK-NEXT: cmgt v4.8h, v4.8h, #0
182 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v16.8h
183 ; CHECK-NEXT: mvni v22.8h, #128, lsl #8
184 ; CHECK-NEXT: sub v23.8h, v3.8h, v7.8h
185 ; CHECK-NEXT: mvn v25.16b, v24.16b
186 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
187 ; CHECK-NEXT: cmgt v4.8h, v5.8h, #0
188 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v19.8h
189 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
190 ; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
191 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
192 ; CHECK-NEXT: cmgt v4.8h, v6.8h, #0
193 ; CHECK-NEXT: cmgt v2.8h, v2.8h, v21.8h
194 ; CHECK-NEXT: mvni v17.8h, #128, lsl #8
195 ; CHECK-NEXT: mvn v25.16b, v24.16b
196 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
197 ; CHECK-NEXT: cmgt v4.8h, v7.8h, #0
198 ; CHECK-NEXT: cmgt v3.8h, v3.8h, v23.8h
199 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
200 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
201 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
202 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
203 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
204 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
205 ; CHECK-NEXT: ret
206 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
207 ret <32 x i16> %z
208 }
210 define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
211 ; CHECK-LABEL: v8i8:
212 ; CHECK: // %bb.0:
213 ; CHECK-NEXT: ldr d0, [x0]
214 ; CHECK-NEXT: ldr d1, [x1]
215 ; CHECK-NEXT: movi v2.8b, #127
216 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
217 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
218 ; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
219 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
220 ; CHECK-NEXT: mvn v5.8b, v4.8b
221 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
222 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
223 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
224 ; CHECK-NEXT: str d0, [x2]
225 ; CHECK-NEXT: ret
226 %x = load <8 x i8>, <8 x i8>* %px
227 %y = load <8 x i8>, <8 x i8>* %py
228 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
229 store <8 x i8> %z, <8 x i8>* %pz
230 ret void
231 }
233 define void @v4i8(<4 x i8>* %px, <4 x i8>* %py, <4 x i8>* %pz) nounwind {
234 ; CHECK-LABEL: v4i8:
235 ; CHECK: // %bb.0:
236 ; CHECK-NEXT: ldrb w8, [x0]
237 ; CHECK-NEXT: ldrb w9, [x1]
238 ; CHECK-NEXT: ldrb w10, [x0, #1]
239 ; CHECK-NEXT: ldrb w11, [x1, #1]
240 ; CHECK-NEXT: ldrb w12, [x0, #2]
241 ; CHECK-NEXT: fmov s0, w8
242 ; CHECK-NEXT: ldrb w8, [x1, #2]
243 ; CHECK-NEXT: fmov s1, w9
244 ; CHECK-NEXT: mov v0.h[1], w10
245 ; CHECK-NEXT: ldrb w9, [x0, #3]
246 ; CHECK-NEXT: ldrb w10, [x1, #3]
247 ; CHECK-NEXT: mov v1.h[1], w11
248 ; CHECK-NEXT: mov v0.h[2], w12
249 ; CHECK-NEXT: mov v1.h[2], w8
250 ; CHECK-NEXT: mov v0.h[3], w9
251 ; CHECK-NEXT: mov v1.h[3], w10
252 ; CHECK-NEXT: shl v1.4h, v1.4h, #8
253 ; CHECK-NEXT: shl v0.4h, v0.4h, #8
254 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
255 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
256 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
257 ; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
258 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
259 ; CHECK-NEXT: mvn v5.8b, v4.8b
260 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
261 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
262 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
263 ; CHECK-NEXT: sshr v0.4h, v0.4h, #8
264 ; CHECK-NEXT: xtn v0.8b, v0.8h
265 ; CHECK-NEXT: str s0, [x2]
266 ; CHECK-NEXT: ret
267 %x = load <4 x i8>, <4 x i8>* %px
268 %y = load <4 x i8>, <4 x i8>* %py
269 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
270 store <4 x i8> %z, <4 x i8>* %pz
271 ret void
272 }
274 define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
275 ; CHECK-LABEL: v2i8:
276 ; CHECK: // %bb.0:
277 ; CHECK-NEXT: ldrb w8, [x0]
278 ; CHECK-NEXT: ldrb w9, [x1]
279 ; CHECK-NEXT: ldrb w10, [x0, #1]
280 ; CHECK-NEXT: ldrb w11, [x1, #1]
281 ; CHECK-NEXT: fmov s0, w8
282 ; CHECK-NEXT: fmov s2, w9
283 ; CHECK-NEXT: mov v0.s[1], w10
284 ; CHECK-NEXT: mov v2.s[1], w11
285 ; CHECK-NEXT: shl v2.2s, v2.2s, #24
286 ; CHECK-NEXT: shl v0.2s, v0.2s, #24
287 ; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
288 ; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
289 ; CHECK-NEXT: mvni v1.2s, #128, lsl #24
290 ; CHECK-NEXT: cmgt v2.2s, v2.2s, #0
291 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
292 ; CHECK-NEXT: mvn v5.8b, v4.8b
293 ; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
294 ; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
295 ; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
296 ; CHECK-NEXT: ushr v0.2s, v0.2s, #24
297 ; CHECK-NEXT: mov w8, v0.s[1]
298 ; CHECK-NEXT: fmov w9, s0
299 ; CHECK-NEXT: strb w8, [x2, #1]
300 ; CHECK-NEXT: strb w9, [x2]
301 ; CHECK-NEXT: ret
302 %x = load <2 x i8>, <2 x i8>* %px
303 %y = load <2 x i8>, <2 x i8>* %py
304 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
305 store <2 x i8> %z, <2 x i8>* %pz
306 ret void
307 }
309 define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
310 ; CHECK-LABEL: v4i16:
311 ; CHECK: // %bb.0:
312 ; CHECK-NEXT: ldr d0, [x0]
313 ; CHECK-NEXT: ldr d1, [x1]
314 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
315 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
316 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
317 ; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
318 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
319 ; CHECK-NEXT: mvn v5.8b, v4.8b
320 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
321 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
322 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
323 ; CHECK-NEXT: str d0, [x2]
324 ; CHECK-NEXT: ret
325 %x = load <4 x i16>, <4 x i16>* %px
326 %y = load <4 x i16>, <4 x i16>* %py
327 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
328 store <4 x i16> %z, <4 x i16>* %pz
329 ret void
330 }
332 define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
333 ; CHECK-LABEL: v2i16:
334 ; CHECK: // %bb.0:
335 ; CHECK-NEXT: ldrh w8, [x0]
336 ; CHECK-NEXT: ldrh w9, [x1]
337 ; CHECK-NEXT: ldrh w10, [x0, #2]
338 ; CHECK-NEXT: ldrh w11, [x1, #2]
339 ; CHECK-NEXT: fmov s0, w8
340 ; CHECK-NEXT: fmov s2, w9
341 ; CHECK-NEXT: mov v0.s[1], w10
342 ; CHECK-NEXT: mov v2.s[1], w11
343 ; CHECK-NEXT: shl v2.2s, v2.2s, #16
344 ; CHECK-NEXT: shl v0.2s, v0.2s, #16
345 ; CHECK-NEXT: sub v3.2s, v0.2s, v2.2s
346 ; CHECK-NEXT: cmlt v4.2s, v3.2s, #0
347 ; CHECK-NEXT: mvni v1.2s, #128, lsl #24
348 ; CHECK-NEXT: cmgt v2.2s, v2.2s, #0
349 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v3.2s
350 ; CHECK-NEXT: mvn v5.8b, v4.8b
351 ; CHECK-NEXT: eor v0.8b, v2.8b, v0.8b
352 ; CHECK-NEXT: bsl v1.8b, v4.8b, v5.8b
353 ; CHECK-NEXT: bsl v0.8b, v1.8b, v3.8b
354 ; CHECK-NEXT: ushr v0.2s, v0.2s, #16
355 ; CHECK-NEXT: mov w8, v0.s[1]
356 ; CHECK-NEXT: fmov w9, s0
357 ; CHECK-NEXT: strh w8, [x2, #2]
358 ; CHECK-NEXT: strh w9, [x2]
359 ; CHECK-NEXT: ret
360 %x = load <2 x i16>, <2 x i16>* %px
361 %y = load <2 x i16>, <2 x i16>* %py
362 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
363 store <2 x i16> %z, <2 x i16>* %pz
364 ret void
365 }
367 define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
368 ; CHECK-LABEL: v12i8:
369 ; CHECK: // %bb.0:
370 ; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b
371 ; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
372 ; CHECK-NEXT: movi v3.16b, #127
373 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
374 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
375 ; CHECK-NEXT: mvn v5.16b, v4.16b
376 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
377 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
378 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
379 ; CHECK-NEXT: ret
380 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
381 ret <12 x i8> %z
382 }
384 define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
385 ; CHECK-LABEL: v12i16:
386 ; CHECK: // %bb.0:
387 ; CHECK-NEXT: ldp q0, q1, [x0]
388 ; CHECK-NEXT: ldp q3, q2, [x1]
389 ; CHECK-NEXT: mvni v5.8h, #128, lsl #8
390 ; CHECK-NEXT: mvni v4.8h, #128, lsl #8
391 ; CHECK-NEXT: sub v6.8h, v1.8h, v2.8h
392 ; CHECK-NEXT: cmlt v7.8h, v6.8h, #0
393 ; CHECK-NEXT: mvn v16.16b, v7.16b
394 ; CHECK-NEXT: bsl v5.16b, v7.16b, v16.16b
395 ; CHECK-NEXT: sub v7.8h, v0.8h, v3.8h
396 ; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
397 ; CHECK-NEXT: cmgt v1.8h, v1.8h, v6.8h
398 ; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
399 ; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
400 ; CHECK-NEXT: cmgt v0.8h, v0.8h, v7.8h
401 ; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
402 ; CHECK-NEXT: mvn v2.16b, v16.16b
403 ; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
404 ; CHECK-NEXT: bsl v4.16b, v16.16b, v2.16b
405 ; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
406 ; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
407 ; CHECK-NEXT: str q0, [x2]
408 ; CHECK-NEXT: str d1, [x2, #16]
409 ; CHECK-NEXT: ret
410 %x = load <12 x i16>, <12 x i16>* %px
411 %y = load <12 x i16>, <12 x i16>* %py
412 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
413 store <12 x i16> %z, <12 x i16>* %pz
414 ret void
415 }
417 define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
418 ; CHECK-LABEL: v1i8:
419 ; CHECK: // %bb.0:
420 ; CHECK-NEXT: ldr b0, [x0]
421 ; CHECK-NEXT: ldr b1, [x1]
422 ; CHECK-NEXT: movi v2.8b, #127
423 ; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
424 ; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
425 ; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
426 ; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
427 ; CHECK-NEXT: mvn v5.8b, v4.8b
428 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
429 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
430 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
431 ; CHECK-NEXT: st1 { v0.b }[0], [x2]
432 ; CHECK-NEXT: ret
433 %x = load <1 x i8>, <1 x i8>* %px
434 %y = load <1 x i8>, <1 x i8>* %py
435 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
436 store <1 x i8> %z, <1 x i8>* %pz
437 ret void
438 }
440 define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
441 ; CHECK-LABEL: v1i16:
442 ; CHECK: // %bb.0:
443 ; CHECK-NEXT: ldr h0, [x0]
444 ; CHECK-NEXT: ldr h1, [x1]
445 ; CHECK-NEXT: mvni v2.4h, #128, lsl #8
446 ; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
447 ; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
448 ; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
449 ; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
450 ; CHECK-NEXT: mvn v5.8b, v4.8b
451 ; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
452 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
453 ; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
454 ; CHECK-NEXT: str h0, [x2]
455 ; CHECK-NEXT: ret
456 %x = load <1 x i16>, <1 x i16>* %px
457 %y = load <1 x i16>, <1 x i16>* %py
458 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
459 store <1 x i16> %z, <1 x i16>* %pz
460 ret void
461 }
463 define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
464 ; CHECK-LABEL: v16i4:
465 ; CHECK: // %bb.0:
466 ; CHECK-NEXT: shl v1.16b, v1.16b, #4
467 ; CHECK-NEXT: shl v0.16b, v0.16b, #4
468 ; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
469 ; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
470 ; CHECK-NEXT: movi v2.16b, #127
471 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
472 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
473 ; CHECK-NEXT: mvn v5.16b, v4.16b
474 ; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
475 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
476 ; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
477 ; CHECK-NEXT: sshr v0.16b, v0.16b, #4
478 ; CHECK-NEXT: ret
479 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
480 ret <16 x i4> %z
481 }
483 define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
484 ; CHECK-LABEL: v16i1:
485 ; CHECK: // %bb.0:
486 ; CHECK-NEXT: shl v1.16b, v1.16b, #7
487 ; CHECK-NEXT: shl v0.16b, v0.16b, #7
488 ; CHECK-NEXT: sub v3.16b, v0.16b, v1.16b
489 ; CHECK-NEXT: cmlt v4.16b, v3.16b, #0
490 ; CHECK-NEXT: movi v2.16b, #127
491 ; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
492 ; CHECK-NEXT: cmgt v0.16b, v0.16b, v3.16b
493 ; CHECK-NEXT: mvn v5.16b, v4.16b
494 ; CHECK-NEXT: bsl v2.16b, v4.16b, v5.16b
495 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
496 ; CHECK-NEXT: bsl v0.16b, v2.16b, v3.16b
497 ; CHECK-NEXT: sshr v0.16b, v0.16b, #7
498 ; CHECK-NEXT: ret
499 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
500 ret <16 x i1> %z
501 }
503 define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
504 ; CHECK-LABEL: v2i32:
505 ; CHECK: // %bb.0:
506 ; CHECK-NEXT: sub v2.2s, v0.2s, v1.2s
507 ; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
508 ; CHECK-NEXT: mvni v3.2s, #128, lsl #24
509 ; CHECK-NEXT: cmgt v1.2s, v1.2s, #0
510 ; CHECK-NEXT: cmgt v0.2s, v0.2s, v2.2s
511 ; CHECK-NEXT: mvn v5.8b, v4.8b
512 ; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
513 ; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
514 ; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
515 ; CHECK-NEXT: ret
516 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
517 ret <2 x i32> %z
518 }
520 define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
521 ; CHECK-LABEL: v4i32:
522 ; CHECK: // %bb.0:
523 ; CHECK-NEXT: sub v2.4s, v0.4s, v1.4s
524 ; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
525 ; CHECK-NEXT: mvni v3.4s, #128, lsl #24
526 ; CHECK-NEXT: cmgt v1.4s, v1.4s, #0
527 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
528 ; CHECK-NEXT: mvn v5.16b, v4.16b
529 ; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
530 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
531 ; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
532 ; CHECK-NEXT: ret
533 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
534 ret <4 x i32> %z
535 }
537 define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
538 ; CHECK-LABEL: v8i32:
539 ; CHECK: // %bb.0:
540 ; CHECK-NEXT: sub v4.4s, v0.4s, v2.4s
541 ; CHECK-NEXT: cmlt v7.4s, v4.4s, #0
542 ; CHECK-NEXT: mvni v6.4s, #128, lsl #24
543 ; CHECK-NEXT: mvn v16.16b, v7.16b
544 ; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
545 ; CHECK-NEXT: sub v7.4s, v1.4s, v3.4s
546 ; CHECK-NEXT: cmgt v2.4s, v2.4s, #0
547 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v4.4s
548 ; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
549 ; CHECK-NEXT: mvni v5.4s, #128, lsl #24
550 ; CHECK-NEXT: cmgt v3.4s, v3.4s, #0
551 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v7.4s
552 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
553 ; CHECK-NEXT: mvn v2.16b, v16.16b
554 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
555 ; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
556 ; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
557 ; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
558 ; CHECK-NEXT: ret
559 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
560 ret <8 x i32> %z
561 }
563 define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
564 ; CHECK-LABEL: v16i32:
565 ; CHECK: // %bb.0:
566 ; CHECK-NEXT: sub v16.4s, v0.4s, v4.4s
567 ; CHECK-NEXT: cmlt v24.4s, v16.4s, #0
568 ; CHECK-NEXT: mvni v18.4s, #128, lsl #24
569 ; CHECK-NEXT: sub v19.4s, v1.4s, v5.4s
570 ; CHECK-NEXT: mvn v25.16b, v24.16b
571 ; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
572 ; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
573 ; CHECK-NEXT: mvni v20.4s, #128, lsl #24
574 ; CHECK-NEXT: sub v21.4s, v2.4s, v6.4s
575 ; CHECK-NEXT: mvn v25.16b, v24.16b
576 ; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
577 ; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
578 ; CHECK-NEXT: cmgt v4.4s, v4.4s, #0
579 ; CHECK-NEXT: cmgt v0.4s, v0.4s, v16.4s
580 ; CHECK-NEXT: mvni v22.4s, #128, lsl #24
581 ; CHECK-NEXT: sub v23.4s, v3.4s, v7.4s
582 ; CHECK-NEXT: mvn v25.16b, v24.16b
583 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
584 ; CHECK-NEXT: cmgt v4.4s, v5.4s, #0
585 ; CHECK-NEXT: cmgt v1.4s, v1.4s, v19.4s
586 ; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
587 ; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
588 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
589 ; CHECK-NEXT: cmgt v4.4s, v6.4s, #0
590 ; CHECK-NEXT: cmgt v2.4s, v2.4s, v21.4s
591 ; CHECK-NEXT: mvni v17.4s, #128, lsl #24
592 ; CHECK-NEXT: mvn v25.16b, v24.16b
593 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
594 ; CHECK-NEXT: cmgt v4.4s, v7.4s, #0
595 ; CHECK-NEXT: cmgt v3.4s, v3.4s, v23.4s
596 ; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
597 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
598 ; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
599 ; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
600 ; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
601 ; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
602 ; CHECK-NEXT: ret
603 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
604 ret <16 x i32> %z
605 }
607 define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
608 ; CHECK-LABEL: v2i64:
609 ; CHECK: // %bb.0:
610 ; CHECK-NEXT: sub v2.2d, v0.2d, v1.2d
611 ; CHECK-NEXT: mov x8, #9223372036854775807
612 ; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
613 ; CHECK-NEXT: cmgt v1.2d, v1.2d, #0
614 ; CHECK-NEXT: dup v4.2d, x8
615 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v2.2d
616 ; CHECK-NEXT: mvn v5.16b, v3.16b
617 ; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
618 ; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
619 ; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
620 ; CHECK-NEXT: ret
621 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
622 ret <2 x i64> %z
623 }
625 define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
626 ; CHECK-LABEL: v4i64:
627 ; CHECK: // %bb.0:
628 ; CHECK-NEXT: sub v4.2d, v0.2d, v2.2d
629 ; CHECK-NEXT: mov x8, #9223372036854775807
630 ; CHECK-NEXT: cmlt v5.2d, v4.2d, #0
631 ; CHECK-NEXT: dup v6.2d, x8
632 ; CHECK-NEXT: mvn v7.16b, v5.16b
633 ; CHECK-NEXT: mov v16.16b, v6.16b
634 ; CHECK-NEXT: bsl v16.16b, v5.16b, v7.16b
635 ; CHECK-NEXT: sub v5.2d, v1.2d, v3.2d
636 ; CHECK-NEXT: cmgt v2.2d, v2.2d, #0
637 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v4.2d
638 ; CHECK-NEXT: cmlt v7.2d, v5.2d, #0
639 ; CHECK-NEXT: cmgt v3.2d, v3.2d, #0
640 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v5.2d
641 ; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
642 ; CHECK-NEXT: mvn v2.16b, v7.16b
643 ; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
644 ; CHECK-NEXT: bsl v6.16b, v7.16b, v2.16b
645 ; CHECK-NEXT: bsl v0.16b, v16.16b, v4.16b
646 ; CHECK-NEXT: bsl v1.16b, v6.16b, v5.16b
647 ; CHECK-NEXT: ret
648 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
649 ret <4 x i64> %z
650 }
652 define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
653 ; CHECK-LABEL: v8i64:
654 ; CHECK: // %bb.0:
655 ; CHECK-NEXT: sub v16.2d, v0.2d, v4.2d
656 ; CHECK-NEXT: mov x8, #9223372036854775807
657 ; CHECK-NEXT: sub v17.2d, v1.2d, v5.2d
658 ; CHECK-NEXT: cmlt v20.2d, v16.2d, #0
659 ; CHECK-NEXT: dup v21.2d, x8
660 ; CHECK-NEXT: sub v18.2d, v2.2d, v6.2d
661 ; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
662 ; CHECK-NEXT: mvn v24.16b, v20.16b
663 ; CHECK-NEXT: mov v25.16b, v21.16b
664 ; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
665 ; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
666 ; CHECK-NEXT: mvn v20.16b, v22.16b
667 ; CHECK-NEXT: mov v24.16b, v21.16b
668 ; CHECK-NEXT: cmgt v4.2d, v4.2d, #0
669 ; CHECK-NEXT: cmgt v0.2d, v0.2d, v16.2d
670 ; CHECK-NEXT: sub v19.2d, v3.2d, v7.2d
671 ; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
672 ; CHECK-NEXT: mvn v20.16b, v23.16b
673 ; CHECK-NEXT: mov v22.16b, v21.16b
674 ; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
675 ; CHECK-NEXT: cmgt v4.2d, v5.2d, #0
676 ; CHECK-NEXT: cmgt v1.2d, v1.2d, v17.2d
677 ; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
678 ; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
679 ; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
680 ; CHECK-NEXT: cmgt v4.2d, v6.2d, #0
681 ; CHECK-NEXT: cmgt v2.2d, v2.2d, v18.2d
682 ; CHECK-NEXT: mvn v23.16b, v20.16b
683 ; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
684 ; CHECK-NEXT: cmgt v4.2d, v7.2d, #0
685 ; CHECK-NEXT: cmgt v3.2d, v3.2d, v19.2d
686 ; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
687 ; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
688 ; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
689 ; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
690 ; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
691 ; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
692 ; CHECK-NEXT: ret
693 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
694 ret <8 x i64> %z
695 }
697 define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
698 ; CHECK-LABEL: v2i128:
699 ; CHECK: // %bb.0:
700 ; CHECK-NEXT: cmp x7, #0 // =0
701 ; CHECK-NEXT: cset w9, ge
702 ; CHECK-NEXT: csinc w9, w9, wzr, ne
703 ; CHECK-NEXT: cmp x3, #0 // =0
704 ; CHECK-NEXT: cset w10, ge
705 ; CHECK-NEXT: csinc w10, w10, wzr, ne
706 ; CHECK-NEXT: cmp w10, w9
707 ; CHECK-NEXT: cset w9, ne
708 ; CHECK-NEXT: subs x11, x2, x6
709 ; CHECK-NEXT: sbcs x12, x3, x7
710 ; CHECK-NEXT: cmp x12, #0 // =0
711 ; CHECK-NEXT: cset w13, ge
712 ; CHECK-NEXT: mov x8, #9223372036854775807
713 ; CHECK-NEXT: csinc w13, w13, wzr, ne
714 ; CHECK-NEXT: cinv x14, x8, ge
715 ; CHECK-NEXT: cmp w10, w13
716 ; CHECK-NEXT: cset w13, ne
717 ; CHECK-NEXT: asr x10, x12, #63
718 ; CHECK-NEXT: tst w9, w13
719 ; CHECK-NEXT: csel x3, x14, x12, ne
720 ; CHECK-NEXT: csel x2, x10, x11, ne
721 ; CHECK-NEXT: cmp x5, #0 // =0
722 ; CHECK-NEXT: cset w9, ge
723 ; CHECK-NEXT: csinc w9, w9, wzr, ne
724 ; CHECK-NEXT: cmp x1, #0 // =0
725 ; CHECK-NEXT: cset w10, ge
726 ; CHECK-NEXT: csinc w10, w10, wzr, ne
727 ; CHECK-NEXT: cmp w10, w9
728 ; CHECK-NEXT: cset w9, ne
729 ; CHECK-NEXT: subs x11, x0, x4
730 ; CHECK-NEXT: sbcs x12, x1, x5
731 ; CHECK-NEXT: cmp x12, #0 // =0
732 ; CHECK-NEXT: cset w13, ge
733 ; CHECK-NEXT: csinc w13, w13, wzr, ne
734 ; CHECK-NEXT: cinv x8, x8, ge
735 ; CHECK-NEXT: cmp w10, w13
736 ; CHECK-NEXT: cset w10, ne
737 ; CHECK-NEXT: tst w9, w10
738 ; CHECK-NEXT: asr x9, x12, #63
739 ; CHECK-NEXT: csel x9, x9, x11, ne
740 ; CHECK-NEXT: csel x1, x8, x12, ne
741 ; CHECK-NEXT: fmov d0, x9
742 ; CHECK-NEXT: mov v0.d[1], x1
743 ; CHECK-NEXT: fmov x0, d0
744 ; CHECK-NEXT: ret
745 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)
746 ret <2 x i128> %z
747 }