1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @vcmp_eqz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
5 ; CHECK-LABEL: vcmp_eqz_v4i32:
6 ; CHECK: @ %bb.0: @ %entry
7 ; CHECK-NEXT: vcmp.i32 eq, q0, zr
8 ; CHECK-NEXT: vpsel q0, q1, q2
11 %c = icmp eq <4 x i32> %src, zeroinitializer
12 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
16 define arm_aapcs_vfpcc <4 x i32> @vcmp_nez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
17 ; CHECK-LABEL: vcmp_nez_v4i32:
18 ; CHECK: @ %bb.0: @ %entry
19 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
20 ; CHECK-NEXT: vpsel q0, q1, q2
23 %c = icmp ne <4 x i32> %src, zeroinitializer
24 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
28 define arm_aapcs_vfpcc <4 x i32> @vcmp_sgtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
29 ; CHECK-LABEL: vcmp_sgtz_v4i32:
30 ; CHECK: @ %bb.0: @ %entry
31 ; CHECK-NEXT: vcmp.s32 gt, q0, zr
32 ; CHECK-NEXT: vpsel q0, q1, q2
35 %c = icmp sgt <4 x i32> %src, zeroinitializer
36 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
40 define arm_aapcs_vfpcc <4 x i32> @vcmp_sgez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
41 ; CHECK-LABEL: vcmp_sgez_v4i32:
42 ; CHECK: @ %bb.0: @ %entry
43 ; CHECK-NEXT: vcmp.s32 ge, q0, zr
44 ; CHECK-NEXT: vpsel q0, q1, q2
47 %c = icmp sge <4 x i32> %src, zeroinitializer
48 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
52 define arm_aapcs_vfpcc <4 x i32> @vcmp_sltz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
53 ; CHECK-LABEL: vcmp_sltz_v4i32:
54 ; CHECK: @ %bb.0: @ %entry
55 ; CHECK-NEXT: vcmp.s32 lt, q0, zr
56 ; CHECK-NEXT: vpsel q0, q1, q2
59 %c = icmp slt <4 x i32> %src, zeroinitializer
60 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
64 define arm_aapcs_vfpcc <4 x i32> @vcmp_slez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
65 ; CHECK-LABEL: vcmp_slez_v4i32:
66 ; CHECK: @ %bb.0: @ %entry
67 ; CHECK-NEXT: vcmp.s32 le, q0, zr
68 ; CHECK-NEXT: vpsel q0, q1, q2
71 %c = icmp sle <4 x i32> %src, zeroinitializer
72 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
76 define arm_aapcs_vfpcc <4 x i32> @vcmp_ugtz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
77 ; CHECK-LABEL: vcmp_ugtz_v4i32:
78 ; CHECK: @ %bb.0: @ %entry
79 ; CHECK-NEXT: vcmp.i32 ne, q0, zr
80 ; CHECK-NEXT: vpsel q0, q1, q2
83 %c = icmp ugt <4 x i32> %src, zeroinitializer
84 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
88 define arm_aapcs_vfpcc <4 x i32> @vcmp_ugez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
89 ; CHECK-LABEL: vcmp_ugez_v4i32:
90 ; CHECK: @ %bb.0: @ %entry
91 ; CHECK-NEXT: vmov q0, q1
94 %c = icmp uge <4 x i32> %src, zeroinitializer
95 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
99 define arm_aapcs_vfpcc <4 x i32> @vcmp_ultz_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
100 ; CHECK-LABEL: vcmp_ultz_v4i32:
101 ; CHECK: @ %bb.0: @ %entry
102 ; CHECK-NEXT: vmov q0, q2
105 %c = icmp ult <4 x i32> %src, zeroinitializer
106 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
110 define arm_aapcs_vfpcc <4 x i32> @vcmp_ulez_v4i32(<4 x i32> %src, <4 x i32> %a, <4 x i32> %b) {
111 ; CHECK-LABEL: vcmp_ulez_v4i32:
112 ; CHECK: @ %bb.0: @ %entry
113 ; CHECK-NEXT: vcmp.u32 cs, q0, zr
114 ; CHECK-NEXT: vpsel q0, q1, q2
117 %c = icmp ule <4 x i32> %src, zeroinitializer
118 %s = select <4 x i1> %c, <4 x i32> %a, <4 x i32> %b
123 define arm_aapcs_vfpcc <8 x i16> @vcmp_eqz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
124 ; CHECK-LABEL: vcmp_eqz_v8i16:
125 ; CHECK: @ %bb.0: @ %entry
126 ; CHECK-NEXT: vcmp.i16 eq, q0, zr
127 ; CHECK-NEXT: vpsel q0, q1, q2
130 %c = icmp eq <8 x i16> %src, zeroinitializer
131 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
135 define arm_aapcs_vfpcc <8 x i16> @vcmp_nez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
136 ; CHECK-LABEL: vcmp_nez_v8i16:
137 ; CHECK: @ %bb.0: @ %entry
138 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
139 ; CHECK-NEXT: vpsel q0, q1, q2
142 %c = icmp ne <8 x i16> %src, zeroinitializer
143 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
147 define arm_aapcs_vfpcc <8 x i16> @vcmp_sgtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
148 ; CHECK-LABEL: vcmp_sgtz_v8i16:
149 ; CHECK: @ %bb.0: @ %entry
150 ; CHECK-NEXT: vcmp.s16 gt, q0, zr
151 ; CHECK-NEXT: vpsel q0, q1, q2
154 %c = icmp sgt <8 x i16> %src, zeroinitializer
155 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
159 define arm_aapcs_vfpcc <8 x i16> @vcmp_sgez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
160 ; CHECK-LABEL: vcmp_sgez_v8i16:
161 ; CHECK: @ %bb.0: @ %entry
162 ; CHECK-NEXT: vcmp.s16 ge, q0, zr
163 ; CHECK-NEXT: vpsel q0, q1, q2
166 %c = icmp sge <8 x i16> %src, zeroinitializer
167 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
171 define arm_aapcs_vfpcc <8 x i16> @vcmp_sltz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
172 ; CHECK-LABEL: vcmp_sltz_v8i16:
173 ; CHECK: @ %bb.0: @ %entry
174 ; CHECK-NEXT: vcmp.s16 lt, q0, zr
175 ; CHECK-NEXT: vpsel q0, q1, q2
178 %c = icmp slt <8 x i16> %src, zeroinitializer
179 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
183 define arm_aapcs_vfpcc <8 x i16> @vcmp_slez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
184 ; CHECK-LABEL: vcmp_slez_v8i16:
185 ; CHECK: @ %bb.0: @ %entry
186 ; CHECK-NEXT: vcmp.s16 le, q0, zr
187 ; CHECK-NEXT: vpsel q0, q1, q2
190 %c = icmp sle <8 x i16> %src, zeroinitializer
191 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
195 define arm_aapcs_vfpcc <8 x i16> @vcmp_ugtz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
196 ; CHECK-LABEL: vcmp_ugtz_v8i16:
197 ; CHECK: @ %bb.0: @ %entry
198 ; CHECK-NEXT: vcmp.i16 ne, q0, zr
199 ; CHECK-NEXT: vpsel q0, q1, q2
202 %c = icmp ugt <8 x i16> %src, zeroinitializer
203 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
207 define arm_aapcs_vfpcc <8 x i16> @vcmp_ugez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
208 ; CHECK-LABEL: vcmp_ugez_v8i16:
209 ; CHECK: @ %bb.0: @ %entry
210 ; CHECK-NEXT: vmov q0, q1
213 %c = icmp uge <8 x i16> %src, zeroinitializer
214 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
218 define arm_aapcs_vfpcc <8 x i16> @vcmp_ultz_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
219 ; CHECK-LABEL: vcmp_ultz_v8i16:
220 ; CHECK: @ %bb.0: @ %entry
221 ; CHECK-NEXT: vmov q0, q2
224 %c = icmp ult <8 x i16> %src, zeroinitializer
225 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
229 define arm_aapcs_vfpcc <8 x i16> @vcmp_ulez_v8i16(<8 x i16> %src, <8 x i16> %a, <8 x i16> %b) {
230 ; CHECK-LABEL: vcmp_ulez_v8i16:
231 ; CHECK: @ %bb.0: @ %entry
232 ; CHECK-NEXT: vcmp.u16 cs, q0, zr
233 ; CHECK-NEXT: vpsel q0, q1, q2
236 %c = icmp ule <8 x i16> %src, zeroinitializer
237 %s = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b
242 define arm_aapcs_vfpcc <16 x i8> @vcmp_eqz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
243 ; CHECK-LABEL: vcmp_eqz_v16i8:
244 ; CHECK: @ %bb.0: @ %entry
245 ; CHECK-NEXT: vcmp.i8 eq, q0, zr
246 ; CHECK-NEXT: vpsel q0, q1, q2
249 %c = icmp eq <16 x i8> %src, zeroinitializer
250 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
254 define arm_aapcs_vfpcc <16 x i8> @vcmp_nez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
255 ; CHECK-LABEL: vcmp_nez_v16i8:
256 ; CHECK: @ %bb.0: @ %entry
257 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
258 ; CHECK-NEXT: vpsel q0, q1, q2
261 %c = icmp ne <16 x i8> %src, zeroinitializer
262 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
266 define arm_aapcs_vfpcc <16 x i8> @vcmp_sgtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
267 ; CHECK-LABEL: vcmp_sgtz_v16i8:
268 ; CHECK: @ %bb.0: @ %entry
269 ; CHECK-NEXT: vcmp.s8 gt, q0, zr
270 ; CHECK-NEXT: vpsel q0, q1, q2
273 %c = icmp sgt <16 x i8> %src, zeroinitializer
274 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
278 define arm_aapcs_vfpcc <16 x i8> @vcmp_sgez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
279 ; CHECK-LABEL: vcmp_sgez_v16i8:
280 ; CHECK: @ %bb.0: @ %entry
281 ; CHECK-NEXT: vcmp.s8 ge, q0, zr
282 ; CHECK-NEXT: vpsel q0, q1, q2
285 %c = icmp sge <16 x i8> %src, zeroinitializer
286 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
290 define arm_aapcs_vfpcc <16 x i8> @vcmp_sltz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
291 ; CHECK-LABEL: vcmp_sltz_v16i8:
292 ; CHECK: @ %bb.0: @ %entry
293 ; CHECK-NEXT: vcmp.s8 lt, q0, zr
294 ; CHECK-NEXT: vpsel q0, q1, q2
297 %c = icmp slt <16 x i8> %src, zeroinitializer
298 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
302 define arm_aapcs_vfpcc <16 x i8> @vcmp_slez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
303 ; CHECK-LABEL: vcmp_slez_v16i8:
304 ; CHECK: @ %bb.0: @ %entry
305 ; CHECK-NEXT: vcmp.s8 le, q0, zr
306 ; CHECK-NEXT: vpsel q0, q1, q2
309 %c = icmp sle <16 x i8> %src, zeroinitializer
310 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
314 define arm_aapcs_vfpcc <16 x i8> @vcmp_ugtz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
315 ; CHECK-LABEL: vcmp_ugtz_v16i8:
316 ; CHECK: @ %bb.0: @ %entry
317 ; CHECK-NEXT: vcmp.i8 ne, q0, zr
318 ; CHECK-NEXT: vpsel q0, q1, q2
321 %c = icmp ugt <16 x i8> %src, zeroinitializer
322 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
326 define arm_aapcs_vfpcc <16 x i8> @vcmp_ugez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
327 ; CHECK-LABEL: vcmp_ugez_v16i8:
328 ; CHECK: @ %bb.0: @ %entry
329 ; CHECK-NEXT: vmov q0, q1
332 %c = icmp uge <16 x i8> %src, zeroinitializer
333 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
337 define arm_aapcs_vfpcc <16 x i8> @vcmp_ultz_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
338 ; CHECK-LABEL: vcmp_ultz_v16i8:
339 ; CHECK: @ %bb.0: @ %entry
340 ; CHECK-NEXT: vmov q0, q2
343 %c = icmp ult <16 x i8> %src, zeroinitializer
344 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
348 define arm_aapcs_vfpcc <16 x i8> @vcmp_ulez_v16i8(<16 x i8> %src, <16 x i8> %a, <16 x i8> %b) {
349 ; CHECK-LABEL: vcmp_ulez_v16i8:
350 ; CHECK: @ %bb.0: @ %entry
351 ; CHECK-NEXT: vcmp.u8 cs, q0, zr
352 ; CHECK-NEXT: vpsel q0, q1, q2
355 %c = icmp ule <16 x i8> %src, zeroinitializer
356 %s = select <16 x i1> %c, <16 x i8> %a, <16 x i8> %b
361 define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
362 ; CHECK-LABEL: vcmp_eqz_v2i64:
363 ; CHECK: @ %bb.0: @ %entry
364 ; CHECK-NEXT: vmov r0, s1
365 ; CHECK-NEXT: vmov r1, s0
366 ; CHECK-NEXT: orrs r0, r1
367 ; CHECK-NEXT: vmov r1, s2
368 ; CHECK-NEXT: cset r0, eq
369 ; CHECK-NEXT: tst.w r0, #1
370 ; CHECK-NEXT: csetm r0, ne
371 ; CHECK-NEXT: vmov.32 q3[0], r0
372 ; CHECK-NEXT: vmov.32 q3[1], r0
373 ; CHECK-NEXT: vmov r0, s3
374 ; CHECK-NEXT: orrs r0, r1
375 ; CHECK-NEXT: cset r0, eq
376 ; CHECK-NEXT: tst.w r0, #1
377 ; CHECK-NEXT: csetm r0, ne
378 ; CHECK-NEXT: vmov.32 q3[2], r0
379 ; CHECK-NEXT: vmov.32 q3[3], r0
380 ; CHECK-NEXT: vbic q0, q2, q3
381 ; CHECK-NEXT: vand q1, q1, q3
382 ; CHECK-NEXT: vorr q0, q1, q0
385 %c = icmp eq <2 x i64> %src, zeroinitializer
386 %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
390 define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) {
391 ; CHECK-LABEL: vcmp_eqz_v2i32:
392 ; CHECK: @ %bb.0: @ %entry
393 ; CHECK-NEXT: vmov r0, s1
394 ; CHECK-NEXT: vmov r1, s0
395 ; CHECK-NEXT: orrs r0, r1
396 ; CHECK-NEXT: vmov r1, s2
397 ; CHECK-NEXT: cset r0, eq
398 ; CHECK-NEXT: tst.w r0, #1
399 ; CHECK-NEXT: csetm r0, ne
400 ; CHECK-NEXT: vmov.32 q3[0], r0
401 ; CHECK-NEXT: vmov.32 q3[1], r0
402 ; CHECK-NEXT: vmov r0, s3
403 ; CHECK-NEXT: orrs r0, r1
404 ; CHECK-NEXT: cset r0, eq
405 ; CHECK-NEXT: tst.w r0, #1
406 ; CHECK-NEXT: csetm r0, ne
407 ; CHECK-NEXT: vmov.32 q3[2], r0
408 ; CHECK-NEXT: vmov.32 q3[3], r0
409 ; CHECK-NEXT: vbic q0, q2, q3
410 ; CHECK-NEXT: vand q1, q1, q3
411 ; CHECK-NEXT: vorr q0, q1, q0
414 %c = icmp eq <2 x i64> %src, zeroinitializer
415 %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b