utils/TableGen/CodeGenSchedule.h

   1 //===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines structures to encapsulate the machine model as described in
  11 // the target description.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
  16 #define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
  17
  18 #include "llvm/ADT/APInt.h"
  19 #include "llvm/ADT/DenseMap.h"
  20 #include "llvm/ADT/StringMap.h"
  21 #include "llvm/Support/ErrorHandling.h"
  22 #include "llvm/TableGen/Record.h"
  23 #include "llvm/TableGen/SetTheory.h"
  24
  25 namespace llvm {
  26
  27 class CodeGenTarget;
  28 class CodeGenSchedModels;
  29 class CodeGenInstruction;
  30 class CodeGenRegisterClass;
  31
  32 using RecVec = std::vector<Record*>;
  33 using RecIter = std::vector<Record*>::const_iterator;
  34
  35 using IdxVec = std::vector<unsigned>;
  36 using IdxIter = std::vector<unsigned>::const_iterator;
  37
  38 /// We have two kinds of SchedReadWrites. Explicitly defined and inferred
  39 /// sequences.  TheDef is nonnull for explicit SchedWrites, but Sequence may or
  40 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
  41 /// be nonempty.
  42 ///
  43 /// IsVariadic controls whether the variants are expanded into multiple operands
  44 /// or a sequence of writes on one operand.
  45 struct CodeGenSchedRW {
  46   unsigned Index;
  47   std::string Name;
  48   Record *TheDef;
  49   bool IsRead;
  50   bool IsAlias;
  51   bool HasVariants;
  52   bool IsVariadic;
  53   bool IsSequence;
  54   IdxVec Sequence;
  55   RecVec Aliases;
  56
  57   CodeGenSchedRW()
  58     : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
  59       HasVariants(false), IsVariadic(false), IsSequence(false) {}
  60   CodeGenSchedRW(unsigned Idx, Record *Def)
  61     : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
  62     Name = Def->getName();
  63     IsRead = Def->isSubClassOf("SchedRead");
  64     HasVariants = Def->isSubClassOf("SchedVariant");
  65     if (HasVariants)
  66       IsVariadic = Def->getValueAsBit("Variadic");
  67
  68     // Read records don't currently have sequences, but it can be easily
  69     // added. Note that implicit Reads (from ReadVariant) may have a Sequence
  70     // (but no record).
  71     IsSequence = Def->isSubClassOf("WriteSequence");
  72   }
  73
  74   CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
  75                  const std::string &Name)
  76       : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
  77         HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
  78     assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
  79   }
  80
  81   bool isValid() const {
  82     assert((!HasVariants || TheDef) && "Variant write needs record def");
  83     assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
  84     assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
  85     assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
  86     assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
  87     return TheDef || !Sequence.empty();
  88   }
  89
  90 #ifndef NDEBUG
  91   void dump() const;
  92 #endif
  93 };
  94
  95 /// Represent a transition between SchedClasses induced by SchedVariant.
  96 struct CodeGenSchedTransition {
  97   unsigned ToClassIdx;
  98   IdxVec ProcIndices;
  99   RecVec PredTerm;
 100 };
 101
 102 /// Scheduling class.
 103 ///
 104 /// Each instruction description will be mapped to a scheduling class. There are
 105 /// four types of classes:
 106 ///
 107 /// 1) An explicitly defined itinerary class with ItinClassDef set.
 108 /// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
 109 ///
 110 /// 2) An implied class with a list of SchedWrites and SchedReads that are
 111 /// defined in an instruction definition and which are common across all
 112 /// subtargets. ProcIndices contains 0 for any processor.
 113 ///
 114 /// 3) An implied class with a list of InstRW records that map instructions to
 115 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
 116 /// instructions to this class. ProcIndices contains all the processors that
 117 /// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
 118 /// still be defined for processors with no InstRW entry.
 119 ///
 120 /// 4) An inferred class represents a variant of another class that may be
 121 /// resolved at runtime. ProcIndices contains the set of processors that may
 122 /// require the class. ProcIndices are propagated through SchedClasses as
 123 /// variants are expanded. Multiple SchedClasses may be inferred from an
 124 /// itinerary class. Each inherits the processor index from the ItinRW record
 125 /// that mapped the itinerary class to the variant Writes or Reads.
 126 struct CodeGenSchedClass {
 127   unsigned Index;
 128   std::string Name;
 129   Record *ItinClassDef;
 130
 131   IdxVec Writes;
 132   IdxVec Reads;
 133   // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
 134   IdxVec ProcIndices;
 135
 136   std::vector<CodeGenSchedTransition> Transitions;
 137
 138   // InstRW records associated with this class. These records may refer to an
 139   // Instruction no longer mapped to this class by InstrClassMap. These
 140   // Instructions should be ignored by this class because they have been split
 141   // off to join another inferred class.
 142   RecVec InstRWs;
 143
 144   CodeGenSchedClass(unsigned Index, std::string Name, Record *ItinClassDef)
 145     : Index(Index), Name(std::move(Name)), ItinClassDef(ItinClassDef) {}
 146
 147   bool isKeyEqual(Record *IC, ArrayRef<unsigned> W,
 148                   ArrayRef<unsigned> R) const {
 149     return ItinClassDef == IC && makeArrayRef(Writes) == W &&
 150            makeArrayRef(Reads) == R;
 151   }
 152
 153   // Is this class generated from a variants if existing classes? Instructions
 154   // are never mapped directly to inferred scheduling classes.
 155   bool isInferred() const { return !ItinClassDef; }
 156
 157 #ifndef NDEBUG
 158   void dump(const CodeGenSchedModels *SchedModels) const;
 159 #endif
 160 };
 161
 162 /// Represent the cost of allocating a register of register class RCDef.
 163 ///
 164 /// The cost of allocating a register is equivalent to the number of physical
 165 /// registers used by the register renamer. Register costs are defined at
 166 /// register class granularity.
 167 struct CodeGenRegisterCost {
 168   Record *RCDef;
 169   unsigned Cost;
 170   bool AllowMoveElimination;
 171   CodeGenRegisterCost(Record *RC, unsigned RegisterCost, bool AllowMoveElim = false)
 172       : RCDef(RC), Cost(RegisterCost), AllowMoveElimination(AllowMoveElim) {}
 173   CodeGenRegisterCost(const CodeGenRegisterCost &) = default;
 174   CodeGenRegisterCost &operator=(const CodeGenRegisterCost &) = delete;
 175 };
 176
 177 /// A processor register file.
 178 ///
 179 /// This class describes a processor register file. Register file information is
 180 /// currently consumed by external tools like llvm-mca to predict dispatch
 181 /// stalls due to register pressure.
 182 struct CodeGenRegisterFile {
 183   std::string Name;
 184   Record *RegisterFileDef;
 185   unsigned MaxMovesEliminatedPerCycle;
 186   bool AllowZeroMoveEliminationOnly;
 187
 188   unsigned NumPhysRegs;
 189   std::vector<CodeGenRegisterCost> Costs;
 190
 191   CodeGenRegisterFile(StringRef name, Record *def, unsigned MaxMoveElimPerCy = 0,
 192                       bool AllowZeroMoveElimOnly = false)
 193       : Name(name), RegisterFileDef(def),
 194         MaxMovesEliminatedPerCycle(MaxMoveElimPerCy),
 195         AllowZeroMoveEliminationOnly(AllowZeroMoveElimOnly),
 196         NumPhysRegs(0) {}
 197
 198   bool hasDefaultCosts() const { return Costs.empty(); }
 199 };
 200
 201 // Processor model.
 202 //
 203 // ModelName is a unique name used to name an instantiation of MCSchedModel.
 204 //
 205 // ModelDef is NULL for inferred Models. This happens when a processor defines
 206 // an itinerary but no machine model. If the processor defines neither a machine
 207 // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
 208 // the special "NoModel" field set to true.
 209 //
 210 // ItinsDef always points to a valid record definition, but may point to the
 211 // default NoItineraries. NoItineraries has an empty list of InstrItinData
 212 // records.
 213 //
 214 // ItinDefList orders this processor's InstrItinData records by SchedClass idx.
 215 struct CodeGenProcModel {
 216   unsigned Index;
 217   std::string ModelName;
 218   Record *ModelDef;
 219   Record *ItinsDef;
 220
 221   // Derived members...
 222
 223   // Array of InstrItinData records indexed by a CodeGenSchedClass index.
 224   // This list is empty if the Processor has no value for Itineraries.
 225   // Initialized by collectProcItins().
 226   RecVec ItinDefList;
 227
 228   // Map itinerary classes to per-operand resources.
 229   // This list is empty if no ItinRW refers to this Processor.
 230   RecVec ItinRWDefs;
 231
 232   // List of unsupported feature.
 233   // This list is empty if the Processor has no UnsupportedFeatures.
 234   RecVec UnsupportedFeaturesDefs;
 235
 236   // All read/write resources associated with this processor.
 237   RecVec WriteResDefs;
 238   RecVec ReadAdvanceDefs;
 239
 240   // Per-operand machine model resources associated with this processor.
 241   RecVec ProcResourceDefs;
 242
 243   // List of Register Files.
 244   std::vector<CodeGenRegisterFile> RegisterFiles;
 245
 246   // Optional Retire Control Unit definition.
 247   Record *RetireControlUnit;
 248
 249   CodeGenProcModel(unsigned Idx, std::string Name, Record *MDef,
 250                    Record *IDef) :
 251     Index(Idx), ModelName(std::move(Name)), ModelDef(MDef), ItinsDef(IDef),
 252     RetireControlUnit(nullptr) {}
 253
 254   bool hasItineraries() const {
 255     return !ItinsDef->getValueAsListOfDefs("IID").empty();
 256   }
 257
 258   bool hasInstrSchedModel() const {
 259     return !WriteResDefs.empty() || !ItinRWDefs.empty();
 260   }
 261
 262   bool hasExtraProcessorInfo() const {
 263     return RetireControlUnit || !RegisterFiles.empty();
 264   }
 265
 266   unsigned getProcResourceIdx(Record *PRDef) const;
 267
 268   bool isUnsupported(const CodeGenInstruction &Inst) const;
 269
 270 #ifndef NDEBUG
 271   void dump() const;
 272 #endif
 273 };
 274
 275 /// Used to correlate instructions to MCInstPredicates specified by
 276 /// InstructionEquivalentClass tablegen definitions.
 277 ///
 278 /// Example: a XOR of a register with self, is a known zero-idiom for most
 279 /// X86 processors.
 280 ///
 281 /// Each processor can use a (potentially different) InstructionEquivalenceClass
 282 ///  definition to classify zero-idioms. That means, XORrr is likely to appear
 283 /// in more than one equivalence class (where each class definition is
 284 /// contributed by a different processor).
 285 ///
 286 /// There is no guarantee that the same MCInstPredicate will be used to describe
 287 /// equivalence classes that identify XORrr as a zero-idiom.
 288 ///
 289 /// To be more specific, the requirements for being a zero-idiom XORrr may be
 290 /// different for different processors.
 291 ///
 292 /// Class PredicateInfo identifies a subset of processors that specify the same
 293 /// requirements (i.e. same MCInstPredicate and OperandMask) for an instruction
 294 /// opcode.
 295 ///
 296 /// Back to the example. Field `ProcModelMask` will have one bit set for every
 297 /// processor model that sees XORrr as a zero-idiom, and that specifies the same
 298 /// set of constraints.
 299 ///
 300 /// By construction, there can be multiple instances of PredicateInfo associated
 301 /// with a same instruction opcode. For example, different processors may define
 302 /// different constraints on the same opcode.
 303 ///
 304 /// Field OperandMask can be used as an extra constraint.
 305 /// It may be used to describe conditions that appy only to a subset of the
 306 /// operands of a machine instruction, and the operands subset may not be the
 307 /// same for all processor models.
 308 struct PredicateInfo {
 309   llvm::APInt ProcModelMask; // A set of processor model indices.
 310   llvm::APInt OperandMask;   // An operand mask.
 311   const Record *Predicate;   // MCInstrPredicate definition.
 312   PredicateInfo(llvm::APInt CpuMask, llvm::APInt Operands, const Record *Pred)
 313       : ProcModelMask(CpuMask), OperandMask(Operands), Predicate(Pred) {}
 314
 315   bool operator==(const PredicateInfo &Other) const {
 316     return ProcModelMask == Other.ProcModelMask &&
 317            OperandMask == Other.OperandMask && Predicate == Other.Predicate;
 318   }
 319 };
 320
 321 /// A collection of PredicateInfo objects.
 322 ///
 323 /// There is at least one OpcodeInfo object for every opcode specified by a
 324 /// TIPredicate definition.
 325 class OpcodeInfo {
 326   std::vector<PredicateInfo> Predicates;
 327
 328   OpcodeInfo(const OpcodeInfo &Other) = delete;
 329   OpcodeInfo &operator=(const OpcodeInfo &Other) = delete;
 330
 331 public:
 332   OpcodeInfo() = default;
 333   OpcodeInfo &operator=(OpcodeInfo &&Other) = default;
 334   OpcodeInfo(OpcodeInfo &&Other) = default;
 335
 336   ArrayRef<PredicateInfo> getPredicates() const { return Predicates; }
 337
 338   void addPredicateForProcModel(const llvm::APInt &CpuMask,
 339                                 const llvm::APInt &OperandMask,
 340                                 const Record *Predicate);
 341 };
 342
 343 /// Used to group together tablegen instruction definitions that are subject
 344 /// to a same set of constraints (identified by an instance of OpcodeInfo).
 345 class OpcodeGroup {
 346   OpcodeInfo Info;
 347   std::vector<const Record *> Opcodes;
 348
 349   OpcodeGroup(const OpcodeGroup &Other) = delete;
 350   OpcodeGroup &operator=(const OpcodeGroup &Other) = delete;
 351
 352 public:
 353   OpcodeGroup(OpcodeInfo &&OpInfo) : Info(std::move(OpInfo)) {}
 354   OpcodeGroup(OpcodeGroup &&Other) = default;
 355
 356   void addOpcode(const Record *Opcode) {
 357     assert(std::find(Opcodes.begin(), Opcodes.end(), Opcode) == Opcodes.end() &&
 358            "Opcode already in set!");
 359     Opcodes.push_back(Opcode);
 360   }
 361
 362   ArrayRef<const Record *> getOpcodes() const { return Opcodes; }
 363   const OpcodeInfo &getOpcodeInfo() const { return Info; }
 364 };
 365
 366 /// An STIPredicateFunction descriptor used by tablegen backends to
 367 /// auto-generate the body of a predicate function as a member of tablegen'd
 368 /// class XXXGenSubtargetInfo.
 369 class STIPredicateFunction {
 370   const Record *FunctionDeclaration;
 371
 372   std::vector<const Record *> Definitions;
 373   std::vector<OpcodeGroup> Groups;
 374
 375   STIPredicateFunction(const STIPredicateFunction &Other) = delete;
 376   STIPredicateFunction &operator=(const STIPredicateFunction &Other) = delete;
 377
 378 public:
 379   STIPredicateFunction(const Record *Rec) : FunctionDeclaration(Rec) {}
 380   STIPredicateFunction(STIPredicateFunction &&Other) = default;
 381
 382   bool isCompatibleWith(const STIPredicateFunction &Other) const {
 383     return FunctionDeclaration == Other.FunctionDeclaration;
 384   }
 385
 386   void addDefinition(const Record *Def) { Definitions.push_back(Def); }
 387   void addOpcode(const Record *OpcodeRec, OpcodeInfo &&Info) {
 388     if (Groups.empty() ||
 389         Groups.back().getOpcodeInfo().getPredicates() != Info.getPredicates())
 390       Groups.emplace_back(std::move(Info));
 391     Groups.back().addOpcode(OpcodeRec);
 392   }
 393
 394   StringRef getName() const {
 395     return FunctionDeclaration->getValueAsString("Name");
 396   }
 397   const Record *getDefaultReturnPredicate() const {
 398     return FunctionDeclaration->getValueAsDef("DefaultReturnValue");
 399   }
 400
 401   const Record *getDeclaration() const { return FunctionDeclaration; }
 402   ArrayRef<const Record *> getDefinitions() const { return Definitions; }
 403   ArrayRef<OpcodeGroup> getGroups() const { return Groups; }
 404 };
 405
 406 /// Top level container for machine model data.
 407 class CodeGenSchedModels {
 408   RecordKeeper &Records;
 409   const CodeGenTarget &Target;
 410
 411   // Map dag expressions to Instruction lists.
 412   SetTheory Sets;
 413
 414   // List of unique processor models.
 415   std::vector<CodeGenProcModel> ProcModels;
 416
 417   // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
 418   using ProcModelMapTy = DenseMap<Record*, unsigned>;
 419   ProcModelMapTy ProcModelMap;
 420
 421   // Per-operand SchedReadWrite types.
 422   std::vector<CodeGenSchedRW> SchedWrites;
 423   std::vector<CodeGenSchedRW> SchedReads;
 424
 425   // List of unique SchedClasses.
 426   std::vector<CodeGenSchedClass> SchedClasses;
 427
 428   // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
 429   unsigned NumInstrSchedClasses;
 430
 431   RecVec ProcResourceDefs;
 432   RecVec ProcResGroups;
 433
 434   // Map each instruction to its unique SchedClass index considering the
 435   // combination of it's itinerary class, SchedRW list, and InstRW records.
 436   using InstClassMapTy = DenseMap<Record*, unsigned>;
 437   InstClassMapTy InstrClassMap;
 438
 439   std::vector<STIPredicateFunction> STIPredicates;
 440
 441 public:
 442   CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
 443
 444   // iterator access to the scheduling classes.
 445   using class_iterator = std::vector<CodeGenSchedClass>::iterator;
 446   using const_class_iterator = std::vector<CodeGenSchedClass>::const_iterator;
 447   class_iterator classes_begin() { return SchedClasses.begin(); }
 448   const_class_iterator classes_begin() const { return SchedClasses.begin(); }
 449   class_iterator classes_end() { return SchedClasses.end(); }
 450   const_class_iterator classes_end() const { return SchedClasses.end(); }
 451   iterator_range<class_iterator> classes() {
 452    return make_range(classes_begin(), classes_end());
 453   }
 454   iterator_range<const_class_iterator> classes() const {
 455    return make_range(classes_begin(), classes_end());
 456   }
 457   iterator_range<class_iterator> explicit_classes() {
 458     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
 459   }
 460   iterator_range<const_class_iterator> explicit_classes() const {
 461     return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
 462   }
 463
 464   Record *getModelOrItinDef(Record *ProcDef) const {
 465     Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
 466     Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
 467     if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
 468       assert(ModelDef->getValueAsBit("NoModel")
 469              && "Itineraries must be defined within SchedMachineModel");
 470       return ItinsDef;
 471     }
 472     return ModelDef;
 473   }
 474
 475   const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
 476     Record *ModelDef = getModelOrItinDef(ProcDef);
 477     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
 478     assert(I != ProcModelMap.end() && "missing machine model");
 479     return ProcModels[I->second];
 480   }
 481
 482   CodeGenProcModel &getProcModel(Record *ModelDef) {
 483     ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
 484     assert(I != ProcModelMap.end() && "missing machine model");
 485     return ProcModels[I->second];
 486   }
 487   const CodeGenProcModel &getProcModel(Record *ModelDef) const {
 488     return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
 489   }
 490
 491   // Iterate over the unique processor models.
 492   using ProcIter = std::vector<CodeGenProcModel>::const_iterator;
 493   ProcIter procModelBegin() const { return ProcModels.begin(); }
 494   ProcIter procModelEnd() const { return ProcModels.end(); }
 495   ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
 496
 497   // Return true if any processors have itineraries.
 498   bool hasItineraries() const;
 499
 500   // Get a SchedWrite from its index.
 501   const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
 502     assert(Idx < SchedWrites.size() && "bad SchedWrite index");
 503     assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
 504     return SchedWrites[Idx];
 505   }
 506   // Get a SchedWrite from its index.
 507   const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
 508     assert(Idx < SchedReads.size() && "bad SchedRead index");
 509     assert(SchedReads[Idx].isValid() && "invalid SchedRead");
 510     return SchedReads[Idx];
 511   }
 512
 513   const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
 514     return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
 515   }
 516   CodeGenSchedRW &getSchedRW(Record *Def) {
 517     bool IsRead = Def->isSubClassOf("SchedRead");
 518     unsigned Idx = getSchedRWIdx(Def, IsRead);
 519     return const_cast<CodeGenSchedRW&>(
 520       IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
 521   }
 522   const CodeGenSchedRW &getSchedRW(Record *Def) const {
 523     return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
 524   }
 525
 526   unsigned getSchedRWIdx(const Record *Def, bool IsRead) const;
 527
 528   // Return true if the given write record is referenced by a ReadAdvance.
 529   bool hasReadOfWrite(Record *WriteDef) const;
 530
 531   // Get a SchedClass from its index.
 532   CodeGenSchedClass &getSchedClass(unsigned Idx) {
 533     assert(Idx < SchedClasses.size() && "bad SchedClass index");
 534     return SchedClasses[Idx];
 535   }
 536   const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
 537     assert(Idx < SchedClasses.size() && "bad SchedClass index");
 538     return SchedClasses[Idx];
 539   }
 540
 541   // Get the SchedClass index for an instruction. Instructions with no
 542   // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
 543   // for NoItinerary.
 544   unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
 545
 546   using SchedClassIter = std::vector<CodeGenSchedClass>::const_iterator;
 547   SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
 548   SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
 549   ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
 550
 551   unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
 552
 553   void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
 554   void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
 555   void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
 556   void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
 557                           const CodeGenProcModel &ProcModel) const;
 558
 559   unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
 560                          ArrayRef<unsigned> OperReads,
 561                          ArrayRef<unsigned> ProcIndices);
 562
 563   unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
 564
 565   Record *findProcResUnits(Record *ProcResKind, const CodeGenProcModel &PM,
 566                            ArrayRef<SMLoc> Loc) const;
 567
 568   ArrayRef<STIPredicateFunction> getSTIPredicates() const {
 569     return STIPredicates;
 570   }
 571 private:
 572   void collectProcModels();
 573
 574   // Initialize a new processor model if it is unique.
 575   void addProcModel(Record *ProcDef);
 576
 577   void collectSchedRW();
 578
 579   std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
 580   unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
 581
 582   void collectSchedClasses();
 583
 584   void collectRetireControlUnits();
 585
 586   void collectRegisterFiles();
 587
 588   void collectOptionalProcessorInfo();
 589
 590   std::string createSchedClassName(Record *ItinClassDef,
 591                                    ArrayRef<unsigned> OperWrites,
 592                                    ArrayRef<unsigned> OperReads);
 593   std::string createSchedClassName(const RecVec &InstDefs);
 594   void createInstRWClass(Record *InstRWDef);
 595
 596   void collectProcItins();
 597
 598   void collectProcItinRW();
 599
 600   void collectProcUnsupportedFeatures();
 601
 602   void inferSchedClasses();
 603
 604   void checkMCInstPredicates() const;
 605
 606   void checkSTIPredicates() const;
 607
 608   void collectSTIPredicates();
 609
 610   void checkCompleteness();
 611
 612   void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
 613                    unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
 614   void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
 615   void inferFromInstRWs(unsigned SCIdx);
 616
 617   bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
 618   void verifyProcResourceGroups(CodeGenProcModel &PM);
 619
 620   void collectProcResources();
 621
 622   void collectItinProcResources(Record *ItinClassDef);
 623
 624   void collectRWResources(unsigned RWIdx, bool IsRead,
 625                           ArrayRef<unsigned> ProcIndices);
 626
 627   void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
 628                           ArrayRef<unsigned> ProcIndices);
 629
 630   void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM,
 631                        ArrayRef<SMLoc> Loc);
 632
 633   void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
 634
 635   void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
 636 };
 637
 638 } // namespace llvm
 639
 640 #endif