[PowerPC] Do not use vectors to codegen bswap with Altivec turned off
[llvm-core.git] / utils / TableGen / InfoByHwMode.h
blob7be4678f271bdc62d1d0ede6be46276da68bfccb
1 //===--- InfoByHwMode.h -----------------------------------------*- C++ -*-===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // Classes that implement data parameterized by HW modes for instruction
10 // selection. Currently it is ValueTypeByHwMode (parameterized ValueType),
11 // and RegSizeInfoByHwMode (parameterized register/spill size and alignment
12 // data).
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
16 #define LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
18 #include "CodeGenHwModes.h"
19 #include "llvm/Support/MachineValueType.h"
21 #include <map>
22 #include <set>
23 #include <string>
24 #include <vector>
26 namespace llvm {
28 struct CodeGenHwModes;
29 class Record;
30 class raw_ostream;
32 template <typename InfoT> struct InfoByHwMode;
34 std::string getModeName(unsigned Mode);
36 enum : unsigned {
37 DefaultMode = CodeGenHwModes::DefaultMode,
40 template <typename InfoT>
41 std::vector<unsigned> union_modes(const InfoByHwMode<InfoT> &A,
42 const InfoByHwMode<InfoT> &B) {
43 std::vector<unsigned> V;
44 std::set<unsigned> U;
45 for (const auto &P : A)
46 U.insert(P.first);
47 for (const auto &P : B)
48 U.insert(P.first);
49 // Make sure that the default mode is last on the list.
50 bool HasDefault = false;
51 for (unsigned M : U)
52 if (M != DefaultMode)
53 V.push_back(M);
54 else
55 HasDefault = true;
56 if (HasDefault)
57 V.push_back(DefaultMode);
58 return V;
61 template <typename InfoT>
62 struct InfoByHwMode {
63 typedef std::map<unsigned,InfoT> MapType;
64 typedef typename MapType::value_type PairType;
65 typedef typename MapType::iterator iterator;
66 typedef typename MapType::const_iterator const_iterator;
68 InfoByHwMode() = default;
69 InfoByHwMode(const MapType &M) : Map(M) {}
71 LLVM_ATTRIBUTE_ALWAYS_INLINE
72 iterator begin() { return Map.begin(); }
73 LLVM_ATTRIBUTE_ALWAYS_INLINE
74 iterator end() { return Map.end(); }
75 LLVM_ATTRIBUTE_ALWAYS_INLINE
76 const_iterator begin() const { return Map.begin(); }
77 LLVM_ATTRIBUTE_ALWAYS_INLINE
78 const_iterator end() const { return Map.end(); }
79 LLVM_ATTRIBUTE_ALWAYS_INLINE
80 bool empty() const { return Map.empty(); }
82 LLVM_ATTRIBUTE_ALWAYS_INLINE
83 bool hasMode(unsigned M) const { return Map.find(M) != Map.end(); }
84 LLVM_ATTRIBUTE_ALWAYS_INLINE
85 bool hasDefault() const { return hasMode(DefaultMode); }
87 InfoT &get(unsigned Mode) {
88 if (!hasMode(Mode)) {
89 assert(hasMode(DefaultMode));
90 Map.insert({Mode, Map.at(DefaultMode)});
92 return Map.at(Mode);
94 const InfoT &get(unsigned Mode) const {
95 auto F = Map.find(Mode);
96 if (Mode != DefaultMode && F == Map.end())
97 F = Map.find(DefaultMode);
98 assert(F != Map.end());
99 return F->second;
102 LLVM_ATTRIBUTE_ALWAYS_INLINE
103 bool isSimple() const {
104 return Map.size() == 1 && Map.begin()->first == DefaultMode;
106 LLVM_ATTRIBUTE_ALWAYS_INLINE
107 InfoT getSimple() const {
108 assert(isSimple());
109 return Map.begin()->second;
111 void makeSimple(unsigned Mode) {
112 assert(hasMode(Mode) || hasDefault());
113 InfoT I = get(Mode);
114 Map.clear();
115 Map.insert(std::make_pair(DefaultMode, I));
118 MapType Map;
121 struct ValueTypeByHwMode : public InfoByHwMode<MVT> {
122 ValueTypeByHwMode(Record *R, const CodeGenHwModes &CGH);
123 ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode,T}); }
124 ValueTypeByHwMode() = default;
126 bool operator== (const ValueTypeByHwMode &T) const;
127 bool operator< (const ValueTypeByHwMode &T) const;
129 bool isValid() const {
130 return !Map.empty();
132 MVT getType(unsigned Mode) const { return get(Mode); }
133 MVT &getOrCreateTypeForMode(unsigned Mode, MVT Type);
135 static StringRef getMVTName(MVT T);
136 void writeToStream(raw_ostream &OS) const;
137 void dump() const;
140 ValueTypeByHwMode getValueTypeByHwMode(Record *Rec,
141 const CodeGenHwModes &CGH);
143 struct RegSizeInfo {
144 unsigned RegSize;
145 unsigned SpillSize;
146 unsigned SpillAlignment;
148 RegSizeInfo(Record *R, const CodeGenHwModes &CGH);
149 RegSizeInfo() = default;
150 bool operator< (const RegSizeInfo &I) const;
151 bool operator== (const RegSizeInfo &I) const {
152 return std::tie(RegSize, SpillSize, SpillAlignment) ==
153 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
155 bool operator!= (const RegSizeInfo &I) const {
156 return !(*this == I);
159 bool isSubClassOf(const RegSizeInfo &I) const;
160 void writeToStream(raw_ostream &OS) const;
163 struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
164 RegSizeInfoByHwMode(Record *R, const CodeGenHwModes &CGH);
165 RegSizeInfoByHwMode() = default;
166 bool operator< (const RegSizeInfoByHwMode &VI) const;
167 bool operator== (const RegSizeInfoByHwMode &VI) const;
168 bool operator!= (const RegSizeInfoByHwMode &VI) const {
169 return !(*this == VI);
172 bool isSubClassOf(const RegSizeInfoByHwMode &I) const;
173 bool hasStricterSpillThan(const RegSizeInfoByHwMode &I) const;
175 void writeToStream(raw_ostream &OS) const;
178 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
179 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
180 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);
182 } // namespace llvm
184 #endif // LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H