1 //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the RegisterClassInfo class which provides dynamic
11 // information about target register classes. Callee-saved vs. caller-saved and
12 // reserved registers depend on calling conventions and other dynamic
13 // information, so some things cannot be determined statically.
15 //===----------------------------------------------------------------------===//
17 #include "llvm/CodeGen/RegisterClassInfo.h"
18 #include "llvm/ADT/ArrayRef.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/MC/MCRegisterInfo.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
29 #include "llvm/Target/TargetSubtargetInfo.h"
36 #define DEBUG_TYPE "regalloc"
38 static cl::opt
<unsigned>
39 StressRA("stress-regalloc", cl::Hidden
, cl::init(0), cl::value_desc("N"),
40 cl::desc("Limit all regclasses to N registers"));
42 RegisterClassInfo::RegisterClassInfo() = default;
44 void RegisterClassInfo::runOnMachineFunction(const MachineFunction
&mf
) {
48 // Allocate new array the first time we see a new target.
49 if (MF
->getSubtarget().getRegisterInfo() != TRI
) {
50 TRI
= MF
->getSubtarget().getRegisterInfo();
51 RegClass
.reset(new RCInfo
[TRI
->getNumRegClasses()]);
52 unsigned NumPSets
= TRI
->getNumRegPressureSets();
53 PSetLimits
.reset(new unsigned[NumPSets
]);
54 std::fill(&PSetLimits
[0], &PSetLimits
[NumPSets
], 0);
58 // Does this MF have different CSRs?
59 assert(TRI
&& "no register info set");
61 // Get the callee saved registers.
62 const MCPhysReg
*CSR
= MF
->getRegInfo().getCalleeSavedRegs();
63 if (Update
|| CSR
!= CalleeSavedRegs
) {
64 // Build a CSRAlias map. Every CSR alias saves the last
66 CalleeSavedAliases
.resize(TRI
->getNumRegs(), 0);
67 for (const MCPhysReg
*I
= CSR
; *I
; ++I
)
68 for (MCRegAliasIterator
AI(*I
, TRI
, true); AI
.isValid(); ++AI
)
69 CalleeSavedAliases
[*AI
] = *I
;
73 CalleeSavedRegs
= CSR
;
75 // Different reserved registers?
76 const BitVector
&RR
= MF
->getRegInfo().getReservedRegs();
77 if (Reserved
.size() != RR
.size() || RR
!= Reserved
) {
82 // Invalidate cached information from previous function.
87 /// compute - Compute the preferred allocation order for RC with reserved
88 /// registers filtered out. Volatile registers come first followed by CSR
89 /// aliases ordered according to the CSR order specified by the target.
90 void RegisterClassInfo::compute(const TargetRegisterClass
*RC
) const {
91 assert(RC
&& "no register class given");
92 RCInfo
&RCI
= RegClass
[RC
->getID()];
94 // Raw register count, including all reserved regs.
95 unsigned NumRegs
= RC
->getNumRegs();
98 RCI
.Order
.reset(new MCPhysReg
[NumRegs
]);
101 SmallVector
<MCPhysReg
, 16> CSRAlias
;
102 unsigned MinCost
= 0xff;
103 unsigned LastCost
= ~0u;
104 unsigned LastCostChange
= 0;
106 // FIXME: Once targets reserve registers instead of removing them from the
107 // allocation order, we can simply use begin/end here.
108 ArrayRef
<MCPhysReg
> RawOrder
= RC
->getRawAllocationOrder(*MF
);
109 for (unsigned i
= 0; i
!= RawOrder
.size(); ++i
) {
110 unsigned PhysReg
= RawOrder
[i
];
111 // Remove reserved registers from the allocation order.
112 if (Reserved
.test(PhysReg
))
114 unsigned Cost
= TRI
->getCostPerUse(PhysReg
);
115 MinCost
= std::min(MinCost
, Cost
);
117 if (CalleeSavedAliases
[PhysReg
])
118 // PhysReg aliases a CSR, save it for later.
119 CSRAlias
.push_back(PhysReg
);
121 if (Cost
!= LastCost
)
123 RCI
.Order
[N
++] = PhysReg
;
127 RCI
.NumRegs
= N
+ CSRAlias
.size();
128 assert(RCI
.NumRegs
<= NumRegs
&& "Allocation order larger than regclass");
130 // CSR aliases go after the volatile registers, preserve the target's order.
131 for (unsigned i
= 0, e
= CSRAlias
.size(); i
!= e
; ++i
) {
132 unsigned PhysReg
= CSRAlias
[i
];
133 unsigned Cost
= TRI
->getCostPerUse(PhysReg
);
134 if (Cost
!= LastCost
)
136 RCI
.Order
[N
++] = PhysReg
;
140 // Register allocator stress test. Clip register class to N registers.
141 if (StressRA
&& RCI
.NumRegs
> StressRA
)
142 RCI
.NumRegs
= StressRA
;
144 // Check if RC is a proper sub-class.
145 if (const TargetRegisterClass
*Super
=
146 TRI
->getLargestLegalSuperClass(RC
, *MF
))
147 if (Super
!= RC
&& getNumAllocatableRegs(Super
) > RCI
.NumRegs
)
148 RCI
.ProperSubClass
= true;
150 RCI
.MinCost
= uint8_t(MinCost
);
151 RCI
.LastCostChange
= LastCostChange
;
154 dbgs() << "AllocationOrder(" << TRI
->getRegClassName(RC
) << ") = [";
155 for (unsigned I
= 0; I
!= RCI
.NumRegs
; ++I
)
156 dbgs() << ' ' << PrintReg(RCI
.Order
[I
], TRI
);
157 dbgs() << (RCI
.ProperSubClass
? " ] (sub-class)\n" : " ]\n");
160 // RCI is now up-to-date.
164 /// This is not accurate because two overlapping register sets may have some
165 /// nonoverlapping reserved registers. However, computing the allocation order
166 /// for all register classes would be too expensive.
167 unsigned RegisterClassInfo::computePSetLimit(unsigned Idx
) const {
168 const TargetRegisterClass
*RC
= nullptr;
169 unsigned NumRCUnits
= 0;
170 for (const TargetRegisterClass
*C
: TRI
->regclasses()) {
171 const int *PSetID
= TRI
->getRegClassPressureSets(C
);
172 for (; *PSetID
!= -1; ++PSetID
) {
173 if ((unsigned)*PSetID
== Idx
)
179 // Found a register class that counts against this pressure set.
180 // For efficiency, only compute the set order for the largest set.
181 unsigned NUnits
= TRI
->getRegClassWeight(C
).WeightLimit
;
182 if (!RC
|| NUnits
> NumRCUnits
) {
188 unsigned NReserved
= RC
->getNumRegs() - getNumAllocatableRegs(RC
);
189 return TRI
->getRegPressureSetLimit(*MF
, Idx
) -
190 TRI
->getRegClassWeight(RC
).RegWeight
* NReserved
;