2 **************************************************
4 * Automatically generated file, do not edit! *
6 **************************************************
8 .. _amdgpu_synid8_imask:
11 ===========================
13 This operand is a mask which controls indexing mode for operands of subsequent instructions.
14 Bits 0, 1 and 2 control indexing of *src0*, *src1* and *src2*, while bit 3 controls indexing of *dst*.
15 Value 1 enables indexing and value 0 disables it.
17 ===== ========================================
19 ===== ========================================
20 0 Enables or disables *src0* indexing.
21 1 Enables or disables *src1* indexing.
22 2 Enables or disables *src2* indexing.
23 3 Enables or disables *dst* indexing.
24 ===== ========================================
26 This operand may be specified as one of the following:
28 * An :ref:`integer_number<amdgpu_synid_integer_number>` or an :ref:`absolute_expression<amdgpu_synid_absolute_expression>`. The value must be in the range 0..15.
29 * A *gpr_idx* value described below.
31 ==================================== ===========================================
32 Gpr_idx Value Syntax Description
33 ==================================== ===========================================
34 gpr_idx(*<operands>*) Enable indexing for specified *operands*
35 and disable it for the rest.
36 *Operands* is a comma-separated list of
37 values which may include:
39 * "SRC0" - enable *src0* indexing.
41 * "SRC1" - enable *src1* indexing.
43 * "SRC2" - enable *src2* indexing.
45 * "DST" - enable *dst* indexing.
47 Each of these values may be specified only
50 *Operands* list may be empty; this syntax
51 disables indexing for all operands.
52 ==================================== ===========================================
59 s_set_gpr_idx_mode gpr_idx() // the same as above
62 s_set_gpr_idx_mode gpr_idx(DST,SRC0,SRC1,SRC2) // the same as above
63 s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) // the same as above
65 s_set_gpr_idx_mode gpr_idx(DST,SRC1)