lib/Target/ARM/ARMISelLowering.h

   1 //===- ARMISelLowering.h - ARM DAG Lowering Interface -----------*- C++ -*-===//
   2 //
   3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   4 // See https://llvm.org/LICENSE.txt for license information.
   5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   6 //
   7 //===----------------------------------------------------------------------===//
   8 //
   9 // This file defines the interfaces that ARM uses to lower LLVM code into a
  10 // selection DAG.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  15 #define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
  16
  17 #include "MCTargetDesc/ARMBaseInfo.h"
  18 #include "llvm/ADT/SmallVector.h"
  19 #include "llvm/ADT/StringRef.h"
  20 #include "llvm/CodeGen/CallingConvLower.h"
  21 #include "llvm/CodeGen/ISDOpcodes.h"
  22 #include "llvm/CodeGen/MachineFunction.h"
  23 #include "llvm/CodeGen/SelectionDAGNodes.h"
  24 #include "llvm/CodeGen/TargetLowering.h"
  25 #include "llvm/CodeGen/ValueTypes.h"
  26 #include "llvm/IR/Attributes.h"
  27 #include "llvm/IR/CallingConv.h"
  28 #include "llvm/IR/Function.h"
  29 #include "llvm/IR/IRBuilder.h"
  30 #include "llvm/IR/InlineAsm.h"
  31 #include "llvm/Support/CodeGen.h"
  32 #include "llvm/Support/MachineValueType.h"
  33 #include <utility>
  34
  35 namespace llvm {
  36
  37 class ARMSubtarget;
  38 class DataLayout;
  39 class FastISel;
  40 class FunctionLoweringInfo;
  41 class GlobalValue;
  42 class InstrItineraryData;
  43 class Instruction;
  44 class MachineBasicBlock;
  45 class MachineInstr;
  46 class SelectionDAG;
  47 class TargetLibraryInfo;
  48 class TargetMachine;
  49 class TargetRegisterInfo;
  50 class VectorType;
  51
  52   namespace ARMISD {
  53
  54     // ARM Specific DAG Nodes
  55     enum NodeType : unsigned {
  56       // Start the numbering where the builtin ops and target ops leave off.
  57       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  58
  59       Wrapper,      // Wrapper - A wrapper node for TargetConstantPool,
  60                     // TargetExternalSymbol, and TargetGlobalAddress.
  61       WrapperPIC,   // WrapperPIC - A wrapper node for TargetGlobalAddress in
  62                     // PIC mode.
  63       WrapperJT,    // WrapperJT - A wrapper node for TargetJumpTable
  64
  65       // Add pseudo op to model memcpy for struct byval.
  66       COPY_STRUCT_BYVAL,
  67
  68       CALL,         // Function call.
  69       CALL_PRED,    // Function call that's predicable.
  70       CALL_NOLINK,  // Function call with branch not branch-and-link.
  71       BRCOND,       // Conditional branch.
  72       BR_JT,        // Jumptable branch.
  73       BR2_JT,       // Jumptable branch (2 level - jumptable entry is a jump).
  74       RET_FLAG,     // Return with a flag operand.
  75       INTRET_FLAG,  // Interrupt return with an LR-offset and a flag operand.
  76
  77       PIC_ADD,      // Add with a PC operand and a PIC label.
  78
  79       ASRL,         // MVE long arithmetic shift right.
  80       LSRL,         // MVE long shift right.
  81       LSLL,         // MVE long shift left.
  82
  83       CMP,          // ARM compare instructions.
  84       CMN,          // ARM CMN instructions.
  85       CMPZ,         // ARM compare that sets only Z flag.
  86       CMPFP,        // ARM VFP compare instruction, sets FPSCR.
  87       CMPFPw0,      // ARM VFP compare against zero instruction, sets FPSCR.
  88       FMSTAT,       // ARM fmstat instruction.
  89
  90       CMOV,         // ARM conditional move instructions.
  91       SUBS,         // Flag-setting subtraction.
  92
  93       SSAT,         // Signed saturation
  94       USAT,         // Unsigned saturation
  95
  96       BCC_i64,
  97
  98       SRL_FLAG,     // V,Flag = srl_flag X -> srl X, 1 + save carry out.
  99       SRA_FLAG,     // V,Flag = sra_flag X -> sra X, 1 + save carry out.
 100       RRX,          // V = RRX X, Flag     -> srl X, 1 + shift in carry flag.
 101
 102       ADDC,         // Add with carry
 103       ADDE,         // Add using carry
 104       SUBC,         // Sub with carry
 105       SUBE,         // Sub using carry
 106       LSLS,         // Shift left producing carry
 107
 108       VMOVRRD,      // double to two gprs.
 109       VMOVDRR,      // Two gprs to double.
 110       VMOVSR,       // move gpr to single, used for f32 literal constructed in a gpr
 111
 112       EH_SJLJ_SETJMP,         // SjLj exception handling setjmp.
 113       EH_SJLJ_LONGJMP,        // SjLj exception handling longjmp.
 114       EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
 115
 116       TC_RETURN,    // Tail call return pseudo.
 117
 118       THREAD_POINTER,
 119
 120       DYN_ALLOC,    // Dynamic allocation on the stack.
 121
 122       MEMBARRIER_MCR, // Memory barrier (MCR)
 123
 124       PRELOAD,      // Preload
 125
 126       WIN__CHKSTK,  // Windows' __chkstk call to do stack probing.
 127       WIN__DBZCHK,  // Windows' divide by zero check
 128
 129       WLS,          // Low-overhead loops, While Loop Start
 130       LOOP_DEC,     // Really a part of LE, performs the sub
 131       LE,           // Low-overhead loops, Loop End
 132
 133       PREDICATE_CAST, // Predicate cast for MVE i1 types
 134
 135       VCMP,         // Vector compare.
 136       VCMPZ,        // Vector compare to zero.
 137       VTST,         // Vector test bits.
 138
 139       // Vector shift by vector
 140       VSHLs,        // ...left/right by signed
 141       VSHLu,        // ...left/right by unsigned
 142
 143       // Vector shift by immediate:
 144       VSHLIMM,      // ...left
 145       VSHRsIMM,     // ...right (signed)
 146       VSHRuIMM,     // ...right (unsigned)
 147
 148       // Vector rounding shift by immediate:
 149       VRSHRsIMM,    // ...right (signed)
 150       VRSHRuIMM,    // ...right (unsigned)
 151       VRSHRNIMM,    // ...right narrow
 152
 153       // Vector saturating shift by immediate:
 154       VQSHLsIMM,    // ...left (signed)
 155       VQSHLuIMM,    // ...left (unsigned)
 156       VQSHLsuIMM,   // ...left (signed to unsigned)
 157       VQSHRNsIMM,   // ...right narrow (signed)
 158       VQSHRNuIMM,   // ...right narrow (unsigned)
 159       VQSHRNsuIMM,  // ...right narrow (signed to unsigned)
 160
 161       // Vector saturating rounding shift by immediate:
 162       VQRSHRNsIMM,  // ...right narrow (signed)
 163       VQRSHRNuIMM,  // ...right narrow (unsigned)
 164       VQRSHRNsuIMM, // ...right narrow (signed to unsigned)
 165
 166       // Vector shift and insert:
 167       VSLIIMM,      // ...left
 168       VSRIIMM,      // ...right
 169
 170       // Vector get lane (VMOV scalar to ARM core register)
 171       // (These are used for 8- and 16-bit element types only.)
 172       VGETLANEu,    // zero-extend vector extract element
 173       VGETLANEs,    // sign-extend vector extract element
 174
 175       // Vector move immediate and move negated immediate:
 176       VMOVIMM,
 177       VMVNIMM,
 178
 179       // Vector move f32 immediate:
 180       VMOVFPIMM,
 181
 182       // Move H <-> R, clearing top 16 bits
 183       VMOVrh,
 184       VMOVhr,
 185
 186       // Vector duplicate:
 187       VDUP,
 188       VDUPLANE,
 189
 190       // Vector shuffles:
 191       VEXT,         // extract
 192       VREV64,       // reverse elements within 64-bit doublewords
 193       VREV32,       // reverse elements within 32-bit words
 194       VREV16,       // reverse elements within 16-bit halfwords
 195       VZIP,         // zip (interleave)
 196       VUZP,         // unzip (deinterleave)
 197       VTRN,         // transpose
 198       VTBL1,        // 1-register shuffle with mask
 199       VTBL2,        // 2-register shuffle with mask
 200       VMOVN,        // MVE vmovn
 201
 202       // Vector multiply long:
 203       VMULLs,       // ...signed
 204       VMULLu,       // ...unsigned
 205
 206       SMULWB,       // Signed multiply word by half word, bottom
 207       SMULWT,       // Signed multiply word by half word, top
 208       UMLAL,        // 64bit Unsigned Accumulate Multiply
 209       SMLAL,        // 64bit Signed Accumulate Multiply
 210       UMAAL,        // 64-bit Unsigned Accumulate Accumulate Multiply
 211       SMLALBB,      // 64-bit signed accumulate multiply bottom, bottom 16
 212       SMLALBT,      // 64-bit signed accumulate multiply bottom, top 16
 213       SMLALTB,      // 64-bit signed accumulate multiply top, bottom 16
 214       SMLALTT,      // 64-bit signed accumulate multiply top, top 16
 215       SMLALD,       // Signed multiply accumulate long dual
 216       SMLALDX,      // Signed multiply accumulate long dual exchange
 217       SMLSLD,       // Signed multiply subtract long dual
 218       SMLSLDX,      // Signed multiply subtract long dual exchange
 219       SMMLAR,       // Signed multiply long, round and add
 220       SMMLSR,       // Signed multiply long, subtract and round
 221
 222       // Single Lane QADD8 and QADD16. Only the bottom lane. That's what the b stands for.
 223       QADD8b,
 224       QSUB8b,
 225       QADD16b,
 226       QSUB16b,
 227
 228       // Operands of the standard BUILD_VECTOR node are not legalized, which
 229       // is fine if BUILD_VECTORs are always lowered to shuffles or other
 230       // operations, but for ARM some BUILD_VECTORs are legal as-is and their
 231       // operands need to be legalized.  Define an ARM-specific version of
 232       // BUILD_VECTOR for this purpose.
 233       BUILD_VECTOR,
 234
 235       // Bit-field insert
 236       BFI,
 237
 238       // Vector OR with immediate
 239       VORRIMM,
 240       // Vector AND with NOT of immediate
 241       VBICIMM,
 242
 243       // Vector bitwise select
 244       VBSL,
 245
 246       // Pseudo-instruction representing a memory copy using ldm/stm
 247       // instructions.
 248       MEMCPY,
 249
 250       // V8.1MMainline condition select
 251       CSINV, // Conditional select invert.
 252       CSNEG, // Conditional select negate.
 253       CSINC, // Conditional select increment.
 254
 255       // Vector load N-element structure to all lanes:
 256       VLD1DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
 257       VLD2DUP,
 258       VLD3DUP,
 259       VLD4DUP,
 260
 261       // NEON loads with post-increment base updates:
 262       VLD1_UPD,
 263       VLD2_UPD,
 264       VLD3_UPD,
 265       VLD4_UPD,
 266       VLD2LN_UPD,
 267       VLD3LN_UPD,
 268       VLD4LN_UPD,
 269       VLD1DUP_UPD,
 270       VLD2DUP_UPD,
 271       VLD3DUP_UPD,
 272       VLD4DUP_UPD,
 273
 274       // NEON stores with post-increment base updates:
 275       VST1_UPD,
 276       VST2_UPD,
 277       VST3_UPD,
 278       VST4_UPD,
 279       VST2LN_UPD,
 280       VST3LN_UPD,
 281       VST4LN_UPD
 282     };
 283
 284   } // end namespace ARMISD
 285
 286   /// Define some predicates that are used for node matching.
 287   namespace ARM {
 288
 289     bool isBitFieldInvertedMask(unsigned v);
 290
 291   } // end namespace ARM
 292
 293   //===--------------------------------------------------------------------===//
 294   //  ARMTargetLowering - ARM Implementation of the TargetLowering interface
 295
 296   class ARMTargetLowering : public TargetLowering {
 297   public:
 298     explicit ARMTargetLowering(const TargetMachine &TM,
 299                                const ARMSubtarget &STI);
 300
 301     unsigned getJumpTableEncoding() const override;
 302     bool useSoftFloat() const override;
 303
 304     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 305
 306     /// ReplaceNodeResults - Replace the results of node with an illegal result
 307     /// type with new values built out of custom code.
 308     void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 309                             SelectionDAG &DAG) const override;
 310
 311     const char *getTargetNodeName(unsigned Opcode) const override;
 312
 313     bool isSelectSupported(SelectSupportKind Kind) const override {
 314       // ARM does not support scalar condition selects on vectors.
 315       return (Kind != ScalarCondVectorVal);
 316     }
 317
 318     bool isReadOnly(const GlobalValue *GV) const;
 319
 320     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
 321     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
 322                            EVT VT) const override;
 323
 324     MachineBasicBlock *
 325     EmitInstrWithCustomInserter(MachineInstr &MI,
 326                                 MachineBasicBlock *MBB) const override;
 327
 328     void AdjustInstrPostInstrSelection(MachineInstr &MI,
 329                                        SDNode *Node) const override;
 330
 331     SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
 332     SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const;
 333     SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const;
 334     SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
 335
 336     bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
 337
 338     /// allowsMisalignedMemoryAccesses - Returns true if the target allows
 339     /// unaligned memory accesses of the specified type. Returns whether it
 340     /// is "fast" by reference in the second argument.
 341     bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
 342                                         unsigned Align,
 343                                         MachineMemOperand::Flags Flags,
 344                                         bool *Fast) const override;
 345
 346     EVT getOptimalMemOpType(uint64_t Size,
 347                             unsigned DstAlign, unsigned SrcAlign,
 348                             bool IsMemset, bool ZeroMemset,
 349                             bool MemcpyStrSrc,
 350                             const AttributeList &FuncAttributes) const override;
 351
 352     bool isTruncateFree(Type *SrcTy, Type *DstTy) const override;
 353     bool isTruncateFree(EVT SrcVT, EVT DstVT) const override;
 354     bool isZExtFree(SDValue Val, EVT VT2) const override;
 355     bool shouldSinkOperands(Instruction *I,
 356                             SmallVectorImpl<Use *> &Ops) const override;
 357
 358     bool isFNegFree(EVT VT) const override;
 359
 360     bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
 361
 362     bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
 363
 364
 365     /// isLegalAddressingMode - Return true if the addressing mode represented
 366     /// by AM is legal for this target, for a load/store of the specified type.
 367     bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
 368                                Type *Ty, unsigned AS,
 369                                Instruction *I = nullptr) const override;
 370
 371     /// getScalingFactorCost - Return the cost of the scaling used in
 372     /// addressing mode represented by AM.
 373     /// If the AM is supported, the return value must be >= 0.
 374     /// If the AM is not supported, the return value must be negative.
 375     int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM, Type *Ty,
 376                              unsigned AS) const override;
 377
 378     bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 379
 380     /// Returns true if the addresing mode representing by AM is legal
 381     /// for the Thumb1 target, for a load/store of the specified type.
 382     bool isLegalT1ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
 383
 384     /// isLegalICmpImmediate - Return true if the specified immediate is legal
 385     /// icmp immediate, that is the target has icmp instructions which can
 386     /// compare a register against the immediate without having to materialize
 387     /// the immediate into a register.
 388     bool isLegalICmpImmediate(int64_t Imm) const override;
 389
 390     /// isLegalAddImmediate - Return true if the specified immediate is legal
 391     /// add immediate, that is the target has add instructions which can
 392     /// add a register and the immediate without having to materialize
 393     /// the immediate into a register.
 394     bool isLegalAddImmediate(int64_t Imm) const override;
 395
 396     /// getPreIndexedAddressParts - returns true by value, base pointer and
 397     /// offset pointer and addressing mode by reference if the node's address
 398     /// can be legally represented as pre-indexed load / store address.
 399     bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
 400                                    ISD::MemIndexedMode &AM,
 401                                    SelectionDAG &DAG) const override;
 402
 403     /// getPostIndexedAddressParts - returns true by value, base pointer and
 404     /// offset pointer and addressing mode by reference if this node can be
 405     /// combined with a load / store to form a post-indexed load / store.
 406     bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
 407                                     SDValue &Offset, ISD::MemIndexedMode &AM,
 408                                     SelectionDAG &DAG) const override;
 409
 410     void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
 411                                        const APInt &DemandedElts,
 412                                        const SelectionDAG &DAG,
 413                                        unsigned Depth) const override;
 414
 415     bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
 416                                       TargetLoweringOpt &TLO) const override;
 417
 418
 419     bool ExpandInlineAsm(CallInst *CI) const override;
 420
 421     ConstraintType getConstraintType(StringRef Constraint) const override;
 422
 423     /// Examine constraint string and operand type and determine a weight value.
 424     /// The operand object must already have been set up with the operand type.
 425     ConstraintWeight getSingleConstraintMatchWeight(
 426       AsmOperandInfo &info, const char *constraint) const override;
 427
 428     std::pair<unsigned, const TargetRegisterClass *>
 429     getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
 430                                  StringRef Constraint, MVT VT) const override;
 431
 432     const char *LowerXConstraint(EVT ConstraintVT) const override;
 433
 434     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 435     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
 436     /// true it means one of the asm constraint of the inline asm instruction
 437     /// being processed is 'm'.
 438     void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
 439                                       std::vector<SDValue> &Ops,
 440                                       SelectionDAG &DAG) const override;
 441
 442     unsigned
 443     getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
 444       if (ConstraintCode == "Q")
 445         return InlineAsm::Constraint_Q;
 446       else if (ConstraintCode == "o")
 447         return InlineAsm::Constraint_o;
 448       else if (ConstraintCode.size() == 2) {
 449         if (ConstraintCode[0] == 'U') {
 450           switch(ConstraintCode[1]) {
 451           default:
 452             break;
 453           case 'm':
 454             return InlineAsm::Constraint_Um;
 455           case 'n':
 456             return InlineAsm::Constraint_Un;
 457           case 'q':
 458             return InlineAsm::Constraint_Uq;
 459           case 's':
 460             return InlineAsm::Constraint_Us;
 461           case 't':
 462             return InlineAsm::Constraint_Ut;
 463           case 'v':
 464             return InlineAsm::Constraint_Uv;
 465           case 'y':
 466             return InlineAsm::Constraint_Uy;
 467           }
 468         }
 469       }
 470       return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
 471     }
 472
 473     const ARMSubtarget* getSubtarget() const {
 474       return Subtarget;
 475     }
 476
 477     /// getRegClassFor - Return the register class that should be used for the
 478     /// specified value type.
 479     const TargetRegisterClass *
 480     getRegClassFor(MVT VT, bool isDivergent = false) const override;
 481
 482     /// Returns true if a cast between SrcAS and DestAS is a noop.
 483     bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
 484       // Addrspacecasts are always noops.
 485       return true;
 486     }
 487
 488     bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
 489                                 unsigned &PrefAlign) const override;
 490
 491     /// createFastISel - This method returns a target specific FastISel object,
 492     /// or null if the target does not support "fast" ISel.
 493     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 494                              const TargetLibraryInfo *libInfo) const override;
 495
 496     Sched::Preference getSchedulingPreference(SDNode *N) const override;
 497
 498     bool
 499     isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const override;
 500     bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
 501
 502     /// isFPImmLegal - Returns true if the target can instruction select the
 503     /// specified FP immediate natively. If false, the legalizer will
 504     /// materialize the FP immediate as a load from a constant pool.
 505     bool isFPImmLegal(const APFloat &Imm, EVT VT,
 506                       bool ForCodeSize = false) const override;
 507
 508     bool getTgtMemIntrinsic(IntrinsicInfo &Info,
 509                             const CallInst &I,
 510                             MachineFunction &MF,
 511                             unsigned Intrinsic) const override;
 512
 513     /// Returns true if it is beneficial to convert a load of a constant
 514     /// to just the constant itself.
 515     bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
 516                                            Type *Ty) const override;
 517
 518     /// Return true if EXTRACT_SUBVECTOR is cheap for this result type
 519     /// with this index.
 520     bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
 521                                  unsigned Index) const override;
 522
 523     /// Returns true if an argument of type Ty needs to be passed in a
 524     /// contiguous block of registers in calling convention CallConv.
 525     bool functionArgumentNeedsConsecutiveRegisters(
 526         Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
 527
 528     /// If a physical register, this returns the register that receives the
 529     /// exception address on entry to an EH pad.
 530     unsigned
 531     getExceptionPointerRegister(const Constant *PersonalityFn) const override;
 532
 533     /// If a physical register, this returns the register that receives the
 534     /// exception typeid on entry to a landing pad.
 535     unsigned
 536     getExceptionSelectorRegister(const Constant *PersonalityFn) const override;
 537
 538     Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
 539     Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
 540                           AtomicOrdering Ord) const override;
 541     Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
 542                                 Value *Addr, AtomicOrdering Ord) const override;
 543
 544     void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
 545
 546     Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
 547                                   AtomicOrdering Ord) const override;
 548     Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
 549                                    AtomicOrdering Ord) const override;
 550
 551     unsigned getMaxSupportedInterleaveFactor() const override;
 552
 553     bool lowerInterleavedLoad(LoadInst *LI,
 554                               ArrayRef<ShuffleVectorInst *> Shuffles,
 555                               ArrayRef<unsigned> Indices,
 556                               unsigned Factor) const override;
 557     bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
 558                                unsigned Factor) const override;
 559
 560     bool shouldInsertFencesForAtomic(const Instruction *I) const override;
 561     TargetLoweringBase::AtomicExpansionKind
 562     shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
 563     bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
 564     TargetLoweringBase::AtomicExpansionKind
 565     shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
 566     TargetLoweringBase::AtomicExpansionKind
 567     shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
 568
 569     bool useLoadStackGuardNode() const override;
 570
 571     void insertSSPDeclarations(Module &M) const override;
 572     Value *getSDagStackGuard(const Module &M) const override;
 573     Function *getSSPStackGuardCheck(const Module &M) const override;
 574
 575     bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
 576                                    unsigned &Cost) const override;
 577
 578     bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
 579                           const SelectionDAG &DAG) const override {
 580       // Do not merge to larger than i32.
 581       return (MemVT.getSizeInBits() <= 32);
 582     }
 583
 584     bool isCheapToSpeculateCttz() const override;
 585     bool isCheapToSpeculateCtlz() const override;
 586
 587     bool convertSetCCLogicToBitwiseLogic(EVT VT) const override {
 588       return VT.isScalarInteger();
 589     }
 590
 591     bool supportSwiftError() const override {
 592       return true;
 593     }
 594
 595     bool hasStandaloneRem(EVT VT) const override {
 596       return HasStandaloneRem;
 597     }
 598
 599     bool shouldExpandShift(SelectionDAG &DAG, SDNode *N) const override;
 600
 601     CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isVarArg) const;
 602     CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool isVarArg) const;
 603
 604     /// Returns true if \p VecTy is a legal interleaved access type. This
 605     /// function checks the vector element type and the overall width of the
 606     /// vector.
 607     bool isLegalInterleavedAccessType(VectorType *VecTy,
 608                                       const DataLayout &DL) const;
 609
 610     bool alignLoopsWithOptSize() const override;
 611
 612     /// Returns the number of interleaved accesses that will be generated when
 613     /// lowering accesses of the given type.
 614     unsigned getNumInterleavedAccesses(VectorType *VecTy,
 615                                        const DataLayout &DL) const;
 616
 617     void finalizeLowering(MachineFunction &MF) const override;
 618
 619     /// Return the correct alignment for the current calling convention.
 620     Align getABIAlignmentForCallingConv(Type *ArgTy,
 621                                         DataLayout DL) const override;
 622
 623     bool isDesirableToCommuteWithShift(const SDNode *N,
 624                                        CombineLevel Level) const override;
 625
 626     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
 627                                            CombineLevel Level) const override;
 628
 629     bool preferIncOfAddToSubOfNot(EVT VT) const override;
 630
 631   protected:
 632     std::pair<const TargetRegisterClass *, uint8_t>
 633     findRepresentativeClass(const TargetRegisterInfo *TRI,
 634                             MVT VT) const override;
 635
 636   private:
 637     /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
 638     /// make the right decision when generating code for different targets.
 639     const ARMSubtarget *Subtarget;
 640
 641     const TargetRegisterInfo *RegInfo;
 642
 643     const InstrItineraryData *Itins;
 644
 645     /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
 646     unsigned ARMPCLabelIndex;
 647
 648     // TODO: remove this, and have shouldInsertFencesForAtomic do the proper
 649     // check.
 650     bool InsertFencesForAtomic;
 651
 652     bool HasStandaloneRem = true;
 653
 654     void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
 655     void addDRTypeForNEON(MVT VT);
 656     void addQRTypeForNEON(MVT VT);
 657     std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
 658
 659     using RegsToPassVector = SmallVector<std::pair<unsigned, SDValue>, 8>;
 660
 661     void PassF64ArgInRegs(const SDLoc &dl, SelectionDAG &DAG, SDValue Chain,
 662                           SDValue &Arg, RegsToPassVector &RegsToPass,
 663                           CCValAssign &VA, CCValAssign &NextVA,
 664                           SDValue &StackPtr,
 665                           SmallVectorImpl<SDValue> &MemOpChains,
 666                           ISD::ArgFlagsTy Flags) const;
 667     SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
 668                                  SDValue &Root, SelectionDAG &DAG,
 669                                  const SDLoc &dl) const;
 670
 671     CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
 672                                             bool isVarArg) const;
 673     CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
 674                                   bool isVarArg) const;
 675     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
 676                              const SDLoc &dl, SelectionDAG &DAG,
 677                              const CCValAssign &VA,
 678                              ISD::ArgFlagsTy Flags) const;
 679     SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
 680     SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
 681     SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
 682     SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG,
 683                                     const ARMSubtarget *Subtarget) const;
 684     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
 685                                     const ARMSubtarget *Subtarget) const;
 686     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 687     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 688     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 689     SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 690     SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
 691     SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 692     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 693     SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
 694                                             SelectionDAG &DAG) const;
 695     SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
 696                                  SelectionDAG &DAG,
 697                                  TLSModel::Model model) const;
 698     SDValue LowerGlobalTLSAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
 699     SDValue LowerGlobalTLSAddressWindows(SDValue Op, SelectionDAG &DAG) const;
 700     SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
 701     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
 702     SDValue LowerSignedALUO(SDValue Op, SelectionDAG &DAG) const;
 703     SDValue LowerUnsignedALUO(SDValue Op, SelectionDAG &DAG) const;
 704     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
 705     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 706     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
 707     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
 708     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
 709     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
 710     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 711     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
 712     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
 713     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
 714     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
 715                             const ARMSubtarget *ST) const;
 716     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
 717                               const ARMSubtarget *ST) const;
 718     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
 719     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
 720     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
 721     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;
 722     void ExpandDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed,
 723                            SmallVectorImpl<SDValue> &Results) const;
 724     SDValue LowerWindowsDIVLibCall(SDValue Op, SelectionDAG &DAG, bool Signed,
 725                                    SDValue &Chain) const;
 726     SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
 727     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
 728     SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
 729     SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
 730     SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
 731     SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
 732     void lowerABS(SDNode *N, SmallVectorImpl<SDValue> &Results,
 733                   SelectionDAG &DAG) const;
 734
 735     Register getRegisterByName(const char* RegName, EVT VT,
 736                                const MachineFunction &MF) const override;
 737
 738     SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
 739                           SmallVectorImpl<SDNode *> &Created) const override;
 740
 741     /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
 742     /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
 743     /// expanded to FMAs when this method returns true, otherwise fmuladd is
 744     /// expanded to fmul + fadd.
 745     ///
 746     /// ARM supports both fused and unfused multiply-add operations; we already
 747     /// lower a pair of fmul and fadd to the latter so it's not clear that there
 748     /// would be a gain or that the gain would be worthwhile enough to risk
 749     /// correctness bugs.
 750     bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
 751
 752     SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
 753
 754     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 755                             CallingConv::ID CallConv, bool isVarArg,
 756                             const SmallVectorImpl<ISD::InputArg> &Ins,
 757                             const SDLoc &dl, SelectionDAG &DAG,
 758                             SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
 759                             SDValue ThisVal) const;
 760
 761     bool supportSplitCSR(MachineFunction *MF) const override {
 762       return MF->getFunction().getCallingConv() == CallingConv::CXX_FAST_TLS &&
 763           MF->getFunction().hasFnAttribute(Attribute::NoUnwind);
 764     }
 765
 766     void initializeSplitCSR(MachineBasicBlock *Entry) const override;
 767     void insertCopiesSplitCSR(
 768       MachineBasicBlock *Entry,
 769       const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
 770
 771     SDValue
 772     LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 773                          const SmallVectorImpl<ISD::InputArg> &Ins,
 774                          const SDLoc &dl, SelectionDAG &DAG,
 775                          SmallVectorImpl<SDValue> &InVals) const override;
 776
 777     int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG, const SDLoc &dl,
 778                        SDValue &Chain, const Value *OrigArg,
 779                        unsigned InRegsParamRecordIdx, int ArgOffset,
 780                        unsigned ArgSize) const;
 781
 782     void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
 783                               const SDLoc &dl, SDValue &Chain,
 784                               unsigned ArgOffset, unsigned TotalArgRegsSaveSize,
 785                               bool ForceMutable = false) const;
 786
 787     SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
 788                       SmallVectorImpl<SDValue> &InVals) const override;
 789
 790     /// HandleByVal - Target-specific cleanup for ByVal support.
 791     void HandleByVal(CCState *, unsigned &, unsigned) const override;
 792
 793     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
 794     /// for tail call optimization. Targets which want to do tail call
 795     /// optimization should implement this function.
 796     bool IsEligibleForTailCallOptimization(
 797         SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
 798         bool isCalleeStructRet, bool isCallerStructRet,
 799         const SmallVectorImpl<ISD::OutputArg> &Outs,
 800         const SmallVectorImpl<SDValue> &OutVals,
 801         const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG,
 802         const bool isIndirect) const;
 803
 804     bool CanLowerReturn(CallingConv::ID CallConv,
 805                         MachineFunction &MF, bool isVarArg,
 806                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 807                         LLVMContext &Context) const override;
 808
 809     SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
 810                         const SmallVectorImpl<ISD::OutputArg> &Outs,
 811                         const SmallVectorImpl<SDValue> &OutVals,
 812                         const SDLoc &dl, SelectionDAG &DAG) const override;
 813
 814     bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
 815
 816     bool mayBeEmittedAsTailCall(const CallInst *CI) const override;
 817
 818     bool shouldConsiderGEPOffsetSplit() const override { return true; }
 819
 820     bool isUnsupportedFloatingType(EVT VT) const;
 821
 822     SDValue getCMOV(const SDLoc &dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
 823                     SDValue ARMcc, SDValue CCR, SDValue Cmp,
 824                     SelectionDAG &DAG) const;
 825     SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
 826                       SDValue &ARMcc, SelectionDAG &DAG, const SDLoc &dl) const;
 827     SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG,
 828                       const SDLoc &dl) const;
 829     SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
 830
 831     SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
 832
 833     void SetupEntryBlockForSjLj(MachineInstr &MI, MachineBasicBlock *MBB,
 834                                 MachineBasicBlock *DispatchBB, int FI) const;
 835
 836     void EmitSjLjDispatchBlock(MachineInstr &MI, MachineBasicBlock *MBB) const;
 837
 838     bool RemapAddSubWithFlags(MachineInstr &MI, MachineBasicBlock *BB) const;
 839
 840     MachineBasicBlock *EmitStructByval(MachineInstr &MI,
 841                                        MachineBasicBlock *MBB) const;
 842
 843     MachineBasicBlock *EmitLowered__chkstk(MachineInstr &MI,
 844                                            MachineBasicBlock *MBB) const;
 845     MachineBasicBlock *EmitLowered__dbzchk(MachineInstr &MI,
 846                                            MachineBasicBlock *MBB) const;
 847     void addMVEVectorTypes(bool HasMVEFP);
 848     void addAllExtLoads(const MVT From, const MVT To, LegalizeAction Action);
 849     void setAllExpand(MVT VT);
 850   };
 851
 852   enum VMOVModImmType {
 853     VMOVModImm,
 854     VMVNModImm,
 855     MVEVMVNModImm,
 856     OtherModImm
 857   };
 858
 859   namespace ARM {
 860
 861     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
 862                              const TargetLibraryInfo *libInfo);
 863
 864   } // end namespace ARM
 865
 866 } // end namespace llvm
 867
 868 #endif // LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H