[RISCV] Support 'f' Inline Assembly Constraint
commite190b9fcfe573c911124e06229807da256710f28
authorSam Elliott <selliott@lowrisc.org>
Wed, 31 Jul 2019 09:45:55 +0000 (31 09:45 +0000)
committerSam Elliott <selliott@lowrisc.org>
Wed, 31 Jul 2019 09:45:55 +0000 (31 09:45 +0000)
treefc6af9b74f5bea75fef33df1a6125218e0e12e03
parent05356fa8fefb33e06faa803d1be09ecfee85a3e0
[RISCV] Support 'f' Inline Assembly Constraint

Summary:
This adds the 'f' inline assembly constraint, as supported by GCC. An
'f'-constrained operand is passed in a floating point register. Exactly
which kind of floating-point register (32-bit or 64-bit) is decided
based on the operand type and the available standard extensions (-f and
-d, respectively).

This patch adds support in both the clang frontend, and LLVM itself.

Reviewers: asb, lewis-revill

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D65500

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367403 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/RISCV/RISCVISelLowering.cpp
lib/Target/RISCV/RISCVISelLowering.h
test/CodeGen/RISCV/inline-asm-d-constraint-f.ll [new file with mode: 0644]
test/CodeGen/RISCV/inline-asm-f-constraint-f.ll [new file with mode: 0644]
test/CodeGen/RISCV/inline-asm-invalid.ll