[AMDGPU][AsmParser][NFC] Get rid of custom default operand handlers.
[llvm-project.git] / clang / lib / Headers / avx512ifmavlintrin.h
blob3284ee182004b86624f0f1d5a25589785946c216
1 /*===------------- avx512ifmavlintrin.h - IFMA intrinsics ------------------===
4 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
5 * See https://llvm.org/LICENSE.txt for license information.
6 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
8 *===-----------------------------------------------------------------------===
9 */
10 #ifndef __IMMINTRIN_H
11 #error "Never use <avx512ifmavlintrin.h> directly; include <immintrin.h> instead."
12 #endif
14 #ifndef __IFMAVLINTRIN_H
15 #define __IFMAVLINTRIN_H
17 /* Define the default attributes for the functions in this file. */
18 #define __DEFAULT_FN_ATTRS128 __attribute__((__always_inline__, __nodebug__, __target__("avx512ifma,avx512vl"), __min_vector_width__(128)))
19 #define __DEFAULT_FN_ATTRS256 __attribute__((__always_inline__, __nodebug__, __target__("avx512ifma,avx512vl"), __min_vector_width__(256)))
21 #define _mm_madd52hi_epu64(X, Y, Z) \
22 ((__m128i)__builtin_ia32_vpmadd52huq128((__v2di)(X), (__v2di)(Y), \
23 (__v2di)(Z)))
25 #define _mm256_madd52hi_epu64(X, Y, Z) \
26 ((__m256i)__builtin_ia32_vpmadd52huq256((__v4di)(X), (__v4di)(Y), \
27 (__v4di)(Z)))
29 #define _mm_madd52lo_epu64(X, Y, Z) \
30 ((__m128i)__builtin_ia32_vpmadd52luq128((__v2di)(X), (__v2di)(Y), \
31 (__v2di)(Z)))
33 #define _mm256_madd52lo_epu64(X, Y, Z) \
34 ((__m256i)__builtin_ia32_vpmadd52luq256((__v4di)(X), (__v4di)(Y), \
35 (__v4di)(Z)))
37 static __inline__ __m128i __DEFAULT_FN_ATTRS128
38 _mm_mask_madd52hi_epu64 (__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y)
40 return (__m128i)__builtin_ia32_selectq_128(__M,
41 (__v2di)_mm_madd52hi_epu64(__W, __X, __Y),
42 (__v2di)__W);
45 static __inline__ __m128i __DEFAULT_FN_ATTRS128
46 _mm_maskz_madd52hi_epu64 (__mmask8 __M, __m128i __X, __m128i __Y, __m128i __Z)
48 return (__m128i)__builtin_ia32_selectq_128(__M,
49 (__v2di)_mm_madd52hi_epu64(__X, __Y, __Z),
50 (__v2di)_mm_setzero_si128());
53 static __inline__ __m256i __DEFAULT_FN_ATTRS256
54 _mm256_mask_madd52hi_epu64 (__m256i __W, __mmask8 __M, __m256i __X, __m256i __Y)
56 return (__m256i)__builtin_ia32_selectq_256(__M,
57 (__v4di)_mm256_madd52hi_epu64(__W, __X, __Y),
58 (__v4di)__W);
61 static __inline__ __m256i __DEFAULT_FN_ATTRS256
62 _mm256_maskz_madd52hi_epu64 (__mmask8 __M, __m256i __X, __m256i __Y, __m256i __Z)
64 return (__m256i)__builtin_ia32_selectq_256(__M,
65 (__v4di)_mm256_madd52hi_epu64(__X, __Y, __Z),
66 (__v4di)_mm256_setzero_si256());
69 static __inline__ __m128i __DEFAULT_FN_ATTRS128
70 _mm_mask_madd52lo_epu64 (__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y)
72 return (__m128i)__builtin_ia32_selectq_128(__M,
73 (__v2di)_mm_madd52lo_epu64(__W, __X, __Y),
74 (__v2di)__W);
77 static __inline__ __m128i __DEFAULT_FN_ATTRS128
78 _mm_maskz_madd52lo_epu64 (__mmask8 __M, __m128i __X, __m128i __Y, __m128i __Z)
80 return (__m128i)__builtin_ia32_selectq_128(__M,
81 (__v2di)_mm_madd52lo_epu64(__X, __Y, __Z),
82 (__v2di)_mm_setzero_si128());
85 static __inline__ __m256i __DEFAULT_FN_ATTRS256
86 _mm256_mask_madd52lo_epu64 (__m256i __W, __mmask8 __M, __m256i __X, __m256i __Y)
88 return (__m256i)__builtin_ia32_selectq_256(__M,
89 (__v4di)_mm256_madd52lo_epu64(__W, __X, __Y),
90 (__v4di)__W);
93 static __inline__ __m256i __DEFAULT_FN_ATTRS256
94 _mm256_maskz_madd52lo_epu64 (__mmask8 __M, __m256i __X, __m256i __Y, __m256i __Z)
96 return (__m256i)__builtin_ia32_selectq_256(__M,
97 (__v4di)_mm256_madd52lo_epu64(__X, __Y, __Z),
98 (__v4di)_mm256_setzero_si256());
102 #undef __DEFAULT_FN_ATTRS128
103 #undef __DEFAULT_FN_ATTRS256
105 #endif