[AMDGPU][AsmParser][NFC] Get rid of custom default operand handlers.
[llvm-project.git] / clang / lib / Headers / avx512vlvp2intersectintrin.h
blob3e0815e5d46ffc50611fe169fd1fd31582657dc8
1 /*===------ avx512vlvp2intersectintrin.h - VL VP2INTERSECT intrinsics ------===
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22 *===-----------------------------------------------------------------------===
24 #ifndef __IMMINTRIN_H
25 #error "Never use <avx512vlvp2intersectintrin.h> directly; include <immintrin.h> instead."
26 #endif
28 #ifndef _AVX512VLVP2INTERSECT_H
29 #define _AVX512VLVP2INTERSECT_H
31 #define __DEFAULT_FN_ATTRS128 \
32 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vp2intersect"), \
33 __min_vector_width__(128)))
35 #define __DEFAULT_FN_ATTRS256 \
36 __attribute__((__always_inline__, __nodebug__, __target__("avx512vl,avx512vp2intersect"), \
37 __min_vector_width__(256)))
38 /// Store, in an even/odd pair of mask registers, the indicators of the
39 /// locations of value matches between dwords in operands __a and __b.
40 ///
41 /// \headerfile <x86intrin.h>
42 ///
43 /// This intrinsic corresponds to the <c> VP2INTERSECTD </c> instruction.
44 ///
45 /// \param __a
46 /// A 256-bit vector of [8 x i32].
47 /// \param __b
48 /// A 256-bit vector of [8 x i32]
49 /// \param __m0
50 /// A pointer point to 8-bit mask
51 /// \param __m1
52 /// A pointer point to 8-bit mask
53 static __inline__ void __DEFAULT_FN_ATTRS256
54 _mm256_2intersect_epi32(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) {
55 __builtin_ia32_vp2intersect_d_256((__v8si)__a, (__v8si)__b, __m0, __m1);
58 /// Store, in an even/odd pair of mask registers, the indicators of the
59 /// locations of value matches between quadwords in operands __a and __b.
60 ///
61 /// \headerfile <x86intrin.h>
62 ///
63 /// This intrinsic corresponds to the <c> VP2INTERSECTQ </c> instruction.
64 ///
65 /// \param __a
66 /// A 256-bit vector of [4 x i64].
67 /// \param __b
68 /// A 256-bit vector of [4 x i64]
69 /// \param __m0
70 /// A pointer point to 8-bit mask
71 /// \param __m1
72 /// A pointer point to 8-bit mask
73 static __inline__ void __DEFAULT_FN_ATTRS256
74 _mm256_2intersect_epi64(__m256i __a, __m256i __b, __mmask8 *__m0, __mmask8 *__m1) {
75 __builtin_ia32_vp2intersect_q_256((__v4di)__a, (__v4di)__b, __m0, __m1);
78 /// Store, in an even/odd pair of mask registers, the indicators of the
79 /// locations of value matches between dwords in operands __a and __b.
80 ///
81 /// \headerfile <x86intrin.h>
82 ///
83 /// This intrinsic corresponds to the <c> VP2INTERSECTD </c> instruction.
84 ///
85 /// \param __a
86 /// A 128-bit vector of [4 x i32].
87 /// \param __b
88 /// A 128-bit vector of [4 x i32]
89 /// \param __m0
90 /// A pointer point to 8-bit mask
91 /// \param __m1
92 /// A pointer point to 8-bit mask
93 static __inline__ void __DEFAULT_FN_ATTRS128
94 _mm_2intersect_epi32(__m128i __a, __m128i __b, __mmask8 *__m0, __mmask8 *__m1) {
95 __builtin_ia32_vp2intersect_d_128((__v4si)__a, (__v4si)__b, __m0, __m1);
98 /// Store, in an even/odd pair of mask registers, the indicators of the
99 /// locations of value matches between quadwords in operands __a and __b.
101 /// \headerfile <x86intrin.h>
103 /// This intrinsic corresponds to the <c> VP2INTERSECTQ </c> instruction.
105 /// \param __a
106 /// A 128-bit vector of [2 x i64].
107 /// \param __b
108 /// A 128-bit vector of [2 x i64]
109 /// \param __m0
110 /// A pointer point to 8-bit mask
111 /// \param __m1
112 /// A pointer point to 8-bit mask
113 static __inline__ void __DEFAULT_FN_ATTRS128
114 _mm_2intersect_epi64(__m128i __a, __m128i __b, __mmask8 *__m0, __mmask8 *__m1) {
115 __builtin_ia32_vp2intersect_q_128((__v2di)__a, (__v2di)__b, __m0, __m1);
118 #undef __DEFAULT_FN_ATTRS128
119 #undef __DEFAULT_FN_ATTRS256
121 #endif