lldb/source/Utility/ARM64_ehframe_Registers.h

   1 //===-- ARM64_ehframe_Registers.h -------------------------------------*- C++
   2 //-*-===//
   3 //
   4 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
   5 // See https://llvm.org/LICENSE.txt for license information.
   6 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 #ifndef LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H
  11 #define LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H
  12
  13 // The register numbers used in the eh_frame unwind information.
  14 // Should be the same as DWARF register numbers.
  15
  16 namespace arm64_ehframe {
  17
  18 enum {
  19   x0 = 0,
  20   x1,
  21   x2,
  22   x3,
  23   x4,
  24   x5,
  25   x6,
  26   x7,
  27   x8,
  28   x9,
  29   x10,
  30   x11,
  31   x12,
  32   x13,
  33   x14,
  34   x15,
  35   x16,
  36   x17,
  37   x18,
  38   x19,
  39   x20,
  40   x21,
  41   x22,
  42   x23,
  43   x24,
  44   x25,
  45   x26,
  46   x27,
  47   x28,
  48   fp, // aka x29
  49   lr, // aka x30
  50   sp, // aka x31 aka wzr
  51   pc, // value is 32
  52   cpsr,
  53   // 34-45 reserved
  54
  55   // 64-bit SVE Vector granule pseudo register
  56   vg = 46,
  57
  58   // VG ́8-bit SVE first fault register
  59   ffr = 47,
  60
  61   // VG x ́8-bit SVE predicate registers
  62   p0 = 48,
  63   p1,
  64   p2,
  65   p3,
  66   p4,
  67   p5,
  68   p6,
  69   p7,
  70   p8,
  71   p9,
  72   p10,
  73   p11,
  74   p12,
  75   p13,
  76   p14,
  77   p15,
  78
  79   // V0-V31 (128 bit vector registers)
  80   v0 = 64,
  81   v1,
  82   v2,
  83   v3,
  84   v4,
  85   v5,
  86   v6,
  87   v7,
  88   v8,
  89   v9,
  90   v10,
  91   v11,
  92   v12,
  93   v13,
  94   v14,
  95   v15,
  96   v16,
  97   v17,
  98   v18,
  99   v19,
 100   v20,
 101   v21,
 102   v22,
 103   v23,
 104   v24,
 105   v25,
 106   v26,
 107   v27,
 108   v28,
 109   v29,
 110   v30,
 111   v31,
 112
 113   // VG ́64-bit SVE vector registers
 114   z0 = 96,
 115   z1,
 116   z2,
 117   z3,
 118   z4,
 119   z5,
 120   z6,
 121   z7,
 122   z8,
 123   z9,
 124   z10,
 125   z11,
 126   z12,
 127   z13,
 128   z14,
 129   z15,
 130   z16,
 131   z17,
 132   z18,
 133   z19,
 134   z20,
 135   z21,
 136   z22,
 137   z23,
 138   z24,
 139   z25,
 140   z26,
 141   z27,
 142   z28,
 143   z29,
 144   z30,
 145   z31
 146 };
 147 }
 148
 149 #endif // LLDB_SOURCE_UTILITY_ARM64_EHFRAME_REGISTERS_H