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[mlir][int-range] Limit xor int range inference to i1 (#116968)
[llvm-project.git] / lldb / source / Utility / ArchSpec.cpp
blob85bb85044ec156c94e49141d42b17604259bd4f0
1 //===-- ArchSpec.cpp ------------------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "lldb/Utility/ArchSpec.h"
10 #include "lldb/Utility/LLDBLog.h"
11
12 #include "lldb/Utility/Log.h"
13 #include "lldb/Utility/StringList.h"
14 #include "lldb/lldb-defines.h"
15 #include "llvm/ADT/STLExtras.h"
16 #include "llvm/BinaryFormat/COFF.h"
17 #include "llvm/BinaryFormat/ELF.h"
18 #include "llvm/BinaryFormat/MachO.h"
19 #include "llvm/BinaryFormat/XCOFF.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/TargetParser/ARMTargetParser.h"
22
23 using namespace lldb;
24 using namespace lldb_private;
25
26 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
27 bool try_inverse, bool enforce_exact_match);
28
29 namespace lldb_private {
30
31 struct CoreDefinition {
32 ByteOrder default_byte_order;
33 uint32_t addr_byte_size;
34 uint32_t min_opcode_byte_size;
35 uint32_t max_opcode_byte_size;
36 llvm::Triple::ArchType machine;
37 ArchSpec::Core core;
38 const char *const name;
39 };
40
41 } // namespace lldb_private
42
43 // This core information can be looked using the ArchSpec::Core as the index
44 static const CoreDefinition g_core_definitions[] = {
45 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_generic,
46 "arm"},
47 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4,
48 "armv4"},
49 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv4t,
50 "armv4t"},
51 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5,
52 "armv5"},
53 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5e,
54 "armv5e"},
55 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv5t,
56 "armv5t"},
57 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6,
58 "armv6"},
59 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv6m,
60 "armv6m"},
61 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7,
62 "armv7"},
63 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7a,
64 "armv7a"},
65 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7l,
66 "armv7l"},
67 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7f,
68 "armv7f"},
69 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7s,
70 "armv7s"},
71 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7k,
72 "armv7k"},
73 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7m,
74 "armv7m"},
75 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv7em,
76 "armv7em"},
77 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_xscale,
78 "xscale"},
79 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumb,
80 "thumb"},
81 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv4t,
82 "thumbv4t"},
83 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5,
84 "thumbv5"},
85 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv5e,
86 "thumbv5e"},
87 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6,
88 "thumbv6"},
89 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv6m,
90 "thumbv6m"},
91 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7,
92 "thumbv7"},
93 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7f,
94 "thumbv7f"},
95 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7s,
96 "thumbv7s"},
97 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7k,
98 "thumbv7k"},
99 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7m,
100 "thumbv7m"},
101 {eByteOrderLittle, 4, 2, 4, llvm::Triple::thumb, ArchSpec::eCore_thumbv7em,
102 "thumbv7em"},
103 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
104 ArchSpec::eCore_arm_arm64, "arm64"},
105 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
106 ArchSpec::eCore_arm_armv8, "armv8"},
107 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
108 ArchSpec::eCore_arm_armv8a, "armv8a"},
109 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arm, ArchSpec::eCore_arm_armv8l,
110 "armv8l"},
111 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
112 ArchSpec::eCore_arm_arm64e, "arm64e"},
113 {eByteOrderLittle, 4, 4, 4, llvm::Triple::aarch64_32,
114 ArchSpec::eCore_arm_arm64_32, "arm64_32"},
115 {eByteOrderLittle, 8, 4, 4, llvm::Triple::aarch64,
116 ArchSpec::eCore_arm_aarch64, "aarch64"},
117
118 // mips32, mips32r2, mips32r3, mips32r5, mips32r6
119 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32,
120 "mips"},
121 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r2,
122 "mipsr2"},
123 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r3,
124 "mipsr3"},
125 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r5,
126 "mipsr5"},
127 {eByteOrderBig, 4, 2, 4, llvm::Triple::mips, ArchSpec::eCore_mips32r6,
128 "mipsr6"},
129 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel, ArchSpec::eCore_mips32el,
130 "mipsel"},
131 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
132 ArchSpec::eCore_mips32r2el, "mipsr2el"},
133 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
134 ArchSpec::eCore_mips32r3el, "mipsr3el"},
135 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
136 ArchSpec::eCore_mips32r5el, "mipsr5el"},
137 {eByteOrderLittle, 4, 2, 4, llvm::Triple::mipsel,
138 ArchSpec::eCore_mips32r6el, "mipsr6el"},
139
140 // mips64, mips64r2, mips64r3, mips64r5, mips64r6
141 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64,
142 "mips64"},
143 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r2,
144 "mips64r2"},
145 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r3,
146 "mips64r3"},
147 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r5,
148 "mips64r5"},
149 {eByteOrderBig, 8, 2, 4, llvm::Triple::mips64, ArchSpec::eCore_mips64r6,
150 "mips64r6"},
151 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
152 ArchSpec::eCore_mips64el, "mips64el"},
153 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
154 ArchSpec::eCore_mips64r2el, "mips64r2el"},
155 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
156 ArchSpec::eCore_mips64r3el, "mips64r3el"},
157 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
158 ArchSpec::eCore_mips64r5el, "mips64r5el"},
159 {eByteOrderLittle, 8, 2, 4, llvm::Triple::mips64el,
160 ArchSpec::eCore_mips64r6el, "mips64r6el"},
161
162 // MSP430
163 {eByteOrderLittle, 2, 2, 4, llvm::Triple::msp430, ArchSpec::eCore_msp430,
164 "msp430"},
165
166 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_generic,
167 "powerpc"},
168 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc601,
169 "ppc601"},
170 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc602,
171 "ppc602"},
172 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603,
173 "ppc603"},
174 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603e,
175 "ppc603e"},
176 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc603ev,
177 "ppc603ev"},
178 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604,
179 "ppc604"},
180 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc604e,
181 "ppc604e"},
182 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc620,
183 "ppc620"},
184 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc750,
185 "ppc750"},
186 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7400,
187 "ppc7400"},
188 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc7450,
189 "ppc7450"},
190 {eByteOrderBig, 4, 4, 4, llvm::Triple::ppc, ArchSpec::eCore_ppc_ppc970,
191 "ppc970"},
192
193 {eByteOrderLittle, 8, 4, 4, llvm::Triple::ppc64le,
194 ArchSpec::eCore_ppc64le_generic, "powerpc64le"},
195 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64, ArchSpec::eCore_ppc64_generic,
196 "powerpc64"},
197 {eByteOrderBig, 8, 4, 4, llvm::Triple::ppc64,
198 ArchSpec::eCore_ppc64_ppc970_64, "ppc970-64"},
199
200 {eByteOrderBig, 8, 2, 6, llvm::Triple::systemz,
201 ArchSpec::eCore_s390x_generic, "s390x"},
202
203 {eByteOrderLittle, 4, 4, 4, llvm::Triple::sparc,
204 ArchSpec::eCore_sparc_generic, "sparc"},
205 {eByteOrderLittle, 8, 4, 4, llvm::Triple::sparcv9,
206 ArchSpec::eCore_sparc9_generic, "sparcv9"},
207
208 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i386,
209 "i386"},
210 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i486,
211 "i486"},
212 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86,
213 ArchSpec::eCore_x86_32_i486sx, "i486sx"},
214 {eByteOrderLittle, 4, 1, 15, llvm::Triple::x86, ArchSpec::eCore_x86_32_i686,
215 "i686"},
216
217 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
218 ArchSpec::eCore_x86_64_x86_64, "x86_64"},
219 {eByteOrderLittle, 8, 1, 15, llvm::Triple::x86_64,
220 ArchSpec::eCore_x86_64_x86_64h, "x86_64h"},
221 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
222 ArchSpec::eCore_hexagon_generic, "hexagon"},
223 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
224 ArchSpec::eCore_hexagon_hexagonv4, "hexagonv4"},
225 {eByteOrderLittle, 4, 4, 4, llvm::Triple::hexagon,
226 ArchSpec::eCore_hexagon_hexagonv5, "hexagonv5"},
227
228 {eByteOrderLittle, 4, 2, 4, llvm::Triple::riscv32, ArchSpec::eCore_riscv32,
229 "riscv32"},
230 {eByteOrderLittle, 8, 2, 4, llvm::Triple::riscv64, ArchSpec::eCore_riscv64,
231 "riscv64"},
232
233 {eByteOrderLittle, 4, 4, 4, llvm::Triple::loongarch32,
234 ArchSpec::eCore_loongarch32, "loongarch32"},
235 {eByteOrderLittle, 8, 4, 4, llvm::Triple::loongarch64,
236 ArchSpec::eCore_loongarch64, "loongarch64"},
237
238 {eByteOrderLittle, 4, 4, 4, llvm::Triple::UnknownArch,
239 ArchSpec::eCore_uknownMach32, "unknown-mach-32"},
240 {eByteOrderLittle, 8, 4, 4, llvm::Triple::UnknownArch,
241 ArchSpec::eCore_uknownMach64, "unknown-mach-64"},
242 {eByteOrderLittle, 4, 2, 4, llvm::Triple::arc, ArchSpec::eCore_arc, "arc"},
243
244 {eByteOrderLittle, 2, 2, 4, llvm::Triple::avr, ArchSpec::eCore_avr, "avr"},
245
246 {eByteOrderLittle, 4, 1, 4, llvm::Triple::wasm32, ArchSpec::eCore_wasm32,
247 "wasm32"},
248 };
249
250 // Ensure that we have an entry in the g_core_definitions for each core. If you
251 // comment out an entry above, you will need to comment out the corresponding
252 // ArchSpec::Core enumeration.
253 static_assert(sizeof(g_core_definitions) / sizeof(CoreDefinition) ==
254 ArchSpec::kNumCores,
255 "make sure we have one core definition for each core");
256
257 struct ArchDefinitionEntry {
258 ArchSpec::Core core;
259 uint32_t cpu;
260 uint32_t sub;
261 uint32_t cpu_mask;
262 uint32_t sub_mask;
263 };
264
265 struct ArchDefinition {
266 ArchitectureType type;
267 size_t num_entries;
268 const ArchDefinitionEntry *entries;
269 const char *name;
270 };
271
272 void ArchSpec::ListSupportedArchNames(StringList &list) {
273 for (const auto &def : g_core_definitions)
274 list.AppendString(def.name);
275 }
276
277 void ArchSpec::AutoComplete(CompletionRequest &request) {
278 for (const auto &def : g_core_definitions)
279 request.TryCompleteCurrentArg(def.name);
280 }
281
282 #define CPU_ANY (UINT32_MAX)
283
284 //===----------------------------------------------------------------------===//
285 // A table that gets searched linearly for matches. This table is used to
286 // convert cpu type and subtypes to architecture names, and to convert
287 // architecture names to cpu types and subtypes. The ordering is important and
288 // allows the precedence to be set when the table is built.
289 #define SUBTYPE_MASK 0x00FFFFFFu
290
291 // clang-format off
292 static const ArchDefinitionEntry g_macho_arch_entries[] = {
293 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, CPU_ANY, UINT32_MAX, UINT32_MAX},
294 {ArchSpec::eCore_arm_generic, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
295 {ArchSpec::eCore_arm_armv4, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
296 {ArchSpec::eCore_arm_armv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
297 {ArchSpec::eCore_arm_armv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
298 {ArchSpec::eCore_arm_armv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
299 {ArchSpec::eCore_arm_armv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
300 {ArchSpec::eCore_arm_armv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
301 {ArchSpec::eCore_arm_armv5t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5TEJ, UINT32_MAX, SUBTYPE_MASK},
302 {ArchSpec::eCore_arm_xscale, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_XSCALE, UINT32_MAX, SUBTYPE_MASK},
303 {ArchSpec::eCore_arm_armv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
304 {ArchSpec::eCore_arm_armv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
305 {ArchSpec::eCore_arm_armv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
306 {ArchSpec::eCore_arm_armv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
307 {ArchSpec::eCore_arm_armv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
308 {ArchSpec::eCore_arm_armv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
309 {ArchSpec::eCore_arm_arm64e, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64E, UINT32_MAX, SUBTYPE_MASK},
310 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_ALL, UINT32_MAX, SUBTYPE_MASK},
311 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, llvm::MachO::CPU_SUBTYPE_ARM64_V8, UINT32_MAX, SUBTYPE_MASK},
312 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, 13, UINT32_MAX, SUBTYPE_MASK},
313 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 0, UINT32_MAX, SUBTYPE_MASK},
314 {ArchSpec::eCore_arm_arm64_32, llvm::MachO::CPU_TYPE_ARM64_32, 1, UINT32_MAX, SUBTYPE_MASK},
315 {ArchSpec::eCore_arm_arm64, llvm::MachO::CPU_TYPE_ARM64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
316 {ArchSpec::eCore_thumb, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_ALL, UINT32_MAX, SUBTYPE_MASK},
317 {ArchSpec::eCore_thumbv4t, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V4T, UINT32_MAX, SUBTYPE_MASK},
318 {ArchSpec::eCore_thumbv5, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
319 {ArchSpec::eCore_thumbv5e, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V5, UINT32_MAX, SUBTYPE_MASK},
320 {ArchSpec::eCore_thumbv6, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6, UINT32_MAX, SUBTYPE_MASK},
321 {ArchSpec::eCore_thumbv6m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V6M, UINT32_MAX, SUBTYPE_MASK},
322 {ArchSpec::eCore_thumbv7, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7, UINT32_MAX, SUBTYPE_MASK},
323 {ArchSpec::eCore_thumbv7f, llvm::MachO::CPU_TYPE_ARM, 10, UINT32_MAX, SUBTYPE_MASK},
324 {ArchSpec::eCore_thumbv7s, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7S, UINT32_MAX, SUBTYPE_MASK},
325 {ArchSpec::eCore_thumbv7k, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7K, UINT32_MAX, SUBTYPE_MASK},
326 {ArchSpec::eCore_thumbv7m, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7M, UINT32_MAX, SUBTYPE_MASK},
327 {ArchSpec::eCore_thumbv7em, llvm::MachO::CPU_TYPE_ARM, llvm::MachO::CPU_SUBTYPE_ARM_V7EM, UINT32_MAX, SUBTYPE_MASK},
328 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, CPU_ANY, UINT32_MAX, UINT32_MAX},
329 {ArchSpec::eCore_ppc_generic, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
330 {ArchSpec::eCore_ppc_ppc601, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_601, UINT32_MAX, SUBTYPE_MASK},
331 {ArchSpec::eCore_ppc_ppc602, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_602, UINT32_MAX, SUBTYPE_MASK},
332 {ArchSpec::eCore_ppc_ppc603, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603, UINT32_MAX, SUBTYPE_MASK},
333 {ArchSpec::eCore_ppc_ppc603e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603e, UINT32_MAX, SUBTYPE_MASK},
334 {ArchSpec::eCore_ppc_ppc603ev, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_603ev, UINT32_MAX, SUBTYPE_MASK},
335 {ArchSpec::eCore_ppc_ppc604, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604, UINT32_MAX, SUBTYPE_MASK},
336 {ArchSpec::eCore_ppc_ppc604e, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_604e, UINT32_MAX, SUBTYPE_MASK},
337 {ArchSpec::eCore_ppc_ppc620, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_620, UINT32_MAX, SUBTYPE_MASK},
338 {ArchSpec::eCore_ppc_ppc750, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_750, UINT32_MAX, SUBTYPE_MASK},
339 {ArchSpec::eCore_ppc_ppc7400, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7400, UINT32_MAX, SUBTYPE_MASK},
340 {ArchSpec::eCore_ppc_ppc7450, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_7450, UINT32_MAX, SUBTYPE_MASK},
341 {ArchSpec::eCore_ppc_ppc970, llvm::MachO::CPU_TYPE_POWERPC, llvm::MachO::CPU_SUBTYPE_POWERPC_970, UINT32_MAX, SUBTYPE_MASK},
342 {ArchSpec::eCore_ppc64_generic, llvm::MachO::CPU_TYPE_POWERPC64, llvm::MachO::CPU_SUBTYPE_POWERPC_ALL, UINT32_MAX, SUBTYPE_MASK},
343 {ArchSpec::eCore_ppc64le_generic, llvm::MachO::CPU_TYPE_POWERPC64, CPU_ANY, UINT32_MAX, SUBTYPE_MASK},
344 {ArchSpec::eCore_ppc64_ppc970_64, llvm::MachO::CPU_TYPE_POWERPC64, 100, UINT32_MAX, SUBTYPE_MASK},
345 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_I386_ALL, UINT32_MAX, SUBTYPE_MASK},
346 {ArchSpec::eCore_x86_32_i486, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486, UINT32_MAX, SUBTYPE_MASK},
347 {ArchSpec::eCore_x86_32_i486sx, llvm::MachO::CPU_TYPE_I386, llvm::MachO::CPU_SUBTYPE_486SX, UINT32_MAX, SUBTYPE_MASK},
348 {ArchSpec::eCore_x86_32_i386, llvm::MachO::CPU_TYPE_I386, CPU_ANY, UINT32_MAX, UINT32_MAX},
349 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_ALL, UINT32_MAX, SUBTYPE_MASK},
350 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_ARCH1, UINT32_MAX, SUBTYPE_MASK},
351 {ArchSpec::eCore_x86_64_x86_64h, llvm::MachO::CPU_TYPE_X86_64, llvm::MachO::CPU_SUBTYPE_X86_64_H, UINT32_MAX, SUBTYPE_MASK},
352 {ArchSpec::eCore_x86_64_x86_64, llvm::MachO::CPU_TYPE_X86_64, CPU_ANY, UINT32_MAX, UINT32_MAX},
353 // Catch any unknown mach architectures so we can always use the object and symbol mach-o files
354 {ArchSpec::eCore_uknownMach32, 0, 0, 0xFF000000u, 0x00000000u},
355 {ArchSpec::eCore_uknownMach64, llvm::MachO::CPU_ARCH_ABI64, 0, 0xFF000000u, 0x00000000u}};
356 // clang-format on
357
358 static const ArchDefinition g_macho_arch_def = {eArchTypeMachO,
359 std::size(g_macho_arch_entries),
360 g_macho_arch_entries, "mach-o"};
361
362 //===----------------------------------------------------------------------===//
363 // A table that gets searched linearly for matches. This table is used to
364 // convert cpu type and subtypes to architecture names, and to convert
365 // architecture names to cpu types and subtypes. The ordering is important and
366 // allows the precedence to be set when the table is built.
367 static const ArchDefinitionEntry g_elf_arch_entries[] = {
368 {ArchSpec::eCore_sparc_generic, llvm::ELF::EM_SPARC, LLDB_INVALID_CPUTYPE,
369 0xFFFFFFFFu, 0xFFFFFFFFu}, // Sparc
370 {ArchSpec::eCore_x86_32_i386, llvm::ELF::EM_386, LLDB_INVALID_CPUTYPE,
371 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80386
372 {ArchSpec::eCore_x86_32_i486, llvm::ELF::EM_IAMCU, LLDB_INVALID_CPUTYPE,
373 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel MCU // FIXME: is this correct?
374 {ArchSpec::eCore_ppc_generic, llvm::ELF::EM_PPC, LLDB_INVALID_CPUTYPE,
375 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
376 {ArchSpec::eCore_ppc64le_generic, llvm::ELF::EM_PPC64,
377 ArchSpec::eCore_ppc64le_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64le
378 {ArchSpec::eCore_ppc64_generic, llvm::ELF::EM_PPC64,
379 ArchSpec::eCore_ppc64_generic, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC64
380 {ArchSpec::eCore_arm_generic, llvm::ELF::EM_ARM, LLDB_INVALID_CPUTYPE,
381 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
382 {ArchSpec::eCore_arm_aarch64, llvm::ELF::EM_AARCH64, LLDB_INVALID_CPUTYPE,
383 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM64
384 {ArchSpec::eCore_s390x_generic, llvm::ELF::EM_S390, LLDB_INVALID_CPUTYPE,
385 0xFFFFFFFFu, 0xFFFFFFFFu}, // SystemZ
386 {ArchSpec::eCore_sparc9_generic, llvm::ELF::EM_SPARCV9,
387 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // SPARC V9
388 {ArchSpec::eCore_x86_64_x86_64, llvm::ELF::EM_X86_64, LLDB_INVALID_CPUTYPE,
389 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
390 {ArchSpec::eCore_mips32, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips32,
391 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32
392 {ArchSpec::eCore_mips32r2, llvm::ELF::EM_MIPS,
393 ArchSpec::eMIPSSubType_mips32r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2
394 {ArchSpec::eCore_mips32r6, llvm::ELF::EM_MIPS,
395 ArchSpec::eMIPSSubType_mips32r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6
396 {ArchSpec::eCore_mips32el, llvm::ELF::EM_MIPS,
397 ArchSpec::eMIPSSubType_mips32el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32el
398 {ArchSpec::eCore_mips32r2el, llvm::ELF::EM_MIPS,
399 ArchSpec::eMIPSSubType_mips32r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r2el
400 {ArchSpec::eCore_mips32r6el, llvm::ELF::EM_MIPS,
401 ArchSpec::eMIPSSubType_mips32r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips32r6el
402 {ArchSpec::eCore_mips64, llvm::ELF::EM_MIPS, ArchSpec::eMIPSSubType_mips64,
403 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64
404 {ArchSpec::eCore_mips64r2, llvm::ELF::EM_MIPS,
405 ArchSpec::eMIPSSubType_mips64r2, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2
406 {ArchSpec::eCore_mips64r6, llvm::ELF::EM_MIPS,
407 ArchSpec::eMIPSSubType_mips64r6, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6
408 {ArchSpec::eCore_mips64el, llvm::ELF::EM_MIPS,
409 ArchSpec::eMIPSSubType_mips64el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64el
410 {ArchSpec::eCore_mips64r2el, llvm::ELF::EM_MIPS,
411 ArchSpec::eMIPSSubType_mips64r2el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r2el
412 {ArchSpec::eCore_mips64r6el, llvm::ELF::EM_MIPS,
413 ArchSpec::eMIPSSubType_mips64r6el, 0xFFFFFFFFu, 0xFFFFFFFFu}, // mips64r6el
414 {ArchSpec::eCore_msp430, llvm::ELF::EM_MSP430, LLDB_INVALID_CPUTYPE,
415 0xFFFFFFFFu, 0xFFFFFFFFu}, // MSP430
416 {ArchSpec::eCore_hexagon_generic, llvm::ELF::EM_HEXAGON,
417 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // HEXAGON
418 {ArchSpec::eCore_arc, llvm::ELF::EM_ARC_COMPACT2, LLDB_INVALID_CPUTYPE,
419 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARC
420 {ArchSpec::eCore_avr, llvm::ELF::EM_AVR, LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu,
421 0xFFFFFFFFu}, // AVR
422 {ArchSpec::eCore_riscv32, llvm::ELF::EM_RISCV,
423 ArchSpec::eRISCVSubType_riscv32, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv32
424 {ArchSpec::eCore_riscv64, llvm::ELF::EM_RISCV,
425 ArchSpec::eRISCVSubType_riscv64, 0xFFFFFFFFu, 0xFFFFFFFFu}, // riscv64
426 {ArchSpec::eCore_loongarch32, llvm::ELF::EM_LOONGARCH,
427 ArchSpec::eLoongArchSubType_loongarch32, 0xFFFFFFFFu,
428 0xFFFFFFFFu}, // loongarch32
429 {ArchSpec::eCore_loongarch64, llvm::ELF::EM_LOONGARCH,
430 ArchSpec::eLoongArchSubType_loongarch64, 0xFFFFFFFFu,
431 0xFFFFFFFFu}, // loongarch64
432 };
433
434 static const ArchDefinition g_elf_arch_def = {
435 eArchTypeELF,
436 std::size(g_elf_arch_entries),
437 g_elf_arch_entries,
438 "elf",
439 };
440
441 static const ArchDefinitionEntry g_coff_arch_entries[] = {
442 {ArchSpec::eCore_x86_32_i386, llvm::COFF::IMAGE_FILE_MACHINE_I386,
443 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // Intel 80x86
444 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPC,
445 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC
446 {ArchSpec::eCore_ppc_generic, llvm::COFF::IMAGE_FILE_MACHINE_POWERPCFP,
447 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // PowerPC (with FPU)
448 {ArchSpec::eCore_arm_generic, llvm::COFF::IMAGE_FILE_MACHINE_ARM,
449 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARM
450 {ArchSpec::eCore_arm_armv7, llvm::COFF::IMAGE_FILE_MACHINE_ARMNT,
451 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
452 {ArchSpec::eCore_thumb, llvm::COFF::IMAGE_FILE_MACHINE_THUMB,
453 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // ARMv7
454 {ArchSpec::eCore_x86_64_x86_64, llvm::COFF::IMAGE_FILE_MACHINE_AMD64,
455 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}, // AMD64
456 {ArchSpec::eCore_arm_arm64, llvm::COFF::IMAGE_FILE_MACHINE_ARM64,
457 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu} // ARM64
458 };
459
460 static const ArchDefinition g_coff_arch_def = {
461 eArchTypeCOFF,
462 std::size(g_coff_arch_entries),
463 g_coff_arch_entries,
464 "pe-coff",
465 };
466
467 static const ArchDefinitionEntry g_xcoff_arch_entries[] = {
468 {ArchSpec::eCore_ppc_generic, llvm::XCOFF::TCPU_COM, LLDB_INVALID_CPUTYPE,
469 0xFFFFFFFFu, 0xFFFFFFFFu},
470 {ArchSpec::eCore_ppc64_generic, llvm::XCOFF::TCPU_PPC64,
471 LLDB_INVALID_CPUTYPE, 0xFFFFFFFFu, 0xFFFFFFFFu}};
472
473 static const ArchDefinition g_xcoff_arch_def = {
474 eArchTypeXCOFF,
475 std::size(g_xcoff_arch_entries),
476 g_xcoff_arch_entries,
477 "xcoff",
478 };
479
480 //===----------------------------------------------------------------------===//
481 // Table of all ArchDefinitions
482 static const ArchDefinition *g_arch_definitions[] = {
483 &g_macho_arch_def, &g_elf_arch_def, &g_coff_arch_def, &g_xcoff_arch_def};
484
485 //===----------------------------------------------------------------------===//
486 // Static helper functions.
487
488 // Get the architecture definition for a given object type.
489 static const ArchDefinition *FindArchDefinition(ArchitectureType arch_type) {
490 for (const ArchDefinition *def : g_arch_definitions) {
491 if (def->type == arch_type)
492 return def;
493 }
494 return nullptr;
495 }
496
497 // Get an architecture definition by name.
498 static const CoreDefinition *FindCoreDefinition(llvm::StringRef name) {
499 for (const auto &def : g_core_definitions) {
500 if (name.equals_insensitive(def.name))
501 return &def;
502 }
503 return nullptr;
504 }
505
506 static inline const CoreDefinition *FindCoreDefinition(ArchSpec::Core core) {
507 if (core < std::size(g_core_definitions))
508 return &g_core_definitions[core];
509 return nullptr;
510 }
511
512 // Get a definition entry by cpu type and subtype.
513 static const ArchDefinitionEntry *
514 FindArchDefinitionEntry(const ArchDefinition *def, uint32_t cpu, uint32_t sub) {
515 if (def == nullptr)
516 return nullptr;
517
518 const ArchDefinitionEntry *entries = def->entries;
519 for (size_t i = 0; i < def->num_entries; ++i) {
520 if (entries[i].cpu == (cpu & entries[i].cpu_mask))
521 if (entries[i].sub == (sub & entries[i].sub_mask))
522 return &entries[i];
523 }
524 return nullptr;
525 }
526
527 static const ArchDefinitionEntry *
528 FindArchDefinitionEntry(const ArchDefinition *def, ArchSpec::Core core) {
529 if (def == nullptr)
530 return nullptr;
531
532 const ArchDefinitionEntry *entries = def->entries;
533 for (size_t i = 0; i < def->num_entries; ++i) {
534 if (entries[i].core == core)
535 return &entries[i];
536 }
537 return nullptr;
538 }
539
540 //===----------------------------------------------------------------------===//
541 // Constructors and destructors.
542
543 ArchSpec::ArchSpec() = default;
544
545 ArchSpec::ArchSpec(const char *triple_cstr) {
546 if (triple_cstr)
547 SetTriple(triple_cstr);
548 }
549
550 ArchSpec::ArchSpec(llvm::StringRef triple_str) { SetTriple(triple_str); }
551
552 ArchSpec::ArchSpec(const llvm::Triple &triple) { SetTriple(triple); }
553
554 ArchSpec::ArchSpec(ArchitectureType arch_type, uint32_t cpu, uint32_t subtype) {
555 SetArchitecture(arch_type, cpu, subtype);
556 }
557
558 ArchSpec::~ArchSpec() = default;
559
560 void ArchSpec::Clear() {
561 m_triple = llvm::Triple();
562 m_core = kCore_invalid;
563 m_byte_order = eByteOrderInvalid;
564 m_flags = 0;
565 }
566
567 //===----------------------------------------------------------------------===//
568 // Predicates.
569
570 const char *ArchSpec::GetArchitectureName() const {
571 const CoreDefinition *core_def = FindCoreDefinition(m_core);
572 if (core_def)
573 return core_def->name;
574 return "unknown";
575 }
576
577 bool ArchSpec::IsMIPS() const { return GetTriple().isMIPS(); }
578
579 std::string ArchSpec::GetTargetABI() const {
580
581 std::string abi;
582
583 if (IsMIPS()) {
584 switch (GetFlags() & ArchSpec::eMIPSABI_mask) {
585 case ArchSpec::eMIPSABI_N64:
586 abi = "n64";
587 return abi;
588 case ArchSpec::eMIPSABI_N32:
589 abi = "n32";
590 return abi;
591 case ArchSpec::eMIPSABI_O32:
592 abi = "o32";
593 return abi;
594 default:
595 return abi;
596 }
597 }
598 return abi;
599 }
600
601 void ArchSpec::SetFlags(const std::string &elf_abi) {
602
603 uint32_t flag = GetFlags();
604 if (IsMIPS()) {
605 if (elf_abi == "n64")
606 flag |= ArchSpec::eMIPSABI_N64;
607 else if (elf_abi == "n32")
608 flag |= ArchSpec::eMIPSABI_N32;
609 else if (elf_abi == "o32")
610 flag |= ArchSpec::eMIPSABI_O32;
611 }
612 SetFlags(flag);
613 }
614
615 std::string ArchSpec::GetClangTargetCPU() const {
616 std::string cpu;
617 if (IsMIPS()) {
618 switch (m_core) {
619 case ArchSpec::eCore_mips32:
620 case ArchSpec::eCore_mips32el:
621 cpu = "mips32";
622 break;
623 case ArchSpec::eCore_mips32r2:
624 case ArchSpec::eCore_mips32r2el:
625 cpu = "mips32r2";
626 break;
627 case ArchSpec::eCore_mips32r3:
628 case ArchSpec::eCore_mips32r3el:
629 cpu = "mips32r3";
630 break;
631 case ArchSpec::eCore_mips32r5:
632 case ArchSpec::eCore_mips32r5el:
633 cpu = "mips32r5";
634 break;
635 case ArchSpec::eCore_mips32r6:
636 case ArchSpec::eCore_mips32r6el:
637 cpu = "mips32r6";
638 break;
639 case ArchSpec::eCore_mips64:
640 case ArchSpec::eCore_mips64el:
641 cpu = "mips64";
642 break;
643 case ArchSpec::eCore_mips64r2:
644 case ArchSpec::eCore_mips64r2el:
645 cpu = "mips64r2";
646 break;
647 case ArchSpec::eCore_mips64r3:
648 case ArchSpec::eCore_mips64r3el:
649 cpu = "mips64r3";
650 break;
651 case ArchSpec::eCore_mips64r5:
652 case ArchSpec::eCore_mips64r5el:
653 cpu = "mips64r5";
654 break;
655 case ArchSpec::eCore_mips64r6:
656 case ArchSpec::eCore_mips64r6el:
657 cpu = "mips64r6";
658 break;
659 default:
660 break;
661 }
662 }
663
664 if (GetTriple().isARM())
665 cpu = llvm::ARM::getARMCPUForArch(GetTriple(), "").str();
666 return cpu;
667 }
668
669 uint32_t ArchSpec::GetMachOCPUType() const {
670 const CoreDefinition *core_def = FindCoreDefinition(m_core);
671 if (core_def) {
672 const ArchDefinitionEntry *arch_def =
673 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
674 if (arch_def) {
675 return arch_def->cpu;
676 }
677 }
678 return LLDB_INVALID_CPUTYPE;
679 }
680
681 uint32_t ArchSpec::GetMachOCPUSubType() const {
682 const CoreDefinition *core_def = FindCoreDefinition(m_core);
683 if (core_def) {
684 const ArchDefinitionEntry *arch_def =
685 FindArchDefinitionEntry(&g_macho_arch_def, core_def->core);
686 if (arch_def) {
687 return arch_def->sub;
688 }
689 }
690 return LLDB_INVALID_CPUTYPE;
691 }
692
693 uint32_t ArchSpec::GetDataByteSize() const {
694 return 1;
695 }
696
697 uint32_t ArchSpec::GetCodeByteSize() const {
698 return 1;
699 }
700
701 llvm::Triple::ArchType ArchSpec::GetMachine() const {
702 const CoreDefinition *core_def = FindCoreDefinition(m_core);
703 if (core_def)
704 return core_def->machine;
705
706 return llvm::Triple::UnknownArch;
707 }
708
709 uint32_t ArchSpec::GetAddressByteSize() const {
710 const CoreDefinition *core_def = FindCoreDefinition(m_core);
711 if (core_def) {
712 if (core_def->machine == llvm::Triple::mips64 ||
713 core_def->machine == llvm::Triple::mips64el) {
714 // For N32/O32 applications Address size is 4 bytes.
715 if (m_flags & (eMIPSABI_N32 | eMIPSABI_O32))
716 return 4;
717 }
718 return core_def->addr_byte_size;
719 }
720 return 0;
721 }
722
723 ByteOrder ArchSpec::GetDefaultEndian() const {
724 const CoreDefinition *core_def = FindCoreDefinition(m_core);
725 if (core_def)
726 return core_def->default_byte_order;
727 return eByteOrderInvalid;
728 }
729
730 bool ArchSpec::CharIsSignedByDefault() const {
731 switch (m_triple.getArch()) {
732 default:
733 return true;
734
735 case llvm::Triple::aarch64:
736 case llvm::Triple::aarch64_32:
737 case llvm::Triple::aarch64_be:
738 case llvm::Triple::arm:
739 case llvm::Triple::armeb:
740 case llvm::Triple::thumb:
741 case llvm::Triple::thumbeb:
742 return m_triple.isOSDarwin() || m_triple.isOSWindows();
743
744 case llvm::Triple::ppc:
745 case llvm::Triple::ppc64:
746 return m_triple.isOSDarwin();
747
748 case llvm::Triple::ppc64le:
749 case llvm::Triple::systemz:
750 case llvm::Triple::xcore:
751 case llvm::Triple::arc:
752 return false;
753 }
754 }
755
756 lldb::ByteOrder ArchSpec::GetByteOrder() const {
757 if (m_byte_order == eByteOrderInvalid)
758 return GetDefaultEndian();
759 return m_byte_order;
760 }
761
762 //===----------------------------------------------------------------------===//
763 // Mutators.
764
765 bool ArchSpec::SetTriple(const llvm::Triple &triple) {
766 m_triple = triple;
767 UpdateCore();
768 return IsValid();
769 }
770
771 bool lldb_private::ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str,
772 ArchSpec &arch) {
773 // Accept "12-10" or "12.10" as cpu type/subtype
774 if (triple_str.empty())
775 return false;
776
777 size_t pos = triple_str.find_first_of("-.");
778 if (pos == llvm::StringRef::npos)
779 return false;
780
781 llvm::StringRef cpu_str = triple_str.substr(0, pos);
782 llvm::StringRef remainder = triple_str.substr(pos + 1);
783 if (cpu_str.empty() || remainder.empty())
784 return false;
785
786 llvm::StringRef sub_str;
787 llvm::StringRef vendor;
788 llvm::StringRef os;
789 std::tie(sub_str, remainder) = remainder.split('-');
790 std::tie(vendor, os) = remainder.split('-');
791
792 uint32_t cpu = 0;
793 uint32_t sub = 0;
794 if (cpu_str.getAsInteger(10, cpu) || sub_str.getAsInteger(10, sub))
795 return false;
796
797 if (!arch.SetArchitecture(eArchTypeMachO, cpu, sub))
798 return false;
799 if (!vendor.empty() && !os.empty()) {
800 arch.GetTriple().setVendorName(vendor);
801 arch.GetTriple().setOSName(os);
802 }
803
804 return true;
805 }
806
807 bool ArchSpec::SetTriple(llvm::StringRef triple) {
808 if (triple.empty()) {
809 Clear();
810 return false;
811 }
812
813 if (ParseMachCPUDashSubtypeTriple(triple, *this))
814 return true;
815
816 SetTriple(llvm::Triple(llvm::Triple::normalize(triple)));
817 return IsValid();
818 }
819
820 bool ArchSpec::ContainsOnlyArch(const llvm::Triple &normalized_triple) {
821 return !normalized_triple.getArchName().empty() &&
822 normalized_triple.getOSName().empty() &&
823 normalized_triple.getVendorName().empty() &&
824 normalized_triple.getEnvironmentName().empty();
825 }
826
827 void ArchSpec::MergeFrom(const ArchSpec &other) {
828 // ios-macabi always wins over macosx.
829 if ((GetTriple().getOS() == llvm::Triple::MacOSX ||
830 GetTriple().getOS() == llvm::Triple::UnknownOS) &&
831 other.GetTriple().getOS() == llvm::Triple::IOS &&
832 other.GetTriple().getEnvironment() == llvm::Triple::MacABI) {
833 (*this) = other;
834 return;
835 }
836
837 if (!TripleVendorWasSpecified() && other.TripleVendorWasSpecified())
838 GetTriple().setVendor(other.GetTriple().getVendor());
839 if (!TripleOSWasSpecified() && other.TripleOSWasSpecified())
840 GetTriple().setOS(other.GetTriple().getOS());
841 if (GetTriple().getArch() == llvm::Triple::UnknownArch) {
842 GetTriple().setArch(other.GetTriple().getArch());
843
844 // MachO unknown64 isn't really invalid as the debugger can still obtain
845 // information from the binary, e.g. line tables. As such, we don't update
846 // the core here.
847 if (other.GetCore() != eCore_uknownMach64)
848 UpdateCore();
849 }
850 if (!TripleEnvironmentWasSpecified() &&
851 other.TripleEnvironmentWasSpecified()) {
852 GetTriple().setEnvironment(other.GetTriple().getEnvironment());
853 }
854 // If this and other are both arm ArchSpecs and this ArchSpec is a generic
855 // "some kind of arm" spec but the other ArchSpec is a specific arm core,
856 // adopt the specific arm core.
857 if (GetTriple().getArch() == llvm::Triple::arm &&
858 other.GetTriple().getArch() == llvm::Triple::arm &&
859 IsCompatibleMatch(other) && GetCore() == ArchSpec::eCore_arm_generic &&
860 other.GetCore() != ArchSpec::eCore_arm_generic) {
861 m_core = other.GetCore();
862 CoreUpdated(false);
863 }
864 if (GetFlags() == 0) {
865 SetFlags(other.GetFlags());
866 }
867 }
868
869 bool ArchSpec::SetArchitecture(ArchitectureType arch_type, uint32_t cpu,
870 uint32_t sub, uint32_t os) {
871 m_core = kCore_invalid;
872 bool update_triple = true;
873 const ArchDefinition *arch_def = FindArchDefinition(arch_type);
874 if (arch_def) {
875 const ArchDefinitionEntry *arch_def_entry =
876 FindArchDefinitionEntry(arch_def, cpu, sub);
877 if (arch_def_entry) {
878 const CoreDefinition *core_def = FindCoreDefinition(arch_def_entry->core);
879 if (core_def) {
880 m_core = core_def->core;
881 update_triple = false;
882 // Always use the architecture name because it might be more
883 // descriptive than the architecture enum ("armv7" ->
884 // llvm::Triple::arm).
885 m_triple.setArchName(llvm::StringRef(core_def->name));
886 if (arch_type == eArchTypeMachO) {
887 m_triple.setVendor(llvm::Triple::Apple);
888
889 // Don't set the OS. It could be simulator, macosx, ios, watchos,
890 // tvos, bridgeos. We could get close with the cpu type - but we
891 // can't get it right all of the time. Better to leave this unset
892 // so other sections of code will set it when they have more
893 // information. NB: don't call m_triple.setOS
894 // (llvm::Triple::UnknownOS). That sets the OSName to "unknown" and
895 // the ArchSpec::TripleVendorWasSpecified() method says that any
896 // OSName setting means it was specified.
897 } else if (arch_type == eArchTypeELF) {
898 switch (os) {
899 case llvm::ELF::ELFOSABI_AIX:
900 m_triple.setOS(llvm::Triple::OSType::AIX);
901 break;
902 case llvm::ELF::ELFOSABI_FREEBSD:
903 m_triple.setOS(llvm::Triple::OSType::FreeBSD);
904 break;
905 case llvm::ELF::ELFOSABI_GNU:
906 m_triple.setOS(llvm::Triple::OSType::Linux);
907 break;
908 case llvm::ELF::ELFOSABI_NETBSD:
909 m_triple.setOS(llvm::Triple::OSType::NetBSD);
910 break;
911 case llvm::ELF::ELFOSABI_OPENBSD:
912 m_triple.setOS(llvm::Triple::OSType::OpenBSD);
913 break;
914 case llvm::ELF::ELFOSABI_SOLARIS:
915 m_triple.setOS(llvm::Triple::OSType::Solaris);
916 break;
917 case llvm::ELF::ELFOSABI_STANDALONE:
918 m_triple.setOS(llvm::Triple::OSType::UnknownOS);
919 break;
920 }
921 } else if (arch_type == eArchTypeCOFF && os == llvm::Triple::Win32) {
922 m_triple.setVendor(llvm::Triple::PC);
923 m_triple.setOS(llvm::Triple::Win32);
924 } else if (arch_type == eArchTypeXCOFF && os == llvm::Triple::AIX) {
925 m_triple.setVendor(llvm::Triple::IBM);
926 m_triple.setOS(llvm::Triple::AIX);
927 } else {
928 m_triple.setVendor(llvm::Triple::UnknownVendor);
929 m_triple.setOS(llvm::Triple::UnknownOS);
930 }
931 // Fall back onto setting the machine type if the arch by name
932 // failed...
933 if (m_triple.getArch() == llvm::Triple::UnknownArch)
934 m_triple.setArch(core_def->machine);
935 }
936 } else {
937 Log *log(GetLog(LLDBLog::Target | LLDBLog::Process | LLDBLog::Platform));
938 LLDB_LOGF(log,
939 "Unable to find a core definition for cpu 0x%" PRIx32
940 " sub %" PRId32,
941 cpu, sub);
942 }
943 }
944 CoreUpdated(update_triple);
945 return IsValid();
946 }
947
948 uint32_t ArchSpec::GetMinimumOpcodeByteSize() const {
949 const CoreDefinition *core_def = FindCoreDefinition(m_core);
950 if (core_def)
951 return core_def->min_opcode_byte_size;
952 return 0;
953 }
954
955 uint32_t ArchSpec::GetMaximumOpcodeByteSize() const {
956 const CoreDefinition *core_def = FindCoreDefinition(m_core);
957 if (core_def)
958 return core_def->max_opcode_byte_size;
959 return 0;
960 }
961
962 static bool IsCompatibleEnvironment(llvm::Triple::EnvironmentType lhs,
963 llvm::Triple::EnvironmentType rhs) {
964 if (lhs == rhs)
965 return true;
966
967 // Apple simulators are a different platform than what they simulate.
968 // As the environments are different at this point, if one of them is a
969 // simulator, then they are different.
970 if (lhs == llvm::Triple::Simulator || rhs == llvm::Triple::Simulator)
971 return false;
972
973 // If any of the environment is unknown then they are compatible
974 if (lhs == llvm::Triple::UnknownEnvironment ||
975 rhs == llvm::Triple::UnknownEnvironment)
976 return true;
977
978 // If one of the environment is Android and the other one is EABI then they
979 // are considered to be compatible. This is required as a workaround for
980 // shared libraries compiled for Android without the NOTE section indicating
981 // that they are using the Android ABI.
982 if ((lhs == llvm::Triple::Android && rhs == llvm::Triple::EABI) ||
983 (rhs == llvm::Triple::Android && lhs == llvm::Triple::EABI) ||
984 (lhs == llvm::Triple::GNUEABI && rhs == llvm::Triple::EABI) ||
985 (rhs == llvm::Triple::GNUEABI && lhs == llvm::Triple::EABI) ||
986 (lhs == llvm::Triple::GNUEABIHF && rhs == llvm::Triple::EABIHF) ||
987 (rhs == llvm::Triple::GNUEABIHF && lhs == llvm::Triple::EABIHF))
988 return true;
989
990 return false;
991 }
992
993 bool ArchSpec::IsMatch(const ArchSpec &rhs, MatchType match) const {
994 if (GetByteOrder() != rhs.GetByteOrder() ||
995 !cores_match(GetCore(), rhs.GetCore(), true, match == ExactMatch))
996 return false;
997
998 const llvm::Triple &lhs_triple = GetTriple();
999 const llvm::Triple &rhs_triple = rhs.GetTriple();
1000
1001 const llvm::Triple::VendorType lhs_triple_vendor = lhs_triple.getVendor();
1002 const llvm::Triple::VendorType rhs_triple_vendor = rhs_triple.getVendor();
1003
1004 const llvm::Triple::OSType lhs_triple_os = lhs_triple.getOS();
1005 const llvm::Triple::OSType rhs_triple_os = rhs_triple.getOS();
1006
1007 bool both_windows = lhs_triple.isOSWindows() && rhs_triple.isOSWindows();
1008
1009 // On Windows, the vendor field doesn't have any practical effect, but
1010 // it is often set to either "pc" or "w64".
1011 if ((lhs_triple_vendor != rhs_triple_vendor) &&
1012 (match == ExactMatch || !both_windows)) {
1013 const bool rhs_vendor_specified = rhs.TripleVendorWasSpecified();
1014 const bool lhs_vendor_specified = TripleVendorWasSpecified();
1015 // Both architectures had the vendor specified, so if they aren't equal
1016 // then we return false
1017 if (rhs_vendor_specified && lhs_vendor_specified)
1018 return false;
1019
1020 // Only fail if both vendor types are not unknown
1021 if (lhs_triple_vendor != llvm::Triple::UnknownVendor &&
1022 rhs_triple_vendor != llvm::Triple::UnknownVendor)
1023 return false;
1024 }
1025
1026 const llvm::Triple::EnvironmentType lhs_triple_env =
1027 lhs_triple.getEnvironment();
1028 const llvm::Triple::EnvironmentType rhs_triple_env =
1029 rhs_triple.getEnvironment();
1030
1031 if (match == CompatibleMatch) {
1032 // x86_64-apple-ios-macabi, x86_64-apple-macosx are compatible, no match.
1033 if ((lhs_triple_os == llvm::Triple::IOS &&
1034 lhs_triple_env == llvm::Triple::MacABI &&
1035 rhs_triple_os == llvm::Triple::MacOSX) ||
1036 (lhs_triple_os == llvm::Triple::MacOSX &&
1037 rhs_triple_os == llvm::Triple::IOS &&
1038 rhs_triple_env == llvm::Triple::MacABI))
1039 return true;
1040 }
1041
1042 // x86_64-apple-ios-macabi and x86_64-apple-ios are not compatible.
1043 if (lhs_triple_os == llvm::Triple::IOS &&
1044 rhs_triple_os == llvm::Triple::IOS &&
1045 (lhs_triple_env == llvm::Triple::MacABI ||
1046 rhs_triple_env == llvm::Triple::MacABI) &&
1047 lhs_triple_env != rhs_triple_env)
1048 return false;
1049
1050 if (lhs_triple_os != rhs_triple_os) {
1051 const bool lhs_os_specified = TripleOSWasSpecified();
1052 const bool rhs_os_specified = rhs.TripleOSWasSpecified();
1053 // If both OS types are specified and different, fail.
1054 if (lhs_os_specified && rhs_os_specified)
1055 return false;
1056
1057 // If the pair of os+env is both unspecified, match any other os+env combo.
1058 if (match == CompatibleMatch &&
1059 ((!lhs_os_specified && !lhs_triple.hasEnvironment()) ||
1060 (!rhs_os_specified && !rhs_triple.hasEnvironment())))
1061 return true;
1062 }
1063
1064 if (match == CompatibleMatch && both_windows)
1065 return true; // The Windows environments (MSVC vs GNU) are compatible
1066
1067 return IsCompatibleEnvironment(lhs_triple_env, rhs_triple_env);
1068 }
1069
1070 void ArchSpec::UpdateCore() {
1071 llvm::StringRef arch_name(m_triple.getArchName());
1072 const CoreDefinition *core_def = FindCoreDefinition(arch_name);
1073 if (core_def) {
1074 m_core = core_def->core;
1075 // Set the byte order to the default byte order for an architecture. This
1076 // can be modified if needed for cases when cores handle both big and
1077 // little endian
1078 m_byte_order = core_def->default_byte_order;
1079 } else {
1080 Clear();
1081 }
1082 }
1083
1084 //===----------------------------------------------------------------------===//
1085 // Helper methods.
1086
1087 void ArchSpec::CoreUpdated(bool update_triple) {
1088 const CoreDefinition *core_def = FindCoreDefinition(m_core);
1089 if (core_def) {
1090 if (update_triple)
1091 m_triple = llvm::Triple(core_def->name, "unknown", "unknown");
1092 m_byte_order = core_def->default_byte_order;
1093 } else {
1094 if (update_triple)
1095 m_triple = llvm::Triple();
1096 m_byte_order = eByteOrderInvalid;
1097 }
1098 }
1099
1100 //===----------------------------------------------------------------------===//
1101 // Operators.
1102
1103 static bool cores_match(const ArchSpec::Core core1, const ArchSpec::Core core2,
1104 bool try_inverse, bool enforce_exact_match) {
1105 if (core1 == core2)
1106 return true;
1107
1108 switch (core1) {
1109 case ArchSpec::kCore_any:
1110 return true;
1111
1112 case ArchSpec::eCore_arm_generic:
1113 if (enforce_exact_match)
1114 break;
1115 [[fallthrough]];
1116 case ArchSpec::kCore_arm_any:
1117 if (core2 >= ArchSpec::kCore_arm_first && core2 <= ArchSpec::kCore_arm_last)
1118 return true;
1119 if (core2 >= ArchSpec::kCore_thumb_first &&
1120 core2 <= ArchSpec::kCore_thumb_last)
1121 return true;
1122 if (core2 == ArchSpec::kCore_arm_any)
1123 return true;
1124 break;
1125
1126 case ArchSpec::kCore_x86_32_any:
1127 if ((core2 >= ArchSpec::kCore_x86_32_first &&
1128 core2 <= ArchSpec::kCore_x86_32_last) ||
1129 (core2 == ArchSpec::kCore_x86_32_any))
1130 return true;
1131 break;
1132
1133 case ArchSpec::kCore_x86_64_any:
1134 if ((core2 >= ArchSpec::kCore_x86_64_first &&
1135 core2 <= ArchSpec::kCore_x86_64_last) ||
1136 (core2 == ArchSpec::kCore_x86_64_any))
1137 return true;
1138 break;
1139
1140 case ArchSpec::kCore_ppc_any:
1141 if ((core2 >= ArchSpec::kCore_ppc_first &&
1142 core2 <= ArchSpec::kCore_ppc_last) ||
1143 (core2 == ArchSpec::kCore_ppc_any))
1144 return true;
1145 break;
1146
1147 case ArchSpec::kCore_ppc64_any:
1148 if ((core2 >= ArchSpec::kCore_ppc64_first &&
1149 core2 <= ArchSpec::kCore_ppc64_last) ||
1150 (core2 == ArchSpec::kCore_ppc64_any))
1151 return true;
1152 break;
1153
1154 case ArchSpec::kCore_hexagon_any:
1155 if ((core2 >= ArchSpec::kCore_hexagon_first &&
1156 core2 <= ArchSpec::kCore_hexagon_last) ||
1157 (core2 == ArchSpec::kCore_hexagon_any))
1158 return true;
1159 break;
1160
1161 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1162 // Cortex-M0 - ARMv6-M - armv6m
1163 // Cortex-M3 - ARMv7-M - armv7m
1164 // Cortex-M4 - ARMv7E-M - armv7em
1165 case ArchSpec::eCore_arm_armv7em:
1166 if (!enforce_exact_match) {
1167 if (core2 == ArchSpec::eCore_arm_generic)
1168 return true;
1169 if (core2 == ArchSpec::eCore_arm_armv7m)
1170 return true;
1171 if (core2 == ArchSpec::eCore_arm_armv6m)
1172 return true;
1173 if (core2 == ArchSpec::eCore_arm_armv7)
1174 return true;
1175 try_inverse = true;
1176 }
1177 break;
1178
1179 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1180 // Cortex-M0 - ARMv6-M - armv6m
1181 // Cortex-M3 - ARMv7-M - armv7m
1182 // Cortex-M4 - ARMv7E-M - armv7em
1183 case ArchSpec::eCore_arm_armv7m:
1184 if (!enforce_exact_match) {
1185 if (core2 == ArchSpec::eCore_arm_generic)
1186 return true;
1187 if (core2 == ArchSpec::eCore_arm_armv6m)
1188 return true;
1189 if (core2 == ArchSpec::eCore_arm_armv7)
1190 return true;
1191 if (core2 == ArchSpec::eCore_arm_armv7em)
1192 return true;
1193 try_inverse = true;
1194 }
1195 break;
1196
1197 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M#Silicon_customization
1198 // Cortex-M0 - ARMv6-M - armv6m
1199 // Cortex-M3 - ARMv7-M - armv7m
1200 // Cortex-M4 - ARMv7E-M - armv7em
1201 case ArchSpec::eCore_arm_armv6m:
1202 if (!enforce_exact_match) {
1203 if (core2 == ArchSpec::eCore_arm_generic)
1204 return true;
1205 if (core2 == ArchSpec::eCore_arm_armv7em)
1206 return true;
1207 if (core2 == ArchSpec::eCore_arm_armv7)
1208 return true;
1209 if (core2 == ArchSpec::eCore_arm_armv6m)
1210 return true;
1211 try_inverse = false;
1212 }
1213 break;
1214
1215 case ArchSpec::eCore_arm_armv7f:
1216 case ArchSpec::eCore_arm_armv7k:
1217 case ArchSpec::eCore_arm_armv7s:
1218 case ArchSpec::eCore_arm_armv7l:
1219 case ArchSpec::eCore_arm_armv8l:
1220 if (!enforce_exact_match) {
1221 if (core2 == ArchSpec::eCore_arm_generic)
1222 return true;
1223 if (core2 == ArchSpec::eCore_arm_armv7)
1224 return true;
1225 try_inverse = false;
1226 }
1227 break;
1228
1229 case ArchSpec::eCore_x86_64_x86_64h:
1230 if (!enforce_exact_match) {
1231 try_inverse = false;
1232 if (core2 == ArchSpec::eCore_x86_64_x86_64)
1233 return true;
1234 }
1235 break;
1236
1237 case ArchSpec::eCore_arm_armv8:
1238 if (!enforce_exact_match) {
1239 if (core2 == ArchSpec::eCore_arm_arm64)
1240 return true;
1241 if (core2 == ArchSpec::eCore_arm_aarch64)
1242 return true;
1243 if (core2 == ArchSpec::eCore_arm_arm64e)
1244 return true;
1245 try_inverse = false;
1246 }
1247 break;
1248
1249 case ArchSpec::eCore_arm_arm64e:
1250 if (!enforce_exact_match) {
1251 if (core2 == ArchSpec::eCore_arm_arm64)
1252 return true;
1253 if (core2 == ArchSpec::eCore_arm_aarch64)
1254 return true;
1255 if (core2 == ArchSpec::eCore_arm_armv8)
1256 return true;
1257 try_inverse = false;
1258 }
1259 break;
1260 case ArchSpec::eCore_arm_aarch64:
1261 if (!enforce_exact_match) {
1262 if (core2 == ArchSpec::eCore_arm_arm64)
1263 return true;
1264 if (core2 == ArchSpec::eCore_arm_armv8)
1265 return true;
1266 if (core2 == ArchSpec::eCore_arm_arm64e)
1267 return true;
1268 try_inverse = false;
1269 }
1270 break;
1271
1272 case ArchSpec::eCore_arm_arm64:
1273 if (!enforce_exact_match) {
1274 if (core2 == ArchSpec::eCore_arm_aarch64)
1275 return true;
1276 if (core2 == ArchSpec::eCore_arm_armv8)
1277 return true;
1278 if (core2 == ArchSpec::eCore_arm_arm64e)
1279 return true;
1280 try_inverse = false;
1281 }
1282 break;
1283
1284 case ArchSpec::eCore_arm_arm64_32:
1285 if (!enforce_exact_match) {
1286 if (core2 == ArchSpec::eCore_arm_generic)
1287 return true;
1288 try_inverse = false;
1289 }
1290 break;
1291
1292 case ArchSpec::eCore_mips32:
1293 if (!enforce_exact_match) {
1294 if (core2 >= ArchSpec::kCore_mips32_first &&
1295 core2 <= ArchSpec::kCore_mips32_last)
1296 return true;
1297 try_inverse = false;
1298 }
1299 break;
1300
1301 case ArchSpec::eCore_mips32el:
1302 if (!enforce_exact_match) {
1303 if (core2 >= ArchSpec::kCore_mips32el_first &&
1304 core2 <= ArchSpec::kCore_mips32el_last)
1305 return true;
1306 try_inverse = true;
1307 }
1308 break;
1309
1310 case ArchSpec::eCore_mips64:
1311 if (!enforce_exact_match) {
1312 if (core2 >= ArchSpec::kCore_mips32_first &&
1313 core2 <= ArchSpec::kCore_mips32_last)
1314 return true;
1315 if (core2 >= ArchSpec::kCore_mips64_first &&
1316 core2 <= ArchSpec::kCore_mips64_last)
1317 return true;
1318 try_inverse = false;
1319 }
1320 break;
1321
1322 case ArchSpec::eCore_mips64el:
1323 if (!enforce_exact_match) {
1324 if (core2 >= ArchSpec::kCore_mips32el_first &&
1325 core2 <= ArchSpec::kCore_mips32el_last)
1326 return true;
1327 if (core2 >= ArchSpec::kCore_mips64el_first &&
1328 core2 <= ArchSpec::kCore_mips64el_last)
1329 return true;
1330 try_inverse = false;
1331 }
1332 break;
1333
1334 case ArchSpec::eCore_mips64r2:
1335 case ArchSpec::eCore_mips64r3:
1336 case ArchSpec::eCore_mips64r5:
1337 if (!enforce_exact_match) {
1338 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= (core1 - 10))
1339 return true;
1340 if (core2 >= ArchSpec::kCore_mips64_first && core2 <= (core1 - 1))
1341 return true;
1342 try_inverse = false;
1343 }
1344 break;
1345
1346 case ArchSpec::eCore_mips64r2el:
1347 case ArchSpec::eCore_mips64r3el:
1348 case ArchSpec::eCore_mips64r5el:
1349 if (!enforce_exact_match) {
1350 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= (core1 - 10))
1351 return true;
1352 if (core2 >= ArchSpec::kCore_mips64el_first && core2 <= (core1 - 1))
1353 return true;
1354 try_inverse = false;
1355 }
1356 break;
1357
1358 case ArchSpec::eCore_mips32r2:
1359 case ArchSpec::eCore_mips32r3:
1360 case ArchSpec::eCore_mips32r5:
1361 if (!enforce_exact_match) {
1362 if (core2 >= ArchSpec::kCore_mips32_first && core2 <= core1)
1363 return true;
1364 }
1365 break;
1366
1367 case ArchSpec::eCore_mips32r2el:
1368 case ArchSpec::eCore_mips32r3el:
1369 case ArchSpec::eCore_mips32r5el:
1370 if (!enforce_exact_match) {
1371 if (core2 >= ArchSpec::kCore_mips32el_first && core2 <= core1)
1372 return true;
1373 }
1374 break;
1375
1376 case ArchSpec::eCore_mips32r6:
1377 if (!enforce_exact_match) {
1378 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1379 return true;
1380 }
1381 break;
1382
1383 case ArchSpec::eCore_mips32r6el:
1384 if (!enforce_exact_match) {
1385 if (core2 == ArchSpec::eCore_mips32el ||
1386 core2 == ArchSpec::eCore_mips32r6el)
1387 return true;
1388 }
1389 break;
1390
1391 case ArchSpec::eCore_mips64r6:
1392 if (!enforce_exact_match) {
1393 if (core2 == ArchSpec::eCore_mips32 || core2 == ArchSpec::eCore_mips32r6)
1394 return true;
1395 if (core2 == ArchSpec::eCore_mips64 || core2 == ArchSpec::eCore_mips64r6)
1396 return true;
1397 }
1398 break;
1399
1400 case ArchSpec::eCore_mips64r6el:
1401 if (!enforce_exact_match) {
1402 if (core2 == ArchSpec::eCore_mips32el ||
1403 core2 == ArchSpec::eCore_mips32r6el)
1404 return true;
1405 if (core2 == ArchSpec::eCore_mips64el ||
1406 core2 == ArchSpec::eCore_mips64r6el)
1407 return true;
1408 }
1409 break;
1410
1411 default:
1412 break;
1413 }
1414 if (try_inverse)
1415 return cores_match(core2, core1, false, enforce_exact_match);
1416 return false;
1417 }
1418
1419 bool lldb_private::operator<(const ArchSpec &lhs, const ArchSpec &rhs) {
1420 const ArchSpec::Core lhs_core = lhs.GetCore();
1421 const ArchSpec::Core rhs_core = rhs.GetCore();
1422 return lhs_core < rhs_core;
1423 }
1424
1425
1426 bool lldb_private::operator==(const ArchSpec &lhs, const ArchSpec &rhs) {
1427 return lhs.GetCore() == rhs.GetCore();
1428 }
1429
1430 bool ArchSpec::IsFullySpecifiedTriple() const {
1431 if (!TripleOSWasSpecified())
1432 return false;
1433
1434 if (!TripleVendorWasSpecified())
1435 return false;
1436
1437 const unsigned unspecified = 0;
1438 const llvm::Triple &triple = GetTriple();
1439 if (triple.isOSDarwin() && triple.getOSMajorVersion() == unspecified)
1440 return false;
1441
1442 return true;
1443 }
1444
1445 bool ArchSpec::IsAlwaysThumbInstructions() const {
1446 std::string Status;
1447 if (GetTriple().getArch() == llvm::Triple::arm ||
1448 GetTriple().getArch() == llvm::Triple::thumb) {
1449 // v. https://en.wikipedia.org/wiki/ARM_Cortex-M
1450 //
1451 // Cortex-M0 through Cortex-M7 are ARM processor cores which can only
1452 // execute thumb instructions. We map the cores to arch names like this:
1453 //
1454 // Cortex-M0, Cortex-M0+, Cortex-M1: armv6m Cortex-M3: armv7m Cortex-M4,
1455 // Cortex-M7: armv7em
1456
1457 if (GetCore() == ArchSpec::Core::eCore_arm_armv7m ||
1458 GetCore() == ArchSpec::Core::eCore_arm_armv7em ||
1459 GetCore() == ArchSpec::Core::eCore_arm_armv6m ||
1460 GetCore() == ArchSpec::Core::eCore_thumbv7m ||
1461 GetCore() == ArchSpec::Core::eCore_thumbv7em ||
1462 GetCore() == ArchSpec::Core::eCore_thumbv6m) {
1463 return true;
1464 }
1465 // Windows on ARM is always thumb.
1466 if (GetTriple().isOSWindows())
1467 return true;
1468 }
1469 return false;
1470 }
1471
1472 void ArchSpec::DumpTriple(llvm::raw_ostream &s) const {
1473 const llvm::Triple &triple = GetTriple();
1474 llvm::StringRef arch_str = triple.getArchName();
1475 llvm::StringRef vendor_str = triple.getVendorName();
1476 llvm::StringRef os_str = triple.getOSName();
1477 llvm::StringRef environ_str = triple.getEnvironmentName();
1478
1479 s << llvm::formatv("{0}-{1}-{2}", arch_str.empty() ? "*" : arch_str,
1480 vendor_str.empty() ? "*" : vendor_str,
1481 os_str.empty() ? "*" : os_str);
1482
1483 if (!environ_str.empty())
1484 s << "-" << environ_str;
1485 }
LLVM monorepo