1 ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 3
2 ; RUN: opt -S -disable-output -passes='print<access-info>' < %s 2>&1 | FileCheck %s
4 ; Generated from following C program:
5 ; void foo(int len, int *a) {
6 ; for (int k = 0; k < len; k+=3) {
11 define void @foo(i64 %len, ptr %a) {
14 ; CHECK-NEXT: Memory dependences are safe with a maximum safe vector width of 64 bits
15 ; CHECK-NEXT: Dependences:
16 ; CHECK-NEXT: BackwardVectorizable:
17 ; CHECK-NEXT: store i32 %0, ptr %arrayidx2, align 4 ->
18 ; CHECK-NEXT: %1 = load i32, ptr %arrayidx5, align 4
20 ; CHECK-NEXT: Run-time memory checks:
21 ; CHECK-NEXT: Grouped accesses:
23 ; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
24 ; CHECK-NEXT: SCEV assumptions:
26 ; CHECK-NEXT: Expressions re-written:
38 %iv = phi i64 [ 0, %loop.preheader ], [ %iv.next, %loop ]
39 %iv.4 = add nuw nsw i64 %iv, 4
40 %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv.4
41 %0 = load i32, ptr %arrayidx, align 4
42 %arrayidx2 = getelementptr inbounds i32, ptr %a, i64 %iv
43 store i32 %0, ptr %arrayidx2, align 4
44 %iv.6 = add nuw nsw i64 %iv, 6
45 %arrayidx5 = getelementptr inbounds i32, ptr %a, i64 %iv.6
46 %1 = load i32, ptr %arrayidx5, align 4
47 %iv.2 = add nuw nsw i64 %iv, 2
48 %arrayidx8 = getelementptr inbounds i32, ptr %a, i64 %iv.2
49 store i32 %1, ptr %arrayidx8, align 4
50 %iv.next = add nuw nsw i64 %iv, 3
51 %cmp = icmp ult i64 %iv.next, %len
52 br i1 %cmp, label %loop, label %loop.exit