| blob | 7f804fe48fd854c4c5dd3a477ae346e946ae362d |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD
3 ; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
5 declare i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
6 declare i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
7 declare i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
8 declare i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)
9 declare i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
10 declare i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)
11 declare i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
13 declare i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)
14 declare i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)
15 declare i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)
16 declare i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
17 declare i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)
18 declare i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)
19 declare i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)
20 declare i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)
22 define i1 @test_v1i1(<1 x i1> %a) nounwind {
23 ; CHECK-LABEL: test_v1i1:
24 ; CHECK: // %bb.0:
25 ; CHECK-NEXT: and w0, w0, #0x1
26 ; CHECK-NEXT: ret
27 %b = call i1 @llvm.vector.reduce.umax.v1i1(<1 x i1> %a)
28 ret i1 %b
29 }
31 define i8 @test_v1i8(<1 x i8> %a) nounwind {
32 ; CHECK-SD-LABEL: test_v1i8:
33 ; CHECK-SD: // %bb.0:
34 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
35 ; CHECK-SD-NEXT: umov w0, v0.b[0]
36 ; CHECK-SD-NEXT: ret
37 ;
38 ; CHECK-GI-LABEL: test_v1i8:
39 ; CHECK-GI: // %bb.0:
40 ; CHECK-GI-NEXT: fmov x0, d0
41 ; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
42 ; CHECK-GI-NEXT: ret
43 %b = call i8 @llvm.vector.reduce.umax.v1i8(<1 x i8> %a)
44 ret i8 %b
45 }
47 define i16 @test_v1i16(<1 x i16> %a) nounwind {
48 ; CHECK-SD-LABEL: test_v1i16:
49 ; CHECK-SD: // %bb.0:
50 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
51 ; CHECK-SD-NEXT: umov w0, v0.h[0]
52 ; CHECK-SD-NEXT: ret
53 ;
54 ; CHECK-GI-LABEL: test_v1i16:
55 ; CHECK-GI: // %bb.0:
56 ; CHECK-GI-NEXT: fmov x0, d0
57 ; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
58 ; CHECK-GI-NEXT: ret
59 %b = call i16 @llvm.vector.reduce.umax.v1i16(<1 x i16> %a)
60 ret i16 %b
61 }
63 define i24 @test_v1i24(<1 x i24> %a) nounwind {
64 ; CHECK-LABEL: test_v1i24:
65 ; CHECK: // %bb.0:
66 ; CHECK-NEXT: ret
67 %b = call i24 @llvm.vector.reduce.umax.v1i24(<1 x i24> %a)
68 ret i24 %b
69 }
71 define i32 @test_v1i32(<1 x i32> %a) nounwind {
72 ; CHECK-SD-LABEL: test_v1i32:
73 ; CHECK-SD: // %bb.0:
74 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
75 ; CHECK-SD-NEXT: fmov w0, s0
76 ; CHECK-SD-NEXT: ret
77 ;
78 ; CHECK-GI-LABEL: test_v1i32:
79 ; CHECK-GI: // %bb.0:
80 ; CHECK-GI-NEXT: fmov x0, d0
81 ; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
82 ; CHECK-GI-NEXT: ret
83 %b = call i32 @llvm.vector.reduce.umax.v1i32(<1 x i32> %a)
84 ret i32 %b
85 }
87 define i64 @test_v1i64(<1 x i64> %a) nounwind {
88 ; CHECK-SD-LABEL: test_v1i64:
89 ; CHECK-SD: // %bb.0:
90 ; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
91 ; CHECK-SD-NEXT: fmov x0, d0
92 ; CHECK-SD-NEXT: ret
93 ;
94 ; CHECK-GI-LABEL: test_v1i64:
95 ; CHECK-GI: // %bb.0:
96 ; CHECK-GI-NEXT: fmov x0, d0
97 ; CHECK-GI-NEXT: ret
98 %b = call i64 @llvm.vector.reduce.umax.v1i64(<1 x i64> %a)
99 ret i64 %b
100 }
102 define i128 @test_v1i128(<1 x i128> %a) nounwind {
103 ; CHECK-LABEL: test_v1i128:
104 ; CHECK: // %bb.0:
105 ; CHECK-NEXT: ret
106 %b = call i128 @llvm.vector.reduce.umax.v1i128(<1 x i128> %a)
107 ret i128 %b
108 }
110 ; No i64 vector support for UMAX.
111 define i64 @test_v2i64(<2 x i64> %a) nounwind {
112 ; CHECK-SD-LABEL: test_v2i64:
113 ; CHECK-SD: // %bb.0:
114 ; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
115 ; CHECK-SD-NEXT: cmhi d2, d0, d1
116 ; CHECK-SD-NEXT: bif v0.8b, v1.8b, v2.8b
117 ; CHECK-SD-NEXT: fmov x0, d0
118 ; CHECK-SD-NEXT: ret
119 ;
120 ; CHECK-GI-LABEL: test_v2i64:
121 ; CHECK-GI: // %bb.0:
122 ; CHECK-GI-NEXT: mov d1, v0.d[1]
123 ; CHECK-GI-NEXT: fmov x8, d0
124 ; CHECK-GI-NEXT: fmov x9, d1
125 ; CHECK-GI-NEXT: cmp x8, x9
126 ; CHECK-GI-NEXT: fcsel d0, d0, d1, hi
127 ; CHECK-GI-NEXT: fmov x0, d0
128 ; CHECK-GI-NEXT: ret
129 %b = call i64 @llvm.vector.reduce.umax.v2i64(<2 x i64> %a)
130 ret i64 %b
131 }
133 define i8 @test_v3i8(<3 x i8> %a) nounwind {
134 ; CHECK-SD-LABEL: test_v3i8:
135 ; CHECK-SD: // %bb.0:
136 ; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
137 ; CHECK-SD-NEXT: mov v0.h[0], w0
138 ; CHECK-SD-NEXT: mov v0.h[1], w1
139 ; CHECK-SD-NEXT: mov v0.h[2], w2
140 ; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8
141 ; CHECK-SD-NEXT: umaxv h0, v0.4h
142 ; CHECK-SD-NEXT: fmov w0, s0
143 ; CHECK-SD-NEXT: ret
144 ;
145 ; CHECK-GI-LABEL: test_v3i8:
146 ; CHECK-GI: // %bb.0:
147 ; CHECK-GI-NEXT: and w8, w0, #0xff
148 ; CHECK-GI-NEXT: cmp w8, w1, uxtb
149 ; CHECK-GI-NEXT: csel w8, w0, w1, hi
150 ; CHECK-GI-NEXT: and w9, w8, #0xff
151 ; CHECK-GI-NEXT: cmp w9, w2, uxtb
152 ; CHECK-GI-NEXT: csel w0, w8, w2, hi
153 ; CHECK-GI-NEXT: ret
154 %b = call i8 @llvm.vector.reduce.umax.v3i8(<3 x i8> %a)
155 ret i8 %b
156 }
158 define i8 @test_v9i8(<9 x i8> %a) nounwind {
159 ; CHECK-SD-LABEL: test_v9i8:
160 ; CHECK-SD: // %bb.0:
161 ; CHECK-SD-NEXT: adrp x8, .LCPI9_0
162 ; CHECK-SD-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
163 ; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b
164 ; CHECK-SD-NEXT: umaxv b0, v0.16b
165 ; CHECK-SD-NEXT: fmov w0, s0
166 ; CHECK-SD-NEXT: ret
167 ;
168 ; CHECK-GI-LABEL: test_v9i8:
169 ; CHECK-GI: // %bb.0:
170 ; CHECK-GI-NEXT: mov b1, v0.b[1]
171 ; CHECK-GI-NEXT: umov w8, v0.b[0]
172 ; CHECK-GI-NEXT: umov w9, v0.b[1]
173 ; CHECK-GI-NEXT: umov w10, v0.b[2]
174 ; CHECK-GI-NEXT: fmov w11, s1
175 ; CHECK-GI-NEXT: cmp w8, w11, uxtb
176 ; CHECK-GI-NEXT: umov w11, v0.b[3]
177 ; CHECK-GI-NEXT: csel w8, w8, w9, hi
178 ; CHECK-GI-NEXT: umov w9, v0.b[4]
179 ; CHECK-GI-NEXT: cmp w10, w8, uxtb
180 ; CHECK-GI-NEXT: csel w8, w8, w10, lo
181 ; CHECK-GI-NEXT: umov w10, v0.b[5]
182 ; CHECK-GI-NEXT: cmp w11, w8, uxtb
183 ; CHECK-GI-NEXT: csel w8, w8, w11, lo
184 ; CHECK-GI-NEXT: umov w11, v0.b[6]
185 ; CHECK-GI-NEXT: cmp w9, w8, uxtb
186 ; CHECK-GI-NEXT: csel w8, w8, w9, lo
187 ; CHECK-GI-NEXT: umov w9, v0.b[7]
188 ; CHECK-GI-NEXT: cmp w10, w8, uxtb
189 ; CHECK-GI-NEXT: csel w8, w8, w10, lo
190 ; CHECK-GI-NEXT: umov w10, v0.b[8]
191 ; CHECK-GI-NEXT: cmp w11, w8, uxtb
192 ; CHECK-GI-NEXT: csel w8, w8, w11, lo
193 ; CHECK-GI-NEXT: cmp w9, w8, uxtb
194 ; CHECK-GI-NEXT: csel w8, w8, w9, lo
195 ; CHECK-GI-NEXT: cmp w10, w8, uxtb
196 ; CHECK-GI-NEXT: csel w0, w8, w10, lo
197 ; CHECK-GI-NEXT: ret
198 %b = call i8 @llvm.vector.reduce.umax.v9i8(<9 x i8> %a)
199 ret i8 %b
200 }
202 define i32 @test_v3i32(<3 x i32> %a) nounwind {
203 ; CHECK-SD-LABEL: test_v3i32:
204 ; CHECK-SD: // %bb.0:
205 ; CHECK-SD-NEXT: mov v0.s[3], wzr
206 ; CHECK-SD-NEXT: umaxv s0, v0.4s
207 ; CHECK-SD-NEXT: fmov w0, s0
208 ; CHECK-SD-NEXT: ret
209 ;
210 ; CHECK-GI-LABEL: test_v3i32:
211 ; CHECK-GI: // %bb.0:
212 ; CHECK-GI-NEXT: mov s1, v0.s[1]
213 ; CHECK-GI-NEXT: fmov w8, s0
214 ; CHECK-GI-NEXT: mov s2, v0.s[2]
215 ; CHECK-GI-NEXT: fmov w9, s1
216 ; CHECK-GI-NEXT: cmp w8, w9
217 ; CHECK-GI-NEXT: fmov w9, s2
218 ; CHECK-GI-NEXT: fcsel s0, s0, s1, hi
219 ; CHECK-GI-NEXT: fmov w8, s0
220 ; CHECK-GI-NEXT: cmp w8, w9
221 ; CHECK-GI-NEXT: fcsel s0, s0, s2, hi
222 ; CHECK-GI-NEXT: fmov w0, s0
223 ; CHECK-GI-NEXT: ret
224 %b = call i32 @llvm.vector.reduce.umax.v3i32(<3 x i32> %a)
225 ret i32 %b
226 }
228 define i1 @test_v4i1(<4 x i1> %a) nounwind {
229 ; CHECK-SD-LABEL: test_v4i1:
230 ; CHECK-SD: // %bb.0:
231 ; CHECK-SD-NEXT: shl v0.4h, v0.4h, #15
232 ; CHECK-SD-NEXT: cmlt v0.4h, v0.4h, #0
233 ; CHECK-SD-NEXT: umaxv h0, v0.4h
234 ; CHECK-SD-NEXT: fmov w8, s0
235 ; CHECK-SD-NEXT: and w0, w8, #0x1
236 ; CHECK-SD-NEXT: ret
237 ;
238 ; CHECK-GI-LABEL: test_v4i1:
239 ; CHECK-GI: // %bb.0:
240 ; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
241 ; CHECK-GI-NEXT: umov w8, v0.h[0]
242 ; CHECK-GI-NEXT: umov w9, v0.h[1]
243 ; CHECK-GI-NEXT: umov w10, v0.h[2]
244 ; CHECK-GI-NEXT: umov w11, v0.h[3]
245 ; CHECK-GI-NEXT: and w12, w8, #0x1
246 ; CHECK-GI-NEXT: and w13, w9, #0x1
247 ; CHECK-GI-NEXT: cmp w12, w13
248 ; CHECK-GI-NEXT: and w12, w10, #0x1
249 ; CHECK-GI-NEXT: and w13, w11, #0x1
250 ; CHECK-GI-NEXT: csel w8, w8, w9, hi
251 ; CHECK-GI-NEXT: cmp w12, w13
252 ; CHECK-GI-NEXT: csel w9, w10, w11, hi
253 ; CHECK-GI-NEXT: and w10, w8, #0x1
254 ; CHECK-GI-NEXT: and w11, w9, #0x1
255 ; CHECK-GI-NEXT: cmp w10, w11
256 ; CHECK-GI-NEXT: csel w8, w8, w9, hi
257 ; CHECK-GI-NEXT: and w0, w8, #0x1
258 ; CHECK-GI-NEXT: ret
259 %b = call i1 @llvm.vector.reduce.umax.v4i1(<4 x i1> %a)
260 ret i1 %b
261 }
263 define i24 @test_v4i24(<4 x i24> %a) nounwind {
264 ; CHECK-SD-LABEL: test_v4i24:
265 ; CHECK-SD: // %bb.0:
266 ; CHECK-SD-NEXT: bic v0.4s, #255, lsl #24
267 ; CHECK-SD-NEXT: umaxv s0, v0.4s
268 ; CHECK-SD-NEXT: fmov w0, s0
269 ; CHECK-SD-NEXT: ret
270 ;
271 ; CHECK-GI-LABEL: test_v4i24:
272 ; CHECK-GI: // %bb.0:
273 ; CHECK-GI-NEXT: mov s1, v0.s[1]
274 ; CHECK-GI-NEXT: mov s2, v0.s[2]
275 ; CHECK-GI-NEXT: mov s3, v0.s[3]
276 ; CHECK-GI-NEXT: fmov w8, s0
277 ; CHECK-GI-NEXT: fmov w9, s1
278 ; CHECK-GI-NEXT: fmov w10, s2
279 ; CHECK-GI-NEXT: fmov w11, s3
280 ; CHECK-GI-NEXT: and w8, w8, #0xffffff
281 ; CHECK-GI-NEXT: and w9, w9, #0xffffff
282 ; CHECK-GI-NEXT: cmp w8, w9
283 ; CHECK-GI-NEXT: and w8, w10, #0xffffff
284 ; CHECK-GI-NEXT: and w9, w11, #0xffffff
285 ; CHECK-GI-NEXT: fcsel s0, s0, s1, hi
286 ; CHECK-GI-NEXT: cmp w8, w9
287 ; CHECK-GI-NEXT: fcsel s1, s2, s3, hi
288 ; CHECK-GI-NEXT: fmov w8, s0
289 ; CHECK-GI-NEXT: fmov w9, s1
290 ; CHECK-GI-NEXT: and w8, w8, #0xffffff
291 ; CHECK-GI-NEXT: and w9, w9, #0xffffff
292 ; CHECK-GI-NEXT: cmp w8, w9
293 ; CHECK-GI-NEXT: fcsel s0, s0, s1, hi
294 ; CHECK-GI-NEXT: fmov w0, s0
295 ; CHECK-GI-NEXT: ret
296 %b = call i24 @llvm.vector.reduce.umax.v4i24(<4 x i24> %a)
297 ret i24 %b
298 }
300 define i128 @test_v2i128(<2 x i128> %a) nounwind {
301 ; CHECK-SD-LABEL: test_v2i128:
302 ; CHECK-SD: // %bb.0:
303 ; CHECK-SD-NEXT: cmp x2, x0
304 ; CHECK-SD-NEXT: sbcs xzr, x3, x1
305 ; CHECK-SD-NEXT: csel x0, x0, x2, lo
306 ; CHECK-SD-NEXT: csel x1, x1, x3, lo
307 ; CHECK-SD-NEXT: ret
308 ;
309 ; CHECK-GI-LABEL: test_v2i128:
310 ; CHECK-GI: // %bb.0:
311 ; CHECK-GI-NEXT: cmp x1, x3
312 ; CHECK-GI-NEXT: cset w8, hi
313 ; CHECK-GI-NEXT: cmp x0, x2
314 ; CHECK-GI-NEXT: cset w9, hi
315 ; CHECK-GI-NEXT: cmp x1, x3
316 ; CHECK-GI-NEXT: csel w8, w9, w8, eq
317 ; CHECK-GI-NEXT: tst w8, #0x1
318 ; CHECK-GI-NEXT: csel x0, x0, x2, ne
319 ; CHECK-GI-NEXT: csel x1, x1, x3, ne
320 ; CHECK-GI-NEXT: ret
321 %b = call i128 @llvm.vector.reduce.umax.v2i128(<2 x i128> %a)
322 ret i128 %b
323 }
325 define i32 @test_v16i32(<16 x i32> %a) nounwind {
326 ; CHECK-SD-LABEL: test_v16i32:
327 ; CHECK-SD: // %bb.0:
328 ; CHECK-SD-NEXT: umax v1.4s, v1.4s, v3.4s
329 ; CHECK-SD-NEXT: umax v0.4s, v0.4s, v2.4s
330 ; CHECK-SD-NEXT: umax v0.4s, v0.4s, v1.4s
331 ; CHECK-SD-NEXT: umaxv s0, v0.4s
332 ; CHECK-SD-NEXT: fmov w0, s0
333 ; CHECK-SD-NEXT: ret
334 ;
335 ; CHECK-GI-LABEL: test_v16i32:
336 ; CHECK-GI: // %bb.0:
337 ; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s
338 ; CHECK-GI-NEXT: umax v1.4s, v2.4s, v3.4s
339 ; CHECK-GI-NEXT: umax v0.4s, v0.4s, v1.4s
340 ; CHECK-GI-NEXT: umaxv s0, v0.4s
341 ; CHECK-GI-NEXT: fmov w0, s0
342 ; CHECK-GI-NEXT: ret
343 %b = call i32 @llvm.vector.reduce.umax.v16i32(<16 x i32> %a)
344 ret i32 %b
345 }