1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,SDAG
3 ; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=GCN,GISEL
5 declare void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) nocapture, i32 %size, i32 %vindex, i32 %voffset, i32 %soffset, i32 %offset, i32 %aux)
7 define amdgpu_ps float @buffer_load_lds_dword(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds) {
8 ; SDAG-LABEL: buffer_load_lds_dword:
9 ; SDAG: ; %bb.0: ; %main_body
10 ; SDAG-NEXT: v_mov_b32_e32 v0, 8
11 ; SDAG-NEXT: s_mov_b32 m0, s4
13 ; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen lds
14 ; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:4 glc lds
15 ; SDAG-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:8 slc lds
16 ; SDAG-NEXT: v_mov_b32_e32 v0, s4
17 ; SDAG-NEXT: s_waitcnt vmcnt(0)
18 ; SDAG-NEXT: ds_read_b32 v0, v0
19 ; SDAG-NEXT: s_waitcnt lgkmcnt(0)
20 ; SDAG-NEXT: ; return to shader part epilog
22 ; GISEL-LABEL: buffer_load_lds_dword:
23 ; GISEL: ; %bb.0: ; %main_body
24 ; GISEL-NEXT: s_mov_b32 m0, s4
25 ; GISEL-NEXT: v_mov_b32_e32 v0, 8
26 ; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen lds
27 ; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:4 glc lds
28 ; GISEL-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:8 slc lds
29 ; GISEL-NEXT: v_mov_b32_e32 v0, s4
30 ; GISEL-NEXT: s_waitcnt vmcnt(0)
31 ; GISEL-NEXT: ds_read_b32 v0, v0
32 ; GISEL-NEXT: s_waitcnt lgkmcnt(0)
33 ; GISEL-NEXT: ; return to shader part epilog
35 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 0, i32 0)
36 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 4, i32 1)
37 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 8, i32 0, i32 0, i32 8, i32 2)
38 %res = load float, ptr addrspace(3) %lds
42 define amdgpu_ps void @buffer_load_lds_dword_imm_offset(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
43 ; GCN-LABEL: buffer_load_lds_dword_imm_offset:
44 ; GCN: ; %bb.0: ; %main_body
45 ; GCN-NEXT: s_mov_b32 m0, s4
47 ; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 idxen offset:2048 lds
50 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)
54 define amdgpu_ps void @buffer_load_lds_dword_v_offset(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset) {
55 ; GCN-LABEL: buffer_load_lds_dword_v_offset:
56 ; GCN: ; %bb.0: ; %main_body
57 ; GCN-NEXT: s_mov_b32 m0, s4
59 ; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], 0 idxen offen lds
62 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 0, i32 0, i32 0)
66 define amdgpu_ps void @buffer_load_lds_dword_s_offset(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 inreg %soffset) {
67 ; GCN-LABEL: buffer_load_lds_dword_s_offset:
68 ; GCN: ; %bb.0: ; %main_body
69 ; GCN-NEXT: s_mov_b32 m0, s4
71 ; GCN-NEXT: buffer_load_dword v0, s[0:3], s5 idxen lds
74 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 0, i32 %soffset, i32 0, i32 0)
78 define amdgpu_ps void @buffer_load_lds_dword_vs_offset(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
79 ; GCN-LABEL: buffer_load_lds_dword_vs_offset:
80 ; GCN: ; %bb.0: ; %main_body
81 ; GCN-NEXT: s_mov_b32 m0, s4
83 ; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen lds
86 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 0, i32 0)
90 define amdgpu_ps void @buffer_load_lds_dword_vs_imm_offset(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex, i32 %voffset, i32 inreg %soffset) {
91 ; GCN-LABEL: buffer_load_lds_dword_vs_imm_offset:
92 ; GCN: ; %bb.0: ; %main_body
93 ; GCN-NEXT: s_mov_b32 m0, s4
95 ; GCN-NEXT: buffer_load_dword v[0:1], s[0:3], s5 idxen offen offset:2048 lds
98 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 4, i32 %vindex, i32 %voffset, i32 %soffset, i32 2048, i32 0)
102 define amdgpu_ps void @buffer_load_lds_ushort(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
103 ; GCN-LABEL: buffer_load_lds_ushort:
104 ; GCN: ; %bb.0: ; %main_body
105 ; GCN-NEXT: v_mov_b32_e32 v1, 0x800
106 ; GCN-NEXT: s_mov_b32 m0, s4
108 ; GCN-NEXT: buffer_load_ushort v[0:1], s[0:3], 0 idxen offen lds
111 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 2, i32 %vindex, i32 2048, i32 0, i32 0, i32 0)
115 define amdgpu_ps void @buffer_load_lds_ubyte(<4 x i32> inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %vindex) {
116 ; GCN-LABEL: buffer_load_lds_ubyte:
117 ; GCN: ; %bb.0: ; %main_body
118 ; GCN-NEXT: s_mov_b32 m0, s4
120 ; GCN-NEXT: buffer_load_ubyte v0, s[0:3], 0 idxen offset:2048 lds
123 call void @llvm.amdgcn.struct.buffer.load.lds(<4 x i32> %rsrc, ptr addrspace(3) %lds, i32 1, i32 %vindex, i32 0, i32 0, i32 2048, i32 0)