| blob | f70441e87a74b5d9519a7ecdba4ee939ac818d8a |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -O0 -verify-machineinstrs < %s | FileCheck %s
4 ; FP is in CSR range, modified.
5 define hidden fastcc void @callee_has_fp() #1 {
6 ; CHECK-LABEL: callee_has_fp:
7 ; CHECK: ; %bb.0:
8 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
9 ; CHECK-NEXT: s_mov_b32 s4, s33
10 ; CHECK-NEXT: s_mov_b32 s33, s32
11 ; CHECK-NEXT: s_add_i32 s32, s32, 0x200
12 ; CHECK-NEXT: v_mov_b32_e32 v0, 1
13 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s33
14 ; CHECK-NEXT: s_waitcnt vmcnt(0)
15 ; CHECK-NEXT: s_add_i32 s32, s32, 0xfffffe00
16 ; CHECK-NEXT: s_mov_b32 s33, s4
17 ; CHECK-NEXT: s_setpc_b64 s[30:31]
18 %alloca = alloca i32, addrspace(5)
19 store volatile i32 1, ptr addrspace(5) %alloca
20 ret void
21 }
23 ; Has no stack objects, but introduces them due to the CSR spill. We
24 ; see the FP modified in the callee with IPRA. We should not have
25 ; redundant spills of s33 or assert.
26 define internal fastcc void @csr_vgpr_spill_fp_callee() #0 {
27 ; CHECK-LABEL: csr_vgpr_spill_fp_callee:
28 ; CHECK: ; %bb.0: ; %bb
29 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
30 ; CHECK-NEXT: s_mov_b32 s18, s33
31 ; CHECK-NEXT: s_mov_b32 s33, s32
32 ; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1
33 ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Spill
34 ; CHECK-NEXT: s_mov_b64 exec, s[16:17]
35 ; CHECK-NEXT: s_add_i32 s32, s32, 0x400
36 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s33 ; 4-byte Folded Spill
37 ; CHECK-NEXT: v_writelane_b32 v1, s30, 0
38 ; CHECK-NEXT: v_writelane_b32 v1, s31, 1
39 ; CHECK-NEXT: s_getpc_b64 s[16:17]
40 ; CHECK-NEXT: s_add_u32 s16, s16, callee_has_fp@rel32@lo+4
41 ; CHECK-NEXT: s_addc_u32 s17, s17, callee_has_fp@rel32@hi+12
42 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
43 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
44 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
45 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
46 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
47 ; CHECK-NEXT: ;;#ASMSTART
48 ; CHECK-NEXT: ; clobber csr v40
49 ; CHECK-NEXT: ;;#ASMEND
50 ; CHECK-NEXT: v_readlane_b32 s31, v1, 1
51 ; CHECK-NEXT: v_readlane_b32 s30, v1, 0
52 ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s33 ; 4-byte Folded Reload
53 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
54 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
55 ; CHECK-NEXT: s_mov_b64 exec, s[4:5]
56 ; CHECK-NEXT: s_add_i32 s32, s32, 0xfffffc00
57 ; CHECK-NEXT: s_mov_b32 s33, s18
58 ; CHECK-NEXT: s_waitcnt vmcnt(0)
59 ; CHECK-NEXT: s_setpc_b64 s[30:31]
60 bb:
61 call fastcc void @callee_has_fp()
62 call void asm sideeffect "; clobber csr v40", "~{v40}"()
63 ret void
64 }
66 define amdgpu_kernel void @kernel_call() {
67 ; CHECK-LABEL: kernel_call:
68 ; CHECK: ; %bb.0: ; %bb
69 ; CHECK-NEXT: s_mov_b32 s32, 0
70 ; CHECK-NEXT: s_add_u32 flat_scratch_lo, s10, s15
71 ; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
72 ; CHECK-NEXT: s_add_u32 s0, s0, s15
73 ; CHECK-NEXT: s_addc_u32 s1, s1, 0
74 ; CHECK-NEXT: s_mov_b64 s[10:11], s[8:9]
75 ; CHECK-NEXT: s_mov_b64 s[8:9], s[6:7]
76 ; CHECK-NEXT: s_getpc_b64 s[16:17]
77 ; CHECK-NEXT: s_add_u32 s16, s16, csr_vgpr_spill_fp_callee@rel32@lo+4
78 ; CHECK-NEXT: s_addc_u32 s17, s17, csr_vgpr_spill_fp_callee@rel32@hi+12
79 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
80 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
81 ; CHECK-NEXT: s_mov_b32 s6, 20
82 ; CHECK-NEXT: v_lshlrev_b32_e64 v2, s6, v2
83 ; CHECK-NEXT: s_mov_b32 s6, 10
84 ; CHECK-NEXT: v_lshlrev_b32_e64 v1, s6, v1
85 ; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2
86 ; CHECK-NEXT: ; implicit-def: $sgpr6_sgpr7
87 ; CHECK-NEXT: ; implicit-def: $sgpr15
88 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
89 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
90 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
91 ; CHECK-NEXT: s_endpgm
92 bb:
93 tail call fastcc void @csr_vgpr_spill_fp_callee()
94 ret void
95 }
97 ; Same, except with a tail call.
98 define internal fastcc void @csr_vgpr_spill_fp_tailcall_callee() #0 {
99 ; CHECK-LABEL: csr_vgpr_spill_fp_tailcall_callee:
100 ; CHECK: ; %bb.0: ; %bb
101 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
102 ; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1
103 ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
104 ; CHECK-NEXT: s_mov_b64 exec, s[16:17]
105 ; CHECK-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
106 ; CHECK-NEXT: v_writelane_b32 v1, s33, 0
107 ; CHECK-NEXT: ;;#ASMSTART
108 ; CHECK-NEXT: ; clobber csr v40
109 ; CHECK-NEXT: ;;#ASMEND
110 ; CHECK-NEXT: s_getpc_b64 s[16:17]
111 ; CHECK-NEXT: s_add_u32 s16, s16, callee_has_fp@rel32@lo+4
112 ; CHECK-NEXT: s_addc_u32 s17, s17, callee_has_fp@rel32@hi+12
113 ; CHECK-NEXT: v_readlane_b32 s33, v1, 0
114 ; CHECK-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
115 ; CHECK-NEXT: s_xor_saveexec_b64 s[18:19], -1
116 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
117 ; CHECK-NEXT: s_mov_b64 exec, s[18:19]
118 ; CHECK-NEXT: s_setpc_b64 s[16:17]
119 bb:
120 call void asm sideeffect "; clobber csr v40", "~{v40}"()
121 tail call fastcc void @callee_has_fp()
122 ret void
123 }
125 define amdgpu_kernel void @kernel_tailcall() {
126 ; CHECK-LABEL: kernel_tailcall:
127 ; CHECK: ; %bb.0: ; %bb
128 ; CHECK-NEXT: s_mov_b32 s32, 0
129 ; CHECK-NEXT: s_add_u32 flat_scratch_lo, s10, s15
130 ; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
131 ; CHECK-NEXT: s_add_u32 s0, s0, s15
132 ; CHECK-NEXT: s_addc_u32 s1, s1, 0
133 ; CHECK-NEXT: s_mov_b64 s[10:11], s[8:9]
134 ; CHECK-NEXT: s_mov_b64 s[8:9], s[6:7]
135 ; CHECK-NEXT: s_getpc_b64 s[16:17]
136 ; CHECK-NEXT: s_add_u32 s16, s16, csr_vgpr_spill_fp_tailcall_callee@rel32@lo+4
137 ; CHECK-NEXT: s_addc_u32 s17, s17, csr_vgpr_spill_fp_tailcall_callee@rel32@hi+12
138 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
139 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
140 ; CHECK-NEXT: s_mov_b32 s6, 20
141 ; CHECK-NEXT: v_lshlrev_b32_e64 v2, s6, v2
142 ; CHECK-NEXT: s_mov_b32 s6, 10
143 ; CHECK-NEXT: v_lshlrev_b32_e64 v1, s6, v1
144 ; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2
145 ; CHECK-NEXT: ; implicit-def: $sgpr6_sgpr7
146 ; CHECK-NEXT: ; implicit-def: $sgpr15
147 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
148 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
149 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
150 ; CHECK-NEXT: s_endpgm
151 bb:
152 tail call fastcc void @csr_vgpr_spill_fp_tailcall_callee()
153 ret void
154 }
156 define hidden i32 @tail_call() #1 {
157 ; CHECK-LABEL: tail_call:
158 ; CHECK: ; %bb.0: ; %entry
159 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
160 ; CHECK-NEXT: s_mov_b32 s4, s33
161 ; CHECK-NEXT: s_mov_b32 s33, s32
162 ; CHECK-NEXT: v_mov_b32_e32 v0, 0
163 ; CHECK-NEXT: s_mov_b32 s33, s4
164 ; CHECK-NEXT: s_setpc_b64 s[30:31]
165 entry:
166 ret i32 0
167 }
169 define hidden i32 @caller_save_vgpr_spill_fp_tail_call() #0 {
170 ; CHECK-LABEL: caller_save_vgpr_spill_fp_tail_call:
171 ; CHECK: ; %bb.0: ; %entry
172 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
173 ; CHECK-NEXT: s_mov_b32 s18, s33
174 ; CHECK-NEXT: s_mov_b32 s33, s32
175 ; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1
176 ; CHECK-NEXT: buffer_store_dword v1, off, s[0:3], s33 ; 4-byte Folded Spill
177 ; CHECK-NEXT: s_mov_b64 exec, s[16:17]
178 ; CHECK-NEXT: s_add_i32 s32, s32, 0x400
179 ; CHECK-NEXT: v_writelane_b32 v1, s30, 0
180 ; CHECK-NEXT: v_writelane_b32 v1, s31, 1
181 ; CHECK-NEXT: s_getpc_b64 s[16:17]
182 ; CHECK-NEXT: s_add_u32 s16, s16, tail_call@rel32@lo+4
183 ; CHECK-NEXT: s_addc_u32 s17, s17, tail_call@rel32@hi+12
184 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
185 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
186 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
187 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
188 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
189 ; CHECK-NEXT: v_readlane_b32 s31, v1, 1
190 ; CHECK-NEXT: v_readlane_b32 s30, v1, 0
191 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
192 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], s33 ; 4-byte Folded Reload
193 ; CHECK-NEXT: s_mov_b64 exec, s[4:5]
194 ; CHECK-NEXT: s_add_i32 s32, s32, 0xfffffc00
195 ; CHECK-NEXT: s_mov_b32 s33, s18
196 ; CHECK-NEXT: s_waitcnt vmcnt(0)
197 ; CHECK-NEXT: s_setpc_b64 s[30:31]
198 entry:
199 %call = call i32 @tail_call()
200 ret i32 %call
201 }
203 define hidden i32 @caller_save_vgpr_spill_fp() #0 {
204 ; CHECK-LABEL: caller_save_vgpr_spill_fp:
205 ; CHECK: ; %bb.0: ; %entry
206 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
207 ; CHECK-NEXT: s_mov_b32 s19, s33
208 ; CHECK-NEXT: s_mov_b32 s33, s32
209 ; CHECK-NEXT: s_xor_saveexec_b64 s[16:17], -1
210 ; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
211 ; CHECK-NEXT: s_mov_b64 exec, s[16:17]
212 ; CHECK-NEXT: s_add_i32 s32, s32, 0x400
213 ; CHECK-NEXT: v_writelane_b32 v2, s30, 0
214 ; CHECK-NEXT: v_writelane_b32 v2, s31, 1
215 ; CHECK-NEXT: s_getpc_b64 s[16:17]
216 ; CHECK-NEXT: s_add_u32 s16, s16, caller_save_vgpr_spill_fp_tail_call@rel32@lo+4
217 ; CHECK-NEXT: s_addc_u32 s17, s17, caller_save_vgpr_spill_fp_tail_call@rel32@hi+12
218 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
219 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
220 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
221 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
222 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
223 ; CHECK-NEXT: v_readlane_b32 s31, v2, 1
224 ; CHECK-NEXT: v_readlane_b32 s30, v2, 0
225 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
226 ; CHECK-NEXT: buffer_load_dword v2, off, s[0:3], s33 ; 4-byte Folded Reload
227 ; CHECK-NEXT: s_mov_b64 exec, s[4:5]
228 ; CHECK-NEXT: s_add_i32 s32, s32, 0xfffffc00
229 ; CHECK-NEXT: s_mov_b32 s33, s19
230 ; CHECK-NEXT: s_waitcnt vmcnt(0)
231 ; CHECK-NEXT: s_setpc_b64 s[30:31]
232 entry:
233 %call = call i32 @caller_save_vgpr_spill_fp_tail_call()
234 ret i32 %call
235 }
237 define protected amdgpu_kernel void @kernel() {
238 ; CHECK-LABEL: kernel:
239 ; CHECK: ; %bb.0: ; %entry
240 ; CHECK-NEXT: s_mov_b32 s32, 0
241 ; CHECK-NEXT: s_add_u32 flat_scratch_lo, s10, s15
242 ; CHECK-NEXT: s_addc_u32 flat_scratch_hi, s11, 0
243 ; CHECK-NEXT: s_add_u32 s0, s0, s15
244 ; CHECK-NEXT: s_addc_u32 s1, s1, 0
245 ; CHECK-NEXT: s_mov_b64 s[10:11], s[8:9]
246 ; CHECK-NEXT: s_mov_b64 s[8:9], s[6:7]
247 ; CHECK-NEXT: s_getpc_b64 s[16:17]
248 ; CHECK-NEXT: s_add_u32 s16, s16, caller_save_vgpr_spill_fp@rel32@lo+4
249 ; CHECK-NEXT: s_addc_u32 s17, s17, caller_save_vgpr_spill_fp@rel32@hi+12
250 ; CHECK-NEXT: s_mov_b64 s[22:23], s[2:3]
251 ; CHECK-NEXT: s_mov_b64 s[20:21], s[0:1]
252 ; CHECK-NEXT: s_mov_b32 s6, 20
253 ; CHECK-NEXT: v_lshlrev_b32_e64 v2, s6, v2
254 ; CHECK-NEXT: s_mov_b32 s6, 10
255 ; CHECK-NEXT: v_lshlrev_b32_e64 v1, s6, v1
256 ; CHECK-NEXT: v_or3_b32 v31, v0, v1, v2
257 ; CHECK-NEXT: ; implicit-def: $sgpr6_sgpr7
258 ; CHECK-NEXT: ; implicit-def: $sgpr15
259 ; CHECK-NEXT: s_mov_b64 s[0:1], s[20:21]
260 ; CHECK-NEXT: s_mov_b64 s[2:3], s[22:23]
261 ; CHECK-NEXT: s_swappc_b64 s[30:31], s[16:17]
262 ; CHECK-NEXT: s_endpgm
263 entry:
264 %call = call i32 @caller_save_vgpr_spill_fp()
265 ret void
266 }
268 attributes #0 = { "frame-pointer"="none" noinline }
269 attributes #1 = { "frame-pointer"="all" noinline }
271 !llvm.module.flags = !{!0}
272 !0 = !{i32 1, !"amdgpu_code_object_version", i32 500}