| blob | 81dd2c4457b2fbd858b63e06da91cd94fae36d39 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 -O0 -verify-machineinstrs -o - %s | FileCheck %s
4 ; Regression test for `processFunctionBeforeFrameFinalized`:
5 ; Check that it correctly updates RegisterScavenger so we
6 ; don't end up with bad machine code due to using undefined
7 ; physical registers.
9 define void @test() {
10 ; CHECK-LABEL: test:
11 ; CHECK: ; %bb.0: ; %bb.0
12 ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
13 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
14 ; CHECK-NEXT: buffer_store_dword v0, off, s[0:3], s32 ; 4-byte Folded Spill
15 ; CHECK-NEXT: s_mov_b64 exec, s[4:5]
16 ; CHECK-NEXT: ; implicit-def: $vgpr0 : SGPR spill to VGPR lane
17 ; CHECK-NEXT: .LBB0_1: ; %bb.1
18 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
19 ; CHECK-NEXT: s_cbranch_scc1 .LBB0_3
20 ; CHECK-NEXT: ; %bb.2: ; %bb.2
21 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
22 ; CHECK-NEXT: .LBB0_3: ; %bb.3
23 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
24 ; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -1
25 ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; Reload Reuse
26 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
27 ; CHECK-NEXT: ; implicit-def: $sgpr4
28 ; CHECK-NEXT: v_mov_b32_e32 v1, s4
29 ; CHECK-NEXT: v_readfirstlane_b32 s6, v1
30 ; CHECK-NEXT: s_mov_b64 s[4:5], -1
31 ; CHECK-NEXT: s_mov_b32 s7, 0
32 ; CHECK-NEXT: s_cmp_eq_u32 s6, s7
33 ; CHECK-NEXT: v_writelane_b32 v0, s4, 0
34 ; CHECK-NEXT: v_writelane_b32 v0, s5, 1
35 ; CHECK-NEXT: s_mov_b64 s[10:11], exec
36 ; CHECK-NEXT: s_mov_b64 exec, -1
37 ; CHECK-NEXT: v_accvgpr_write_b32 a0, v0 ; Reload Reuse
38 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
39 ; CHECK-NEXT: s_cbranch_scc1 .LBB0_5
40 ; CHECK-NEXT: ; %bb.4: ; %bb.4
41 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
42 ; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -1
43 ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; Reload Reuse
44 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
45 ; CHECK-NEXT: s_mov_b64 s[4:5], 0
46 ; CHECK-NEXT: v_writelane_b32 v0, s4, 0
47 ; CHECK-NEXT: v_writelane_b32 v0, s5, 1
48 ; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -1
49 ; CHECK-NEXT: s_nop 0
50 ; CHECK-NEXT: v_accvgpr_write_b32 a0, v0 ; Reload Reuse
51 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
52 ; CHECK-NEXT: .LBB0_5: ; %Flow
53 ; CHECK-NEXT: ; in Loop: Header=BB0_1 Depth=1
54 ; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -1
55 ; CHECK-NEXT: s_nop 0
56 ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; Reload Reuse
57 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
58 ; CHECK-NEXT: v_readlane_b32 s4, v0, 0
59 ; CHECK-NEXT: v_readlane_b32 s5, v0, 1
60 ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
61 ; CHECK-NEXT: s_mov_b32 s4, 1
62 ; CHECK-NEXT: ; implicit-def: $sgpr5
63 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[4:5], v0, s4
64 ; CHECK-NEXT: s_and_b64 vcc, exec, s[4:5]
65 ; CHECK-NEXT: s_cbranch_vccnz .LBB0_1
66 ; CHECK-NEXT: ; %bb.6: ; %bb.5
67 ; CHECK-NEXT: s_or_saveexec_b64 s[10:11], -1
68 ; CHECK-NEXT: v_accvgpr_read_b32 v0, a0 ; Reload Reuse
69 ; CHECK-NEXT: s_mov_b64 exec, s[10:11]
70 ; CHECK-NEXT: ; kill: killed $vgpr0
71 ; CHECK-NEXT: s_xor_saveexec_b64 s[4:5], -1
72 ; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload
73 ; CHECK-NEXT: s_mov_b64 exec, s[4:5]
74 ; CHECK-NEXT: s_waitcnt vmcnt(0)
75 ; CHECK-NEXT: s_setpc_b64 s[30:31]
76 bb.0:
77 br label %bb.1
78 bb.1: ; preds = %bb.4, %bb.0
79 br i1 poison, label %bb.2, label %bb.3
80 bb.2: ; preds = %bb.1
81 br label %bb.3
82 bb.3: ; preds = %bb.2, %bb.1
83 %call = tail call i32 @llvm.amdgcn.readfirstlane(i32 poison)
84 %cmp = icmp eq i32 %call, 0
85 br i1 %cmp, label %bb.5, label %bb.4
86 bb.4: ; preds = %bb.3
87 br label %bb.1
88 bb.5: ; preds = %bb.3
89 ret void
90 }
92 declare i32 @llvm.amdgcn.readfirstlane(i32)