| blob | e7db8ef9d5aff37fa3d06e21eda1cc8009f55fe0 |
1 ; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
2 ; RUN: grep -v "Verify generated machine code" | \
3 ; RUN: FileCheck %s --check-prefixes=CHECK
4 ; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \
5 ; RUN: grep -v "Verify generated machine code" | \
6 ; RUN: FileCheck %s --check-prefixes=CHECK,RV64
8 ; REQUIRES: asserts
10 ; CHECK-LABEL: Pass Arguments:
11 ; CHECK-NEXT: Target Library Information
12 ; CHECK-NEXT: Target Pass Configuration
13 ; CHECK-NEXT: Machine Module Information
14 ; CHECK-NEXT: Target Transform Information
15 ; CHECK-NEXT: Assumption Cache Tracker
16 ; CHECK-NEXT: Profile summary info
17 ; CHECK-NEXT: Type-Based Alias Analysis
18 ; CHECK-NEXT: Scoped NoAlias Alias Analysis
19 ; CHECK-NEXT: Create Garbage Collector Module Metadata
20 ; CHECK-NEXT: Machine Branch Probability Analysis
21 ; CHECK-NEXT: Default Regalloc Eviction Advisor
22 ; CHECK-NEXT: Default Regalloc Priority Advisor
23 ; CHECK-NEXT: ModulePass Manager
24 ; CHECK-NEXT: Pre-ISel Intrinsic Lowering
25 ; CHECK-NEXT: FunctionPass Manager
26 ; CHECK-NEXT: Expand large div/rem
27 ; CHECK-NEXT: Expand large fp convert
28 ; CHECK-NEXT: Expand Atomic instructions
29 ; CHECK-NEXT: Dominator Tree Construction
30 ; CHECK-NEXT: Natural Loop Information
31 ; CHECK-NEXT: Canonicalize natural loops
32 ; CHECK-NEXT: Lazy Branch Probability Analysis
33 ; CHECK-NEXT: Lazy Block Frequency Analysis
34 ; CHECK-NEXT: Optimization Remark Emitter
35 ; CHECK-NEXT: Scalar Evolution Analysis
36 ; CHECK-NEXT: Loop Data Prefetch
37 ; CHECK-NEXT: RISC-V gather/scatter lowering
38 ; CHECK-NEXT: Interleaved Access Pass
39 ; CHECK-NEXT: RISC-V CodeGenPrepare
40 ; CHECK-NEXT: Module Verifier
41 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
42 ; CHECK-NEXT: Canonicalize natural loops
43 ; CHECK-NEXT: Scalar Evolution Analysis
44 ; CHECK-NEXT: Loop Pass Manager
45 ; CHECK-NEXT: Canonicalize Freeze Instructions in Loops
46 ; CHECK-NEXT: Induction Variable Users
47 ; CHECK-NEXT: Loop Strength Reduction
48 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
49 ; CHECK-NEXT: Function Alias Analysis Results
50 ; CHECK-NEXT: Merge contiguous icmps into a memcmp
51 ; CHECK-NEXT: Natural Loop Information
52 ; CHECK-NEXT: Lazy Branch Probability Analysis
53 ; CHECK-NEXT: Lazy Block Frequency Analysis
54 ; CHECK-NEXT: Expand memcmp() to load/stores
55 ; CHECK-NEXT: Lower Garbage Collection Instructions
56 ; CHECK-NEXT: Shadow Stack GC Lowering
57 ; CHECK-NEXT: Lower constant intrinsics
58 ; CHECK-NEXT: Remove unreachable blocks from the CFG
59 ; CHECK-NEXT: Natural Loop Information
60 ; CHECK-NEXT: Post-Dominator Tree Construction
61 ; CHECK-NEXT: Branch Probability Analysis
62 ; CHECK-NEXT: Block Frequency Analysis
63 ; CHECK-NEXT: Constant Hoisting
64 ; CHECK-NEXT: Replace intrinsics with calls to vector library
65 ; CHECK-NEXT: Partially inline calls to library functions
66 ; CHECK-NEXT: Expand vector predication intrinsics
67 ; CHECK-NEXT: Scalarize Masked Memory Intrinsics
68 ; CHECK-NEXT: Expand reduction intrinsics
69 ; CHECK-NEXT: Natural Loop Information
70 ; CHECK-NEXT: TLS Variable Hoist
71 ; CHECK-NEXT: CodeGen Prepare
72 ; CHECK-NEXT: Dominator Tree Construction
73 ; CHECK-NEXT: Exception handling preparation
74 ; CHECK-NEXT: A No-Op Barrier Pass
75 ; CHECK-NEXT: FunctionPass Manager
76 ; CHECK-NEXT: Prepare callbr
77 ; CHECK-NEXT: Safe Stack instrumentation pass
78 ; CHECK-NEXT: Insert stack protectors
79 ; CHECK-NEXT: Module Verifier
80 ; CHECK-NEXT: Dominator Tree Construction
81 ; CHECK-NEXT: Basic Alias Analysis (stateless AA impl)
82 ; CHECK-NEXT: Function Alias Analysis Results
83 ; CHECK-NEXT: Natural Loop Information
84 ; CHECK-NEXT: Post-Dominator Tree Construction
85 ; CHECK-NEXT: Branch Probability Analysis
86 ; CHECK-NEXT: Assignment Tracking Analysis
87 ; CHECK-NEXT: Lazy Branch Probability Analysis
88 ; CHECK-NEXT: Lazy Block Frequency Analysis
89 ; CHECK-NEXT: RISC-V DAG->DAG Pattern Instruction Selection
90 ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions
91 ; CHECK-NEXT: RISC-V Fold Masks
92 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
93 ; CHECK-NEXT: Early Tail Duplication
94 ; CHECK-NEXT: Optimize machine instruction PHIs
95 ; CHECK-NEXT: Slot index numbering
96 ; CHECK-NEXT: Merge disjoint stack slots
97 ; CHECK-NEXT: Local Stack Slot Allocation
98 ; CHECK-NEXT: Remove dead machine instructions
99 ; CHECK-NEXT: MachineDominator Tree Construction
100 ; CHECK-NEXT: Machine Natural Loop Construction
101 ; CHECK-NEXT: Machine Block Frequency Analysis
102 ; CHECK-NEXT: Early Machine Loop Invariant Code Motion
103 ; CHECK-NEXT: MachineDominator Tree Construction
104 ; CHECK-NEXT: Machine Block Frequency Analysis
105 ; CHECK-NEXT: Machine Common Subexpression Elimination
106 ; CHECK-NEXT: MachinePostDominator Tree Construction
107 ; CHECK-NEXT: Machine Cycle Info Analysis
108 ; CHECK-NEXT: Machine code sinking
109 ; CHECK-NEXT: Peephole Optimizations
110 ; CHECK-NEXT: Remove dead machine instructions
111 ; CHECK-NEXT: Machine Trace Metrics
112 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
113 ; CHECK-NEXT: Machine InstCombiner
114 ; RV64-NEXT: RISC-V Optimize W Instructions
115 ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass
116 ; CHECK-NEXT: RISC-V Merge Base Offset
117 ; CHECK-NEXT: RISC-V Insert VSETVLI pass
118 ; CHECK-NEXT: RISC-V Dead register definitions
119 ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass
120 ; CHECK-NEXT: RISC-V Insert Write VXRM Pass
121 ; CHECK-NEXT: Detect Dead Lanes
122 ; CHECK-NEXT: RISC-V init undef pass
123 ; CHECK-NEXT: Process Implicit Definitions
124 ; CHECK-NEXT: Remove unreachable machine basic blocks
125 ; CHECK-NEXT: Live Variable Analysis
126 ; CHECK-NEXT: Eliminate PHI nodes for register allocation
127 ; CHECK-NEXT: Two-Address instruction pass
128 ; CHECK-NEXT: MachineDominator Tree Construction
129 ; CHECK-NEXT: Slot index numbering
130 ; CHECK-NEXT: Live Interval Analysis
131 ; CHECK-NEXT: Register Coalescer
132 ; CHECK-NEXT: Rename Disconnected Subregister Components
133 ; CHECK-NEXT: Machine Instruction Scheduler
134 ; CHECK-NEXT: Machine Block Frequency Analysis
135 ; CHECK-NEXT: Debug Variable Analysis
136 ; CHECK-NEXT: Live Stack Slot Analysis
137 ; CHECK-NEXT: Virtual Register Map
138 ; CHECK-NEXT: Live Register Matrix
139 ; CHECK-NEXT: Bundle Machine CFG Edges
140 ; CHECK-NEXT: Spill Code Placement Analysis
141 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
142 ; CHECK-NEXT: Machine Optimization Remark Emitter
143 ; CHECK-NEXT: Greedy Register Allocator
144 ; CHECK-NEXT: Virtual Register Rewriter
145 ; CHECK-NEXT: Virtual Register Map
146 ; CHECK-NEXT: Live Register Matrix
147 ; CHECK-NEXT: Greedy Register Allocator
148 ; CHECK-NEXT: Virtual Register Rewriter
149 ; CHECK-NEXT: Register Allocation Pass Scoring
150 ; CHECK-NEXT: Stack Slot Coloring
151 ; CHECK-NEXT: Machine Copy Propagation Pass
152 ; CHECK-NEXT: Machine Loop Invariant Code Motion
153 ; CHECK-NEXT: RISC-V Redundant Copy Elimination
154 ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis
155 ; CHECK-NEXT: Fixup Statepoint Caller Saved
156 ; CHECK-NEXT: PostRA Machine Sink
157 ; CHECK-NEXT: MachineDominator Tree Construction
158 ; CHECK-NEXT: Machine Natural Loop Construction
159 ; CHECK-NEXT: Machine Block Frequency Analysis
160 ; CHECK-NEXT: MachinePostDominator Tree Construction
161 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
162 ; CHECK-NEXT: Machine Optimization Remark Emitter
163 ; CHECK-NEXT: Shrink Wrapping analysis
164 ; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization
165 ; CHECK-NEXT: Machine Late Instructions Cleanup Pass
166 ; CHECK-NEXT: Control Flow Optimizer
167 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
168 ; CHECK-NEXT: Tail Duplication
169 ; CHECK-NEXT: Machine Copy Propagation Pass
170 ; CHECK-NEXT: Post-RA pseudo instruction expansion pass
171 ; CHECK-NEXT: RISC-V post-regalloc pseudo instruction expansion pass
172 ; CHECK-NEXT: Insert KCFI indirect call checks
173 ; CHECK-NEXT: MachineDominator Tree Construction
174 ; CHECK-NEXT: Machine Natural Loop Construction
175 ; CHECK-NEXT: PostRA Machine Instruction Scheduler
176 ; CHECK-NEXT: Analyze Machine Code For Garbage Collection
177 ; CHECK-NEXT: Machine Block Frequency Analysis
178 ; CHECK-NEXT: MachinePostDominator Tree Construction
179 ; CHECK-NEXT: Branch Probability Basic Block Placement
180 ; CHECK-NEXT: Insert fentry calls
181 ; CHECK-NEXT: Insert XRay ops
182 ; CHECK-NEXT: Implement the 'patchable-function' attribute
183 ; CHECK-NEXT: Branch relaxation pass
184 ; CHECK-NEXT: RISC-V Make Compressible
185 ; CHECK-NEXT: Machine Copy Propagation Pass
186 ; CHECK-NEXT: Contiguously Lay Out Funclets
187 ; CHECK-NEXT: StackMap Liveness Analysis
188 ; CHECK-NEXT: Live DEBUG_VALUE analysis
189 ; CHECK-NEXT: Machine Sanitizer Binary Metadata
190 ; CHECK-NEXT: Machine Outliner
191 ; CHECK-NEXT: FunctionPass Manager
192 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
193 ; CHECK-NEXT: Machine Optimization Remark Emitter
194 ; CHECK-NEXT: Stack Frame Layout Analysis
195 ; CHECK-NEXT: RISC-V Zcmp move merging pass
196 ; CHECK-NEXT: RISC-V Zcmp Push/Pop optimization pass
197 ; CHECK-NEXT: RISC-V pseudo instruction expansion pass
198 ; CHECK-NEXT: RISC-V atomic pseudo instruction expansion pass
199 ; CHECK-NEXT: Unpack machine instruction bundles
200 ; CHECK-NEXT: Lazy Machine Block Frequency Analysis
201 ; CHECK-NEXT: Machine Optimization Remark Emitter
202 ; CHECK-NEXT: RISC-V Assembly Printer
203 ; CHECK-NEXT: Free MachineFunction