| blob | b0d60a7aaa235f2b806e2118ecad0e15183f2513 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
3 ; RUN: -target-abi ilp32f < %s \
4 ; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
5 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+d \
6 ; RUN: -target-abi ilp32d < %s \
7 ; RUN: | FileCheck -check-prefix=RV32-ILP32FD %s
9 ; This file contains tests that should have identical output for the ilp32f
10 ; and ilp32d ABIs.
12 define i32 @callee_float_in_fpr(i32 %a, float %b) nounwind {
13 ; RV32-ILP32FD-LABEL: callee_float_in_fpr:
14 ; RV32-ILP32FD: # %bb.0:
15 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
16 ; RV32-ILP32FD-NEXT: add a0, a0, a1
17 ; RV32-ILP32FD-NEXT: ret
18 %b_fptosi = fptosi float %b to i32
19 %1 = add i32 %a, %b_fptosi
20 ret i32 %1
21 }
23 define i32 @caller_float_in_fpr() nounwind {
24 ; RV32-ILP32FD-LABEL: caller_float_in_fpr:
25 ; RV32-ILP32FD: # %bb.0:
26 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
27 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
28 ; RV32-ILP32FD-NEXT: lui a0, 262144
29 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
30 ; RV32-ILP32FD-NEXT: li a0, 1
31 ; RV32-ILP32FD-NEXT: call callee_float_in_fpr
32 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
33 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
34 ; RV32-ILP32FD-NEXT: ret
35 %1 = call i32 @callee_float_in_fpr(i32 1, float 2.0)
36 ret i32 %1
37 }
39 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
40 define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {
41 ; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:
42 ; RV32-ILP32FD: # %bb.0:
43 ; RV32-ILP32FD-NEXT: lw a0, 0(sp)
44 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
45 ; RV32-ILP32FD-NEXT: add a0, a0, a1
46 ; RV32-ILP32FD-NEXT: ret
47 %f_fptosi = fptosi float %f to i32
48 %1 = add i32 %e, %f_fptosi
49 ret i32 %1
50 }
52 define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
53 ; RV32-ILP32FD-LABEL: caller_float_in_fpr_exhausted_gprs:
54 ; RV32-ILP32FD: # %bb.0:
55 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
56 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
57 ; RV32-ILP32FD-NEXT: li a1, 5
58 ; RV32-ILP32FD-NEXT: lui a0, 265216
59 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
60 ; RV32-ILP32FD-NEXT: li a0, 1
61 ; RV32-ILP32FD-NEXT: li a2, 2
62 ; RV32-ILP32FD-NEXT: li a4, 3
63 ; RV32-ILP32FD-NEXT: li a6, 4
64 ; RV32-ILP32FD-NEXT: sw a1, 0(sp)
65 ; RV32-ILP32FD-NEXT: li a1, 0
66 ; RV32-ILP32FD-NEXT: li a3, 0
67 ; RV32-ILP32FD-NEXT: li a5, 0
68 ; RV32-ILP32FD-NEXT: li a7, 0
69 ; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
70 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
71 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
72 ; RV32-ILP32FD-NEXT: ret
73 %1 = call i32 @callee_float_in_fpr_exhausted_gprs(
74 i64 1, i64 2, i64 3, i64 4, i32 5, float 6.0)
75 ret i32 %1
76 }
78 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
79 define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
80 ; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
81 ; RV32-ILP32FD: # %bb.0:
82 ; RV32-ILP32FD-NEXT: fmv.w.x fa5, a0
83 ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
84 ; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa5, rtz
85 ; RV32-ILP32FD-NEXT: add a0, a0, a1
86 ; RV32-ILP32FD-NEXT: ret
87 %h_fptosi = fptosi float %h to i32
88 %i_fptosi = fptosi float %i to i32
89 %1 = add i32 %h_fptosi, %i_fptosi
90 ret i32 %1
91 }
93 define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
94 ; RV32-ILP32FD-LABEL: caller_float_in_gpr_exhausted_fprs:
95 ; RV32-ILP32FD: # %bb.0:
96 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
97 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
98 ; RV32-ILP32FD-NEXT: lui a0, 260096
99 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
100 ; RV32-ILP32FD-NEXT: lui a0, 262144
101 ; RV32-ILP32FD-NEXT: fmv.w.x fa1, a0
102 ; RV32-ILP32FD-NEXT: lui a0, 263168
103 ; RV32-ILP32FD-NEXT: fmv.w.x fa2, a0
104 ; RV32-ILP32FD-NEXT: lui a0, 264192
105 ; RV32-ILP32FD-NEXT: fmv.w.x fa3, a0
106 ; RV32-ILP32FD-NEXT: lui a0, 264704
107 ; RV32-ILP32FD-NEXT: fmv.w.x fa4, a0
108 ; RV32-ILP32FD-NEXT: lui a0, 265216
109 ; RV32-ILP32FD-NEXT: fmv.w.x fa5, a0
110 ; RV32-ILP32FD-NEXT: lui a0, 265728
111 ; RV32-ILP32FD-NEXT: fmv.w.x fa6, a0
112 ; RV32-ILP32FD-NEXT: lui a0, 266240
113 ; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0
114 ; RV32-ILP32FD-NEXT: lui a0, 266496
115 ; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
116 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
117 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
118 ; RV32-ILP32FD-NEXT: ret
119 %1 = call i32 @callee_float_in_gpr_exhausted_fprs(
120 float 1.0, float 2.0, float 3.0, float 4.0, float 5.0, float 6.0,
121 float 7.0, float 8.0, float 9.0)
122 ret i32 %1
123 }
125 ; Must keep define on a single line due to an update_llc_test_checks.py limitation
126 define i32 @callee_float_on_stack_exhausted_gprs_fprs(i64 %a, float %b, i64 %c, float %d, i64 %e, float %f, i64 %g, float %h, float %i, float %j, float %k, float %l, float %m) nounwind {
127 ; RV32-ILP32FD-LABEL: callee_float_on_stack_exhausted_gprs_fprs:
128 ; RV32-ILP32FD: # %bb.0:
129 ; RV32-ILP32FD-NEXT: flw fa5, 0(sp)
130 ; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa5, rtz
131 ; RV32-ILP32FD-NEXT: add a0, a6, a0
132 ; RV32-ILP32FD-NEXT: ret
133 %g_trunc = trunc i64 %g to i32
134 %m_fptosi = fptosi float %m to i32
135 %1 = add i32 %g_trunc, %m_fptosi
136 ret i32 %1
137 }
139 define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
140 ; RV32-ILP32FD-LABEL: caller_float_on_stack_exhausted_gprs_fprs:
141 ; RV32-ILP32FD: # %bb.0:
142 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
143 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
144 ; RV32-ILP32FD-NEXT: lui a1, 267520
145 ; RV32-ILP32FD-NEXT: lui a0, 262144
146 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
147 ; RV32-ILP32FD-NEXT: lui a0, 264192
148 ; RV32-ILP32FD-NEXT: fmv.w.x fa1, a0
149 ; RV32-ILP32FD-NEXT: lui a0, 265216
150 ; RV32-ILP32FD-NEXT: fmv.w.x fa2, a0
151 ; RV32-ILP32FD-NEXT: lui a0, 266240
152 ; RV32-ILP32FD-NEXT: fmv.w.x fa3, a0
153 ; RV32-ILP32FD-NEXT: lui a0, 266496
154 ; RV32-ILP32FD-NEXT: fmv.w.x fa4, a0
155 ; RV32-ILP32FD-NEXT: lui a0, 266752
156 ; RV32-ILP32FD-NEXT: fmv.w.x fa5, a0
157 ; RV32-ILP32FD-NEXT: lui a0, 267008
158 ; RV32-ILP32FD-NEXT: fmv.w.x fa6, a0
159 ; RV32-ILP32FD-NEXT: lui a0, 267264
160 ; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0
161 ; RV32-ILP32FD-NEXT: li a0, 1
162 ; RV32-ILP32FD-NEXT: li a2, 3
163 ; RV32-ILP32FD-NEXT: li a4, 5
164 ; RV32-ILP32FD-NEXT: li a6, 7
165 ; RV32-ILP32FD-NEXT: sw a1, 0(sp)
166 ; RV32-ILP32FD-NEXT: li a1, 0
167 ; RV32-ILP32FD-NEXT: li a3, 0
168 ; RV32-ILP32FD-NEXT: li a5, 0
169 ; RV32-ILP32FD-NEXT: li a7, 0
170 ; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
171 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
172 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
173 ; RV32-ILP32FD-NEXT: ret
174 %1 = call i32 @callee_float_on_stack_exhausted_gprs_fprs(
175 i64 1, float 2.0, i64 3, float 4.0, i64 5, float 6.0, i64 7, float 8.0,
176 float 9.0, float 10.0, float 11.0, float 12.0, float 13.0)
177 ret i32 %1
178 }
180 define float @callee_float_ret() nounwind {
181 ; RV32-ILP32FD-LABEL: callee_float_ret:
182 ; RV32-ILP32FD: # %bb.0:
183 ; RV32-ILP32FD-NEXT: lui a0, 260096
184 ; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
185 ; RV32-ILP32FD-NEXT: ret
186 ret float 1.0
187 }
189 define i32 @caller_float_ret() nounwind {
190 ; RV32-ILP32FD-LABEL: caller_float_ret:
191 ; RV32-ILP32FD: # %bb.0:
192 ; RV32-ILP32FD-NEXT: addi sp, sp, -16
193 ; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
194 ; RV32-ILP32FD-NEXT: call callee_float_ret
195 ; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0
196 ; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
197 ; RV32-ILP32FD-NEXT: addi sp, sp, 16
198 ; RV32-ILP32FD-NEXT: ret
199 %1 = call float @callee_float_ret()
200 %2 = bitcast float %1 to i32
201 ret i32 %2
202 }