| blob | accd52369fa1cdd4521422ca31df67d2828a4a65 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck %s -check-prefix=RV32I
4 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck %s -check-prefix=RV64I
6 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
7 ; RUN: -target-abi ilp32f < %s | FileCheck %s -check-prefix=RV32IF
8 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
9 ; RUN: -target-abi ilp32d < %s | FileCheck %s -check-prefix=RV32IFD
10 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
11 ; RUN: -target-abi lp64d < %s | FileCheck %s -check-prefix=RV64IFD
12 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
13 ; RUN: -mattr=+zfh -target-abi ilp32f < %s \
14 ; RUN: | FileCheck %s -check-prefix=RV32IFZFH
15 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
16 ; RUN: -mattr=+zfh -target-abi ilp32d < %s \
17 ; RUN: | FileCheck %s -check-prefix=RV32IFDZFH
18 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
19 ; RUN: -mattr=+zfh -target-abi lp64d < %s \
20 ; RUN: | FileCheck %s -check-prefix=RV64IFDZFH
21 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f \
22 ; RUN: -mattr=+zfhmin -target-abi ilp32f < %s \
23 ; RUN: | FileCheck %s -check-prefix=RV32IFZFHMIN
24 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs -mattr=+f -mattr=+d \
25 ; RUN: -mattr=+zfhmin -target-abi ilp32d < %s \
26 ; RUN: | FileCheck %s -check-prefix=RV32IFDZFHMIN
27 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs -mattr=+f -mattr=+d \
28 ; RUN: -mattr=+zfhmin -target-abi lp64d < %s \
29 ; RUN: | FileCheck %s -check-prefix=RV64IFDZFHMIN
31 ; Test fcopysign scenarios where the sign argument is casted to the type of the
32 ; magnitude argument. Those casts can be folded away by the DAGCombiner.
34 declare double @llvm.copysign.f64(double, double)
35 declare float @llvm.copysign.f32(float, float)
36 declare half @llvm.copysign.f16(half, half)
38 define double @fold_promote_d_s(double %a, float %b) nounwind {
39 ; RV32I-LABEL: fold_promote_d_s:
40 ; RV32I: # %bb.0:
41 ; RV32I-NEXT: lui a3, 524288
42 ; RV32I-NEXT: and a2, a2, a3
43 ; RV32I-NEXT: slli a1, a1, 1
44 ; RV32I-NEXT: srli a1, a1, 1
45 ; RV32I-NEXT: or a1, a1, a2
46 ; RV32I-NEXT: ret
47 ;
48 ; RV64I-LABEL: fold_promote_d_s:
49 ; RV64I: # %bb.0:
50 ; RV64I-NEXT: lui a2, 524288
51 ; RV64I-NEXT: and a1, a1, a2
52 ; RV64I-NEXT: slli a1, a1, 32
53 ; RV64I-NEXT: slli a0, a0, 1
54 ; RV64I-NEXT: srli a0, a0, 1
55 ; RV64I-NEXT: or a0, a0, a1
56 ; RV64I-NEXT: ret
57 ;
58 ; RV32IF-LABEL: fold_promote_d_s:
59 ; RV32IF: # %bb.0:
60 ; RV32IF-NEXT: fmv.x.w a2, fa0
61 ; RV32IF-NEXT: lui a3, 524288
62 ; RV32IF-NEXT: and a2, a2, a3
63 ; RV32IF-NEXT: slli a1, a1, 1
64 ; RV32IF-NEXT: srli a1, a1, 1
65 ; RV32IF-NEXT: or a1, a1, a2
66 ; RV32IF-NEXT: ret
67 ;
68 ; RV32IFD-LABEL: fold_promote_d_s:
69 ; RV32IFD: # %bb.0:
70 ; RV32IFD-NEXT: fcvt.d.s fa5, fa1
71 ; RV32IFD-NEXT: fsgnj.d fa0, fa0, fa5
72 ; RV32IFD-NEXT: ret
73 ;
74 ; RV64IFD-LABEL: fold_promote_d_s:
75 ; RV64IFD: # %bb.0:
76 ; RV64IFD-NEXT: fcvt.d.s fa5, fa1
77 ; RV64IFD-NEXT: fsgnj.d fa0, fa0, fa5
78 ; RV64IFD-NEXT: ret
79 ;
80 ; RV32IFZFH-LABEL: fold_promote_d_s:
81 ; RV32IFZFH: # %bb.0:
82 ; RV32IFZFH-NEXT: fmv.x.w a2, fa0
83 ; RV32IFZFH-NEXT: lui a3, 524288
84 ; RV32IFZFH-NEXT: and a2, a2, a3
85 ; RV32IFZFH-NEXT: slli a1, a1, 1
86 ; RV32IFZFH-NEXT: srli a1, a1, 1
87 ; RV32IFZFH-NEXT: or a1, a1, a2
88 ; RV32IFZFH-NEXT: ret
89 ;
90 ; RV32IFDZFH-LABEL: fold_promote_d_s:
91 ; RV32IFDZFH: # %bb.0:
92 ; RV32IFDZFH-NEXT: fcvt.d.s fa5, fa1
93 ; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa5
94 ; RV32IFDZFH-NEXT: ret
95 ;
96 ; RV64IFDZFH-LABEL: fold_promote_d_s:
97 ; RV64IFDZFH: # %bb.0:
98 ; RV64IFDZFH-NEXT: fcvt.d.s fa5, fa1
99 ; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa5
100 ; RV64IFDZFH-NEXT: ret
101 ;
102 ; RV32IFZFHMIN-LABEL: fold_promote_d_s:
103 ; RV32IFZFHMIN: # %bb.0:
104 ; RV32IFZFHMIN-NEXT: fmv.x.w a2, fa0
105 ; RV32IFZFHMIN-NEXT: lui a3, 524288
106 ; RV32IFZFHMIN-NEXT: and a2, a2, a3
107 ; RV32IFZFHMIN-NEXT: slli a1, a1, 1
108 ; RV32IFZFHMIN-NEXT: srli a1, a1, 1
109 ; RV32IFZFHMIN-NEXT: or a1, a1, a2
110 ; RV32IFZFHMIN-NEXT: ret
111 ;
112 ; RV32IFDZFHMIN-LABEL: fold_promote_d_s:
113 ; RV32IFDZFHMIN: # %bb.0:
114 ; RV32IFDZFHMIN-NEXT: fcvt.d.s fa5, fa1
115 ; RV32IFDZFHMIN-NEXT: fsgnj.d fa0, fa0, fa5
116 ; RV32IFDZFHMIN-NEXT: ret
117 ;
118 ; RV64IFDZFHMIN-LABEL: fold_promote_d_s:
119 ; RV64IFDZFHMIN: # %bb.0:
120 ; RV64IFDZFHMIN-NEXT: fcvt.d.s fa5, fa1
121 ; RV64IFDZFHMIN-NEXT: fsgnj.d fa0, fa0, fa5
122 ; RV64IFDZFHMIN-NEXT: ret
123 %c = fpext float %b to double
124 %t = call double @llvm.copysign.f64(double %a, double %c)
125 ret double %t
126 }
128 define double @fold_promote_d_h(double %a, half %b) nounwind {
129 ; RV32I-LABEL: fold_promote_d_h:
130 ; RV32I: # %bb.0:
131 ; RV32I-NEXT: lui a3, 8
132 ; RV32I-NEXT: and a2, a2, a3
133 ; RV32I-NEXT: slli a2, a2, 16
134 ; RV32I-NEXT: slli a1, a1, 1
135 ; RV32I-NEXT: srli a1, a1, 1
136 ; RV32I-NEXT: or a1, a1, a2
137 ; RV32I-NEXT: ret
138 ;
139 ; RV64I-LABEL: fold_promote_d_h:
140 ; RV64I: # %bb.0:
141 ; RV64I-NEXT: lui a2, 8
142 ; RV64I-NEXT: and a1, a1, a2
143 ; RV64I-NEXT: slli a1, a1, 48
144 ; RV64I-NEXT: slli a0, a0, 1
145 ; RV64I-NEXT: srli a0, a0, 1
146 ; RV64I-NEXT: or a0, a0, a1
147 ; RV64I-NEXT: ret
148 ;
149 ; RV32IF-LABEL: fold_promote_d_h:
150 ; RV32IF: # %bb.0:
151 ; RV32IF-NEXT: fmv.x.w a2, fa0
152 ; RV32IF-NEXT: lui a3, 8
153 ; RV32IF-NEXT: and a2, a2, a3
154 ; RV32IF-NEXT: slli a2, a2, 16
155 ; RV32IF-NEXT: slli a1, a1, 1
156 ; RV32IF-NEXT: srli a1, a1, 1
157 ; RV32IF-NEXT: or a1, a1, a2
158 ; RV32IF-NEXT: ret
159 ;
160 ; RV32IFD-LABEL: fold_promote_d_h:
161 ; RV32IFD: # %bb.0:
162 ; RV32IFD-NEXT: addi sp, sp, -16
163 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
164 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
165 ; RV32IFD-NEXT: fmv.d fs0, fa0
166 ; RV32IFD-NEXT: fmv.s fa0, fa1
167 ; RV32IFD-NEXT: call __extendhfsf2
168 ; RV32IFD-NEXT: fcvt.d.s fa5, fa0
169 ; RV32IFD-NEXT: fsgnj.d fa0, fs0, fa5
170 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
171 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
172 ; RV32IFD-NEXT: addi sp, sp, 16
173 ; RV32IFD-NEXT: ret
174 ;
175 ; RV64IFD-LABEL: fold_promote_d_h:
176 ; RV64IFD: # %bb.0:
177 ; RV64IFD-NEXT: addi sp, sp, -16
178 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
179 ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
180 ; RV64IFD-NEXT: fmv.d fs0, fa0
181 ; RV64IFD-NEXT: fmv.s fa0, fa1
182 ; RV64IFD-NEXT: call __extendhfsf2
183 ; RV64IFD-NEXT: fcvt.d.s fa5, fa0
184 ; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa5
185 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
186 ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
187 ; RV64IFD-NEXT: addi sp, sp, 16
188 ; RV64IFD-NEXT: ret
189 ;
190 ; RV32IFZFH-LABEL: fold_promote_d_h:
191 ; RV32IFZFH: # %bb.0:
192 ; RV32IFZFH-NEXT: fmv.x.h a2, fa0
193 ; RV32IFZFH-NEXT: lui a3, 8
194 ; RV32IFZFH-NEXT: and a2, a2, a3
195 ; RV32IFZFH-NEXT: slli a2, a2, 16
196 ; RV32IFZFH-NEXT: slli a1, a1, 1
197 ; RV32IFZFH-NEXT: srli a1, a1, 1
198 ; RV32IFZFH-NEXT: or a1, a1, a2
199 ; RV32IFZFH-NEXT: ret
200 ;
201 ; RV32IFDZFH-LABEL: fold_promote_d_h:
202 ; RV32IFDZFH: # %bb.0:
203 ; RV32IFDZFH-NEXT: fcvt.d.h fa5, fa1
204 ; RV32IFDZFH-NEXT: fsgnj.d fa0, fa0, fa5
205 ; RV32IFDZFH-NEXT: ret
206 ;
207 ; RV64IFDZFH-LABEL: fold_promote_d_h:
208 ; RV64IFDZFH: # %bb.0:
209 ; RV64IFDZFH-NEXT: fcvt.d.h fa5, fa1
210 ; RV64IFDZFH-NEXT: fsgnj.d fa0, fa0, fa5
211 ; RV64IFDZFH-NEXT: ret
212 ;
213 ; RV32IFZFHMIN-LABEL: fold_promote_d_h:
214 ; RV32IFZFHMIN: # %bb.0:
215 ; RV32IFZFHMIN-NEXT: fmv.x.h a2, fa0
216 ; RV32IFZFHMIN-NEXT: lui a3, 8
217 ; RV32IFZFHMIN-NEXT: and a2, a2, a3
218 ; RV32IFZFHMIN-NEXT: slli a2, a2, 16
219 ; RV32IFZFHMIN-NEXT: slli a1, a1, 1
220 ; RV32IFZFHMIN-NEXT: srli a1, a1, 1
221 ; RV32IFZFHMIN-NEXT: or a1, a1, a2
222 ; RV32IFZFHMIN-NEXT: ret
223 ;
224 ; RV32IFDZFHMIN-LABEL: fold_promote_d_h:
225 ; RV32IFDZFHMIN: # %bb.0:
226 ; RV32IFDZFHMIN-NEXT: fcvt.d.h fa5, fa1
227 ; RV32IFDZFHMIN-NEXT: fsgnj.d fa0, fa0, fa5
228 ; RV32IFDZFHMIN-NEXT: ret
229 ;
230 ; RV64IFDZFHMIN-LABEL: fold_promote_d_h:
231 ; RV64IFDZFHMIN: # %bb.0:
232 ; RV64IFDZFHMIN-NEXT: fcvt.d.h fa5, fa1
233 ; RV64IFDZFHMIN-NEXT: fsgnj.d fa0, fa0, fa5
234 ; RV64IFDZFHMIN-NEXT: ret
235 %c = fpext half %b to double
236 %t = call double @llvm.copysign.f64(double %a, double %c)
237 ret double %t
238 }
240 define float @fold_promote_f_h(float %a, half %b) nounwind {
241 ; RV32I-LABEL: fold_promote_f_h:
242 ; RV32I: # %bb.0:
243 ; RV32I-NEXT: lui a2, 8
244 ; RV32I-NEXT: and a1, a1, a2
245 ; RV32I-NEXT: slli a1, a1, 16
246 ; RV32I-NEXT: slli a0, a0, 1
247 ; RV32I-NEXT: srli a0, a0, 1
248 ; RV32I-NEXT: or a0, a0, a1
249 ; RV32I-NEXT: ret
250 ;
251 ; RV64I-LABEL: fold_promote_f_h:
252 ; RV64I: # %bb.0:
253 ; RV64I-NEXT: lui a2, 8
254 ; RV64I-NEXT: and a1, a1, a2
255 ; RV64I-NEXT: slliw a1, a1, 16
256 ; RV64I-NEXT: slli a0, a0, 33
257 ; RV64I-NEXT: srli a0, a0, 33
258 ; RV64I-NEXT: or a0, a0, a1
259 ; RV64I-NEXT: ret
260 ;
261 ; RV32IF-LABEL: fold_promote_f_h:
262 ; RV32IF: # %bb.0:
263 ; RV32IF-NEXT: addi sp, sp, -16
264 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
265 ; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
266 ; RV32IF-NEXT: fmv.s fs0, fa0
267 ; RV32IF-NEXT: fmv.s fa0, fa1
268 ; RV32IF-NEXT: call __extendhfsf2
269 ; RV32IF-NEXT: fsgnj.s fa0, fs0, fa0
270 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
271 ; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
272 ; RV32IF-NEXT: addi sp, sp, 16
273 ; RV32IF-NEXT: ret
274 ;
275 ; RV32IFD-LABEL: fold_promote_f_h:
276 ; RV32IFD: # %bb.0:
277 ; RV32IFD-NEXT: addi sp, sp, -16
278 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
279 ; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
280 ; RV32IFD-NEXT: fmv.s fs0, fa0
281 ; RV32IFD-NEXT: fmv.s fa0, fa1
282 ; RV32IFD-NEXT: call __extendhfsf2
283 ; RV32IFD-NEXT: fsgnj.s fa0, fs0, fa0
284 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
285 ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
286 ; RV32IFD-NEXT: addi sp, sp, 16
287 ; RV32IFD-NEXT: ret
288 ;
289 ; RV64IFD-LABEL: fold_promote_f_h:
290 ; RV64IFD: # %bb.0:
291 ; RV64IFD-NEXT: addi sp, sp, -16
292 ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
293 ; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
294 ; RV64IFD-NEXT: fmv.s fs0, fa0
295 ; RV64IFD-NEXT: fmv.s fa0, fa1
296 ; RV64IFD-NEXT: call __extendhfsf2
297 ; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0
298 ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
299 ; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
300 ; RV64IFD-NEXT: addi sp, sp, 16
301 ; RV64IFD-NEXT: ret
302 ;
303 ; RV32IFZFH-LABEL: fold_promote_f_h:
304 ; RV32IFZFH: # %bb.0:
305 ; RV32IFZFH-NEXT: fcvt.s.h fa5, fa1
306 ; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa5
307 ; RV32IFZFH-NEXT: ret
308 ;
309 ; RV32IFDZFH-LABEL: fold_promote_f_h:
310 ; RV32IFDZFH: # %bb.0:
311 ; RV32IFDZFH-NEXT: fcvt.s.h fa5, fa1
312 ; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa5
313 ; RV32IFDZFH-NEXT: ret
314 ;
315 ; RV64IFDZFH-LABEL: fold_promote_f_h:
316 ; RV64IFDZFH: # %bb.0:
317 ; RV64IFDZFH-NEXT: fcvt.s.h fa5, fa1
318 ; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa5
319 ; RV64IFDZFH-NEXT: ret
320 ;
321 ; RV32IFZFHMIN-LABEL: fold_promote_f_h:
322 ; RV32IFZFHMIN: # %bb.0:
323 ; RV32IFZFHMIN-NEXT: fcvt.s.h fa5, fa1
324 ; RV32IFZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
325 ; RV32IFZFHMIN-NEXT: ret
326 ;
327 ; RV32IFDZFHMIN-LABEL: fold_promote_f_h:
328 ; RV32IFDZFHMIN: # %bb.0:
329 ; RV32IFDZFHMIN-NEXT: fcvt.s.h fa5, fa1
330 ; RV32IFDZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
331 ; RV32IFDZFHMIN-NEXT: ret
332 ;
333 ; RV64IFDZFHMIN-LABEL: fold_promote_f_h:
334 ; RV64IFDZFHMIN: # %bb.0:
335 ; RV64IFDZFHMIN-NEXT: fcvt.s.h fa5, fa1
336 ; RV64IFDZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
337 ; RV64IFDZFHMIN-NEXT: ret
338 %c = fpext half %b to float
339 %t = call float @llvm.copysign.f32(float %a, float %c)
340 ret float %t
341 }
343 define float @fold_demote_s_d(float %a, double %b) nounwind {
344 ; RV32I-LABEL: fold_demote_s_d:
345 ; RV32I: # %bb.0:
346 ; RV32I-NEXT: lui a1, 524288
347 ; RV32I-NEXT: and a1, a2, a1
348 ; RV32I-NEXT: slli a0, a0, 1
349 ; RV32I-NEXT: srli a0, a0, 1
350 ; RV32I-NEXT: or a0, a0, a1
351 ; RV32I-NEXT: ret
352 ;
353 ; RV64I-LABEL: fold_demote_s_d:
354 ; RV64I: # %bb.0:
355 ; RV64I-NEXT: slli a0, a0, 33
356 ; RV64I-NEXT: srli a0, a0, 33
357 ; RV64I-NEXT: srli a1, a1, 63
358 ; RV64I-NEXT: slli a1, a1, 63
359 ; RV64I-NEXT: srli a1, a1, 32
360 ; RV64I-NEXT: or a0, a0, a1
361 ; RV64I-NEXT: ret
362 ;
363 ; RV32IF-LABEL: fold_demote_s_d:
364 ; RV32IF: # %bb.0:
365 ; RV32IF-NEXT: fmv.w.x fa5, a1
366 ; RV32IF-NEXT: fsgnj.s fa0, fa0, fa5
367 ; RV32IF-NEXT: ret
368 ;
369 ; RV32IFD-LABEL: fold_demote_s_d:
370 ; RV32IFD: # %bb.0:
371 ; RV32IFD-NEXT: fcvt.s.d fa5, fa1
372 ; RV32IFD-NEXT: fsgnj.s fa0, fa0, fa5
373 ; RV32IFD-NEXT: ret
374 ;
375 ; RV64IFD-LABEL: fold_demote_s_d:
376 ; RV64IFD: # %bb.0:
377 ; RV64IFD-NEXT: fcvt.s.d fa5, fa1
378 ; RV64IFD-NEXT: fsgnj.s fa0, fa0, fa5
379 ; RV64IFD-NEXT: ret
380 ;
381 ; RV32IFZFH-LABEL: fold_demote_s_d:
382 ; RV32IFZFH: # %bb.0:
383 ; RV32IFZFH-NEXT: fmv.w.x fa5, a1
384 ; RV32IFZFH-NEXT: fsgnj.s fa0, fa0, fa5
385 ; RV32IFZFH-NEXT: ret
386 ;
387 ; RV32IFDZFH-LABEL: fold_demote_s_d:
388 ; RV32IFDZFH: # %bb.0:
389 ; RV32IFDZFH-NEXT: fcvt.s.d fa5, fa1
390 ; RV32IFDZFH-NEXT: fsgnj.s fa0, fa0, fa5
391 ; RV32IFDZFH-NEXT: ret
392 ;
393 ; RV64IFDZFH-LABEL: fold_demote_s_d:
394 ; RV64IFDZFH: # %bb.0:
395 ; RV64IFDZFH-NEXT: fcvt.s.d fa5, fa1
396 ; RV64IFDZFH-NEXT: fsgnj.s fa0, fa0, fa5
397 ; RV64IFDZFH-NEXT: ret
398 ;
399 ; RV32IFZFHMIN-LABEL: fold_demote_s_d:
400 ; RV32IFZFHMIN: # %bb.0:
401 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a1
402 ; RV32IFZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
403 ; RV32IFZFHMIN-NEXT: ret
404 ;
405 ; RV32IFDZFHMIN-LABEL: fold_demote_s_d:
406 ; RV32IFDZFHMIN: # %bb.0:
407 ; RV32IFDZFHMIN-NEXT: fcvt.s.d fa5, fa1
408 ; RV32IFDZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
409 ; RV32IFDZFHMIN-NEXT: ret
410 ;
411 ; RV64IFDZFHMIN-LABEL: fold_demote_s_d:
412 ; RV64IFDZFHMIN: # %bb.0:
413 ; RV64IFDZFHMIN-NEXT: fcvt.s.d fa5, fa1
414 ; RV64IFDZFHMIN-NEXT: fsgnj.s fa0, fa0, fa5
415 ; RV64IFDZFHMIN-NEXT: ret
416 %c = fptrunc double %b to float
417 %t = call float @llvm.copysign.f32(float %a, float %c)
418 ret float %t
419 }
421 define half @fold_demote_h_s(half %a, float %b) nounwind {
422 ; RV32I-LABEL: fold_demote_h_s:
423 ; RV32I: # %bb.0:
424 ; RV32I-NEXT: lui a2, 524288
425 ; RV32I-NEXT: and a1, a1, a2
426 ; RV32I-NEXT: srli a1, a1, 16
427 ; RV32I-NEXT: slli a0, a0, 17
428 ; RV32I-NEXT: srli a0, a0, 17
429 ; RV32I-NEXT: or a0, a0, a1
430 ; RV32I-NEXT: ret
431 ;
432 ; RV64I-LABEL: fold_demote_h_s:
433 ; RV64I: # %bb.0:
434 ; RV64I-NEXT: srliw a1, a1, 31
435 ; RV64I-NEXT: slli a1, a1, 15
436 ; RV64I-NEXT: slli a0, a0, 49
437 ; RV64I-NEXT: srli a0, a0, 49
438 ; RV64I-NEXT: or a0, a0, a1
439 ; RV64I-NEXT: ret
440 ;
441 ; RV32IF-LABEL: fold_demote_h_s:
442 ; RV32IF: # %bb.0:
443 ; RV32IF-NEXT: fmv.x.w a0, fa0
444 ; RV32IF-NEXT: fmv.x.w a1, fa1
445 ; RV32IF-NEXT: lui a2, 524288
446 ; RV32IF-NEXT: and a1, a1, a2
447 ; RV32IF-NEXT: srli a1, a1, 16
448 ; RV32IF-NEXT: slli a0, a0, 17
449 ; RV32IF-NEXT: srli a0, a0, 17
450 ; RV32IF-NEXT: or a0, a0, a1
451 ; RV32IF-NEXT: lui a1, 1048560
452 ; RV32IF-NEXT: or a0, a0, a1
453 ; RV32IF-NEXT: fmv.w.x fa0, a0
454 ; RV32IF-NEXT: ret
455 ;
456 ; RV32IFD-LABEL: fold_demote_h_s:
457 ; RV32IFD: # %bb.0:
458 ; RV32IFD-NEXT: fmv.x.w a0, fa0
459 ; RV32IFD-NEXT: fmv.x.w a1, fa1
460 ; RV32IFD-NEXT: lui a2, 524288
461 ; RV32IFD-NEXT: and a1, a1, a2
462 ; RV32IFD-NEXT: srli a1, a1, 16
463 ; RV32IFD-NEXT: slli a0, a0, 17
464 ; RV32IFD-NEXT: srli a0, a0, 17
465 ; RV32IFD-NEXT: or a0, a0, a1
466 ; RV32IFD-NEXT: lui a1, 1048560
467 ; RV32IFD-NEXT: or a0, a0, a1
468 ; RV32IFD-NEXT: fmv.w.x fa0, a0
469 ; RV32IFD-NEXT: ret
470 ;
471 ; RV64IFD-LABEL: fold_demote_h_s:
472 ; RV64IFD: # %bb.0:
473 ; RV64IFD-NEXT: fmv.x.w a0, fa0
474 ; RV64IFD-NEXT: fmv.x.w a1, fa1
475 ; RV64IFD-NEXT: lui a2, 524288
476 ; RV64IFD-NEXT: and a1, a1, a2
477 ; RV64IFD-NEXT: srli a1, a1, 16
478 ; RV64IFD-NEXT: slli a0, a0, 49
479 ; RV64IFD-NEXT: srli a0, a0, 49
480 ; RV64IFD-NEXT: or a0, a0, a1
481 ; RV64IFD-NEXT: lui a1, 1048560
482 ; RV64IFD-NEXT: or a0, a0, a1
483 ; RV64IFD-NEXT: fmv.w.x fa0, a0
484 ; RV64IFD-NEXT: ret
485 ;
486 ; RV32IFZFH-LABEL: fold_demote_h_s:
487 ; RV32IFZFH: # %bb.0:
488 ; RV32IFZFH-NEXT: fcvt.h.s fa5, fa1
489 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa5
490 ; RV32IFZFH-NEXT: ret
491 ;
492 ; RV32IFDZFH-LABEL: fold_demote_h_s:
493 ; RV32IFDZFH: # %bb.0:
494 ; RV32IFDZFH-NEXT: fcvt.h.s fa5, fa1
495 ; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa5
496 ; RV32IFDZFH-NEXT: ret
497 ;
498 ; RV64IFDZFH-LABEL: fold_demote_h_s:
499 ; RV64IFDZFH: # %bb.0:
500 ; RV64IFDZFH-NEXT: fcvt.h.s fa5, fa1
501 ; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa5
502 ; RV64IFDZFH-NEXT: ret
503 ;
504 ; RV32IFZFHMIN-LABEL: fold_demote_h_s:
505 ; RV32IFZFHMIN: # %bb.0:
506 ; RV32IFZFHMIN-NEXT: addi sp, sp, -16
507 ; RV32IFZFHMIN-NEXT: fsh fa0, 12(sp)
508 ; RV32IFZFHMIN-NEXT: fmv.x.w a0, fa1
509 ; RV32IFZFHMIN-NEXT: lbu a1, 13(sp)
510 ; RV32IFZFHMIN-NEXT: lui a2, 524288
511 ; RV32IFZFHMIN-NEXT: and a0, a0, a2
512 ; RV32IFZFHMIN-NEXT: srli a0, a0, 24
513 ; RV32IFZFHMIN-NEXT: andi a1, a1, 127
514 ; RV32IFZFHMIN-NEXT: or a0, a1, a0
515 ; RV32IFZFHMIN-NEXT: sb a0, 13(sp)
516 ; RV32IFZFHMIN-NEXT: flh fa0, 12(sp)
517 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
518 ; RV32IFZFHMIN-NEXT: ret
519 ;
520 ; RV32IFDZFHMIN-LABEL: fold_demote_h_s:
521 ; RV32IFDZFHMIN: # %bb.0:
522 ; RV32IFDZFHMIN-NEXT: addi sp, sp, -16
523 ; RV32IFDZFHMIN-NEXT: fsh fa0, 12(sp)
524 ; RV32IFDZFHMIN-NEXT: fmv.x.w a0, fa1
525 ; RV32IFDZFHMIN-NEXT: lbu a1, 13(sp)
526 ; RV32IFDZFHMIN-NEXT: lui a2, 524288
527 ; RV32IFDZFHMIN-NEXT: and a0, a0, a2
528 ; RV32IFDZFHMIN-NEXT: srli a0, a0, 24
529 ; RV32IFDZFHMIN-NEXT: andi a1, a1, 127
530 ; RV32IFDZFHMIN-NEXT: or a0, a1, a0
531 ; RV32IFDZFHMIN-NEXT: sb a0, 13(sp)
532 ; RV32IFDZFHMIN-NEXT: flh fa0, 12(sp)
533 ; RV32IFDZFHMIN-NEXT: addi sp, sp, 16
534 ; RV32IFDZFHMIN-NEXT: ret
535 ;
536 ; RV64IFDZFHMIN-LABEL: fold_demote_h_s:
537 ; RV64IFDZFHMIN: # %bb.0:
538 ; RV64IFDZFHMIN-NEXT: addi sp, sp, -16
539 ; RV64IFDZFHMIN-NEXT: fsw fa1, 8(sp)
540 ; RV64IFDZFHMIN-NEXT: fsh fa0, 0(sp)
541 ; RV64IFDZFHMIN-NEXT: lbu a0, 11(sp)
542 ; RV64IFDZFHMIN-NEXT: lbu a1, 1(sp)
543 ; RV64IFDZFHMIN-NEXT: andi a0, a0, 128
544 ; RV64IFDZFHMIN-NEXT: andi a1, a1, 127
545 ; RV64IFDZFHMIN-NEXT: or a0, a1, a0
546 ; RV64IFDZFHMIN-NEXT: sb a0, 1(sp)
547 ; RV64IFDZFHMIN-NEXT: flh fa0, 0(sp)
548 ; RV64IFDZFHMIN-NEXT: addi sp, sp, 16
549 ; RV64IFDZFHMIN-NEXT: ret
550 %c = fptrunc float %b to half
551 %t = call half @llvm.copysign.f16(half %a, half %c)
552 ret half %t
553 }
555 define half @fold_demote_h_d(half %a, double %b) nounwind {
556 ; RV32I-LABEL: fold_demote_h_d:
557 ; RV32I: # %bb.0:
558 ; RV32I-NEXT: lui a1, 524288
559 ; RV32I-NEXT: and a1, a2, a1
560 ; RV32I-NEXT: srli a1, a1, 16
561 ; RV32I-NEXT: slli a0, a0, 17
562 ; RV32I-NEXT: srli a0, a0, 17
563 ; RV32I-NEXT: or a0, a0, a1
564 ; RV32I-NEXT: ret
565 ;
566 ; RV64I-LABEL: fold_demote_h_d:
567 ; RV64I: # %bb.0:
568 ; RV64I-NEXT: slli a0, a0, 49
569 ; RV64I-NEXT: srli a0, a0, 49
570 ; RV64I-NEXT: srli a1, a1, 63
571 ; RV64I-NEXT: slli a1, a1, 63
572 ; RV64I-NEXT: srli a1, a1, 48
573 ; RV64I-NEXT: or a0, a0, a1
574 ; RV64I-NEXT: ret
575 ;
576 ; RV32IF-LABEL: fold_demote_h_d:
577 ; RV32IF: # %bb.0:
578 ; RV32IF-NEXT: fmv.x.w a0, fa0
579 ; RV32IF-NEXT: lui a2, 524288
580 ; RV32IF-NEXT: and a1, a1, a2
581 ; RV32IF-NEXT: srli a1, a1, 16
582 ; RV32IF-NEXT: slli a0, a0, 17
583 ; RV32IF-NEXT: srli a0, a0, 17
584 ; RV32IF-NEXT: or a0, a0, a1
585 ; RV32IF-NEXT: lui a1, 1048560
586 ; RV32IF-NEXT: or a0, a0, a1
587 ; RV32IF-NEXT: fmv.w.x fa0, a0
588 ; RV32IF-NEXT: ret
589 ;
590 ; RV32IFD-LABEL: fold_demote_h_d:
591 ; RV32IFD: # %bb.0:
592 ; RV32IFD-NEXT: addi sp, sp, -16
593 ; RV32IFD-NEXT: fsd fa1, 8(sp)
594 ; RV32IFD-NEXT: lw a0, 12(sp)
595 ; RV32IFD-NEXT: fmv.x.w a1, fa0
596 ; RV32IFD-NEXT: lui a2, 524288
597 ; RV32IFD-NEXT: and a0, a0, a2
598 ; RV32IFD-NEXT: srli a0, a0, 16
599 ; RV32IFD-NEXT: slli a1, a1, 17
600 ; RV32IFD-NEXT: srli a1, a1, 17
601 ; RV32IFD-NEXT: lui a2, 1048560
602 ; RV32IFD-NEXT: or a1, a1, a2
603 ; RV32IFD-NEXT: or a0, a1, a0
604 ; RV32IFD-NEXT: fmv.w.x fa0, a0
605 ; RV32IFD-NEXT: addi sp, sp, 16
606 ; RV32IFD-NEXT: ret
607 ;
608 ; RV64IFD-LABEL: fold_demote_h_d:
609 ; RV64IFD: # %bb.0:
610 ; RV64IFD-NEXT: fmv.x.d a0, fa1
611 ; RV64IFD-NEXT: fmv.x.w a1, fa0
612 ; RV64IFD-NEXT: slli a1, a1, 49
613 ; RV64IFD-NEXT: srli a1, a1, 49
614 ; RV64IFD-NEXT: srli a0, a0, 63
615 ; RV64IFD-NEXT: slli a0, a0, 63
616 ; RV64IFD-NEXT: srli a0, a0, 48
617 ; RV64IFD-NEXT: lui a2, 1048560
618 ; RV64IFD-NEXT: or a1, a1, a2
619 ; RV64IFD-NEXT: or a0, a1, a0
620 ; RV64IFD-NEXT: fmv.w.x fa0, a0
621 ; RV64IFD-NEXT: ret
622 ;
623 ; RV32IFZFH-LABEL: fold_demote_h_d:
624 ; RV32IFZFH: # %bb.0:
625 ; RV32IFZFH-NEXT: srli a1, a1, 16
626 ; RV32IFZFH-NEXT: fmv.h.x fa5, a1
627 ; RV32IFZFH-NEXT: fsgnj.h fa0, fa0, fa5
628 ; RV32IFZFH-NEXT: ret
629 ;
630 ; RV32IFDZFH-LABEL: fold_demote_h_d:
631 ; RV32IFDZFH: # %bb.0:
632 ; RV32IFDZFH-NEXT: fcvt.h.d fa5, fa1
633 ; RV32IFDZFH-NEXT: fsgnj.h fa0, fa0, fa5
634 ; RV32IFDZFH-NEXT: ret
635 ;
636 ; RV64IFDZFH-LABEL: fold_demote_h_d:
637 ; RV64IFDZFH: # %bb.0:
638 ; RV64IFDZFH-NEXT: fcvt.h.d fa5, fa1
639 ; RV64IFDZFH-NEXT: fsgnj.h fa0, fa0, fa5
640 ; RV64IFDZFH-NEXT: ret
641 ;
642 ; RV32IFZFHMIN-LABEL: fold_demote_h_d:
643 ; RV32IFZFHMIN: # %bb.0:
644 ; RV32IFZFHMIN-NEXT: addi sp, sp, -16
645 ; RV32IFZFHMIN-NEXT: fsh fa0, 8(sp)
646 ; RV32IFZFHMIN-NEXT: srli a1, a1, 16
647 ; RV32IFZFHMIN-NEXT: fmv.h.x fa5, a1
648 ; RV32IFZFHMIN-NEXT: fsh fa5, 12(sp)
649 ; RV32IFZFHMIN-NEXT: lbu a0, 9(sp)
650 ; RV32IFZFHMIN-NEXT: lbu a1, 13(sp)
651 ; RV32IFZFHMIN-NEXT: andi a0, a0, 127
652 ; RV32IFZFHMIN-NEXT: andi a1, a1, 128
653 ; RV32IFZFHMIN-NEXT: or a0, a0, a1
654 ; RV32IFZFHMIN-NEXT: sb a0, 9(sp)
655 ; RV32IFZFHMIN-NEXT: flh fa0, 8(sp)
656 ; RV32IFZFHMIN-NEXT: addi sp, sp, 16
657 ; RV32IFZFHMIN-NEXT: ret
658 ;
659 ; RV32IFDZFHMIN-LABEL: fold_demote_h_d:
660 ; RV32IFDZFHMIN: # %bb.0:
661 ; RV32IFDZFHMIN-NEXT: addi sp, sp, -16
662 ; RV32IFDZFHMIN-NEXT: fsd fa1, 8(sp)
663 ; RV32IFDZFHMIN-NEXT: fsh fa0, 4(sp)
664 ; RV32IFDZFHMIN-NEXT: lbu a0, 15(sp)
665 ; RV32IFDZFHMIN-NEXT: lbu a1, 5(sp)
666 ; RV32IFDZFHMIN-NEXT: andi a0, a0, 128
667 ; RV32IFDZFHMIN-NEXT: andi a1, a1, 127
668 ; RV32IFDZFHMIN-NEXT: or a0, a1, a0
669 ; RV32IFDZFHMIN-NEXT: sb a0, 5(sp)
670 ; RV32IFDZFHMIN-NEXT: flh fa0, 4(sp)
671 ; RV32IFDZFHMIN-NEXT: addi sp, sp, 16
672 ; RV32IFDZFHMIN-NEXT: ret
673 ;
674 ; RV64IFDZFHMIN-LABEL: fold_demote_h_d:
675 ; RV64IFDZFHMIN: # %bb.0:
676 ; RV64IFDZFHMIN-NEXT: addi sp, sp, -16
677 ; RV64IFDZFHMIN-NEXT: fsh fa0, 8(sp)
678 ; RV64IFDZFHMIN-NEXT: lbu a0, 9(sp)
679 ; RV64IFDZFHMIN-NEXT: andi a0, a0, 127
680 ; RV64IFDZFHMIN-NEXT: fmv.x.d a1, fa1
681 ; RV64IFDZFHMIN-NEXT: srli a1, a1, 63
682 ; RV64IFDZFHMIN-NEXT: slli a1, a1, 63
683 ; RV64IFDZFHMIN-NEXT: srli a1, a1, 56
684 ; RV64IFDZFHMIN-NEXT: or a0, a0, a1
685 ; RV64IFDZFHMIN-NEXT: sb a0, 9(sp)
686 ; RV64IFDZFHMIN-NEXT: flh fa0, 8(sp)
687 ; RV64IFDZFHMIN-NEXT: addi sp, sp, 16
688 ; RV64IFDZFHMIN-NEXT: ret
689 %c = fptrunc double %b to half
690 %t = call half @llvm.copysign.f16(half %a, half %c)
691 ret half %t
692 }