| blob | d46256b12052e0801f6719820258e1f0a02e90c2 |
1 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2 ; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs < %s \
3 ; RUN: | FileCheck -check-prefix=RV32IFD %s
4 ; RUN: llc -mtriple=riscv32 -mattr=+zdinx -target-abi=ilp32 -verify-machineinstrs < %s \
5 ; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
7 ; Basic correctness checks for calling convention lowering for RV32D. This can
8 ; be somewhat error-prone for soft-float RV32D due to the fact that f64 is legal
9 ; but i64 is not, and there is no instruction to move values directly between
10 ; the GPRs and 64-bit FPRs.
12 define double @callee_double_inreg(double %a, double %b) nounwind {
13 ; RV32IFD-LABEL: callee_double_inreg:
14 ; RV32IFD: # %bb.0:
15 ; RV32IFD-NEXT: addi sp, sp, -16
16 ; RV32IFD-NEXT: sw a2, 8(sp)
17 ; RV32IFD-NEXT: sw a3, 12(sp)
18 ; RV32IFD-NEXT: fld fa5, 8(sp)
19 ; RV32IFD-NEXT: sw a0, 8(sp)
20 ; RV32IFD-NEXT: sw a1, 12(sp)
21 ; RV32IFD-NEXT: fld fa4, 8(sp)
22 ; RV32IFD-NEXT: fadd.d fa5, fa4, fa5
23 ; RV32IFD-NEXT: fsd fa5, 8(sp)
24 ; RV32IFD-NEXT: lw a0, 8(sp)
25 ; RV32IFD-NEXT: lw a1, 12(sp)
26 ; RV32IFD-NEXT: addi sp, sp, 16
27 ; RV32IFD-NEXT: ret
28 ;
29 ; RV32IZFINXZDINX-LABEL: callee_double_inreg:
30 ; RV32IZFINXZDINX: # %bb.0:
31 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
32 ; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
33 ; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
34 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
35 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
36 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
37 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
38 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
39 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
40 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, a2
41 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
42 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
43 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
44 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
45 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
46 ; RV32IZFINXZDINX-NEXT: ret
47 %1 = fadd double %a, %b
48 ret double %1
49 }
51 ; TODO: code quality for loading and then passing f64 constants is poor.
53 define double @caller_double_inreg() nounwind {
54 ; RV32IFD-LABEL: caller_double_inreg:
55 ; RV32IFD: # %bb.0:
56 ; RV32IFD-NEXT: addi sp, sp, -16
57 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
58 ; RV32IFD-NEXT: lui a0, 262236
59 ; RV32IFD-NEXT: addi a1, a0, 655
60 ; RV32IFD-NEXT: lui a0, 377487
61 ; RV32IFD-NEXT: addi a0, a0, 1475
62 ; RV32IFD-NEXT: lui a2, 262364
63 ; RV32IFD-NEXT: addi a3, a2, 655
64 ; RV32IFD-NEXT: mv a2, a0
65 ; RV32IFD-NEXT: call callee_double_inreg
66 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
67 ; RV32IFD-NEXT: addi sp, sp, 16
68 ; RV32IFD-NEXT: ret
69 ;
70 ; RV32IZFINXZDINX-LABEL: caller_double_inreg:
71 ; RV32IZFINXZDINX: # %bb.0:
72 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
73 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
74 ; RV32IZFINXZDINX-NEXT: lui a0, 262236
75 ; RV32IZFINXZDINX-NEXT: addi a1, a0, 655
76 ; RV32IZFINXZDINX-NEXT: lui a0, 377487
77 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 1475
78 ; RV32IZFINXZDINX-NEXT: lui a2, 262364
79 ; RV32IZFINXZDINX-NEXT: addi a3, a2, 655
80 ; RV32IZFINXZDINX-NEXT: mv a2, a0
81 ; RV32IZFINXZDINX-NEXT: call callee_double_inreg
82 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
83 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
84 ; RV32IZFINXZDINX-NEXT: ret
85 %1 = call double @callee_double_inreg(double 2.720000e+00, double 3.720000e+00)
86 ret double %1
87 }
89 define double @callee_double_split_reg_stack(i32 %a, i64 %b, i64 %c, double %d, double %e) nounwind {
90 ; RV32IFD-LABEL: callee_double_split_reg_stack:
91 ; RV32IFD: # %bb.0:
92 ; RV32IFD-NEXT: addi sp, sp, -16
93 ; RV32IFD-NEXT: lw a0, 16(sp)
94 ; RV32IFD-NEXT: sw a7, 8(sp)
95 ; RV32IFD-NEXT: sw a0, 12(sp)
96 ; RV32IFD-NEXT: fld fa5, 8(sp)
97 ; RV32IFD-NEXT: sw a5, 8(sp)
98 ; RV32IFD-NEXT: sw a6, 12(sp)
99 ; RV32IFD-NEXT: fld fa4, 8(sp)
100 ; RV32IFD-NEXT: fadd.d fa5, fa4, fa5
101 ; RV32IFD-NEXT: fsd fa5, 8(sp)
102 ; RV32IFD-NEXT: lw a0, 8(sp)
103 ; RV32IFD-NEXT: lw a1, 12(sp)
104 ; RV32IFD-NEXT: addi sp, sp, 16
105 ; RV32IFD-NEXT: ret
106 ;
107 ; RV32IZFINXZDINX-LABEL: callee_double_split_reg_stack:
108 ; RV32IZFINXZDINX: # %bb.0:
109 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
110 ; RV32IZFINXZDINX-NEXT: lw a0, 16(sp)
111 ; RV32IZFINXZDINX-NEXT: sw a7, 8(sp)
112 ; RV32IZFINXZDINX-NEXT: sw a0, 12(sp)
113 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
114 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
115 ; RV32IZFINXZDINX-NEXT: sw a5, 8(sp)
116 ; RV32IZFINXZDINX-NEXT: sw a6, 12(sp)
117 ; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
118 ; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
119 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
120 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
121 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
122 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
123 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
124 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
125 ; RV32IZFINXZDINX-NEXT: ret
126 %1 = fadd double %d, %e
127 ret double %1
128 }
130 define double @caller_double_split_reg_stack() nounwind {
131 ; RV32IFD-LABEL: caller_double_split_reg_stack:
132 ; RV32IFD: # %bb.0:
133 ; RV32IFD-NEXT: addi sp, sp, -16
134 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
135 ; RV32IFD-NEXT: lui a0, 262510
136 ; RV32IFD-NEXT: addi a2, a0, 327
137 ; RV32IFD-NEXT: lui a0, 262446
138 ; RV32IFD-NEXT: addi a6, a0, 327
139 ; RV32IFD-NEXT: lui a0, 713032
140 ; RV32IFD-NEXT: addi a5, a0, -1311
141 ; RV32IFD-NEXT: li a0, 1
142 ; RV32IFD-NEXT: li a1, 2
143 ; RV32IFD-NEXT: li a3, 3
144 ; RV32IFD-NEXT: sw a2, 0(sp)
145 ; RV32IFD-NEXT: li a2, 0
146 ; RV32IFD-NEXT: li a4, 0
147 ; RV32IFD-NEXT: mv a7, a5
148 ; RV32IFD-NEXT: call callee_double_split_reg_stack
149 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
150 ; RV32IFD-NEXT: addi sp, sp, 16
151 ; RV32IFD-NEXT: ret
152 ;
153 ; RV32IZFINXZDINX-LABEL: caller_double_split_reg_stack:
154 ; RV32IZFINXZDINX: # %bb.0:
155 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
156 ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
157 ; RV32IZFINXZDINX-NEXT: lui a0, 262510
158 ; RV32IZFINXZDINX-NEXT: addi a2, a0, 327
159 ; RV32IZFINXZDINX-NEXT: lui a0, 262446
160 ; RV32IZFINXZDINX-NEXT: addi a6, a0, 327
161 ; RV32IZFINXZDINX-NEXT: lui a0, 713032
162 ; RV32IZFINXZDINX-NEXT: addi a5, a0, -1311
163 ; RV32IZFINXZDINX-NEXT: li a0, 1
164 ; RV32IZFINXZDINX-NEXT: li a1, 2
165 ; RV32IZFINXZDINX-NEXT: li a3, 3
166 ; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
167 ; RV32IZFINXZDINX-NEXT: li a2, 0
168 ; RV32IZFINXZDINX-NEXT: li a4, 0
169 ; RV32IZFINXZDINX-NEXT: mv a7, a5
170 ; RV32IZFINXZDINX-NEXT: call callee_double_split_reg_stack
171 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
172 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
173 ; RV32IZFINXZDINX-NEXT: ret
174 %1 = call double @callee_double_split_reg_stack(i32 1, i64 2, i64 3, double 4.72, double 5.72)
175 ret double %1
176 }
178 define double @callee_double_stack(i64 %a, i64 %b, i64 %c, i64 %d, double %e, double %f) nounwind {
179 ; RV32IFD-LABEL: callee_double_stack:
180 ; RV32IFD: # %bb.0:
181 ; RV32IFD-NEXT: addi sp, sp, -16
182 ; RV32IFD-NEXT: fld fa5, 24(sp)
183 ; RV32IFD-NEXT: fld fa4, 16(sp)
184 ; RV32IFD-NEXT: fadd.d fa5, fa4, fa5
185 ; RV32IFD-NEXT: fsd fa5, 8(sp)
186 ; RV32IFD-NEXT: lw a0, 8(sp)
187 ; RV32IFD-NEXT: lw a1, 12(sp)
188 ; RV32IFD-NEXT: addi sp, sp, 16
189 ; RV32IFD-NEXT: ret
190 ;
191 ; RV32IZFINXZDINX-LABEL: callee_double_stack:
192 ; RV32IZFINXZDINX: # %bb.0:
193 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
194 ; RV32IZFINXZDINX-NEXT: lw a0, 24(sp)
195 ; RV32IZFINXZDINX-NEXT: lw a1, 28(sp)
196 ; RV32IZFINXZDINX-NEXT: lw a2, 16(sp)
197 ; RV32IZFINXZDINX-NEXT: lw a3, 20(sp)
198 ; RV32IZFINXZDINX-NEXT: fadd.d a0, a2, a0
199 ; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
200 ; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
201 ; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
202 ; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
203 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
204 ; RV32IZFINXZDINX-NEXT: ret
205 %1 = fadd double %e, %f
206 ret double %1
207 }
209 define double @caller_double_stack() nounwind {
210 ; RV32IFD-LABEL: caller_double_stack:
211 ; RV32IFD: # %bb.0:
212 ; RV32IFD-NEXT: addi sp, sp, -32
213 ; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
214 ; RV32IFD-NEXT: lui a0, 262510
215 ; RV32IFD-NEXT: addi a0, a0, 327
216 ; RV32IFD-NEXT: sw a0, 4(sp)
217 ; RV32IFD-NEXT: lui a0, 713032
218 ; RV32IFD-NEXT: addi a1, a0, -1311
219 ; RV32IFD-NEXT: sw a1, 0(sp)
220 ; RV32IFD-NEXT: lui a0, 262574
221 ; RV32IFD-NEXT: addi a0, a0, 327
222 ; RV32IFD-NEXT: sw a0, 12(sp)
223 ; RV32IFD-NEXT: li a0, 1
224 ; RV32IFD-NEXT: li a2, 2
225 ; RV32IFD-NEXT: li a4, 3
226 ; RV32IFD-NEXT: li a6, 4
227 ; RV32IFD-NEXT: sw a1, 8(sp)
228 ; RV32IFD-NEXT: li a1, 0
229 ; RV32IFD-NEXT: li a3, 0
230 ; RV32IFD-NEXT: li a5, 0
231 ; RV32IFD-NEXT: li a7, 0
232 ; RV32IFD-NEXT: call callee_double_stack
233 ; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
234 ; RV32IFD-NEXT: addi sp, sp, 32
235 ; RV32IFD-NEXT: ret
236 ;
237 ; RV32IZFINXZDINX-LABEL: caller_double_stack:
238 ; RV32IZFINXZDINX: # %bb.0:
239 ; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
240 ; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
241 ; RV32IZFINXZDINX-NEXT: lui a0, 262510
242 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 327
243 ; RV32IZFINXZDINX-NEXT: sw a0, 4(sp)
244 ; RV32IZFINXZDINX-NEXT: lui a0, 713032
245 ; RV32IZFINXZDINX-NEXT: addi a1, a0, -1311
246 ; RV32IZFINXZDINX-NEXT: sw a1, 0(sp)
247 ; RV32IZFINXZDINX-NEXT: lui a0, 262574
248 ; RV32IZFINXZDINX-NEXT: addi a0, a0, 327
249 ; RV32IZFINXZDINX-NEXT: sw a0, 12(sp)
250 ; RV32IZFINXZDINX-NEXT: li a0, 1
251 ; RV32IZFINXZDINX-NEXT: li a2, 2
252 ; RV32IZFINXZDINX-NEXT: li a4, 3
253 ; RV32IZFINXZDINX-NEXT: li a6, 4
254 ; RV32IZFINXZDINX-NEXT: sw a1, 8(sp)
255 ; RV32IZFINXZDINX-NEXT: li a1, 0
256 ; RV32IZFINXZDINX-NEXT: li a3, 0
257 ; RV32IZFINXZDINX-NEXT: li a5, 0
258 ; RV32IZFINXZDINX-NEXT: li a7, 0
259 ; RV32IZFINXZDINX-NEXT: call callee_double_stack
260 ; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
261 ; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
262 ; RV32IZFINXZDINX-NEXT: ret
263 %1 = call double @callee_double_stack(i64 1, i64 2, i64 3, i64 4, double 5.72, double 6.72)
264 ret double %1
265 }
267 define double @func_return_double_undef() nounwind {
268 ; RV32IFD-LABEL: func_return_double_undef:
269 ; RV32IFD: # %bb.0:
270 ; RV32IFD-NEXT: ret
271 ;
272 ; RV32IZFINXZDINX-LABEL: func_return_double_undef:
273 ; RV32IZFINXZDINX: # %bb.0:
274 ; RV32IZFINXZDINX-NEXT: ret
275 ret double undef
276 }